CN114743504A

CN114743504A - Pixel circuit, display panel and display device

Info

Publication number: CN114743504A
Application number: CN202210539325.1A
Authority: CN
Inventors: 卢慧玲; 曹培轩; 齐栋宇; 楼均辉; 胡思明
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2022-05-18
Filing date: 2022-05-18
Publication date: 2022-07-12
Anticipated expiration: 2042-05-18
Also published as: CN114743504B

Abstract

The embodiment of the application provides a pixel circuit, a display panel and a display device, the pixel circuit is applied to the pixel drive of the display panel, the display panel is provided with a first display area and a transparent display area, part of the pixel circuit in the first display area is electrically connected with a light-emitting element in the transparent display area, and the pixel circuit comprises: the output end of the driving module is electrically connected with the target node; the control end of the first reset module is electrically connected with the first scanning signal line, the first end of the first reset module is electrically connected with the reference voltage signal line, and the second end of the first reset module is electrically connected with the first pole of the light-emitting element through the first wire; a control end of the switching module is electrically connected with the light-emitting control signal wire, a first end of the switching module is electrically connected with the target node, and a second end of the switching module is connected with the first wiring; in the light emitting stage, the first reset module is turned off, the switching module is turned on, and the driving current is transmitted to the first pole of the light emitting element through the switching module and the first wire. The embodiment of the application can save the wiring space of the first display area.

Description

Pixel circuit, display panel and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a pixel circuit, a display panel and a display device.

Background

With the rapid development of display technology, full-screen display has become the development trend of mobile display devices such as mobile phones.

Current display panels usually have a high pixel density (Pixels Per inc, PPI), and most display devices are configured with front camera modules. In order to realize a full-screen display and simultaneously take account of a front camera, a display region with a low PPI and a partial transparency is usually disposed in the display panel, and this region may be referred to as a transparent display region. In order to improve light transmittance, the transparent display region is generally provided with only light emitting elements, and pixel circuits electrically connected to the light emitting elements in the transparent display region are provided in other regions (referred to as first display regions), and the pixel circuits in the first display regions are electrically connected to the light emitting elements in the transparent display region through wirings.

The inventor of the application finds that the first display area is limited by the existing wiring mode, and the problem that wiring space is insufficient and wiring is difficult to arrange exists in the existing first display area.

Disclosure of Invention

The embodiment of the application provides a pixel circuit, a display panel and a display device, which can save the wiring space of a first display area and facilitate the wiring arrangement of the first display area.

In a first aspect, an embodiment of the present application provides a pixel circuit, where the pixel circuit is applied to pixel driving of a display panel, the display panel has a first display area and a transparent display area in a first direction, the transparent display area includes a light emitting element, and a part of the pixel circuit located in the first display area is electrically connected to the light emitting element in the transparent display area, and the part of the pixel circuit includes: the output end of the driving module is electrically connected with the target node; the control end of the first reset module is electrically connected with the first scanning signal line, the first end of the first reset module is electrically connected with the reference voltage signal line, and the second end of the first reset module is electrically connected with the first pole of the light-emitting element through the first wiring; the control end of the switching module is electrically connected with the light-emitting control signal line, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is electrically connected with the first pole of the light-emitting element through the first wiring; in a light emitting stage, the first reset module is turned off in response to an off level provided by the first scanning signal line, the switching module is turned on in response to an on level provided by the light emitting control signal line, and a driving current output by the driving module is transmitted to the first pole of the light emitting element through the turned-on switching module and the first wire.

According to an embodiment of the first aspect of the present application, the first reset module includes a first transistor, a gate of the first transistor is electrically connected to the first scanning signal line, a first pole of the first transistor is electrically connected to the reference voltage signal line, and a second pole of the first transistor is electrically connected to the first pole of the light emitting element through the first trace; the switching module comprises a second transistor, the grid electrode of the second transistor is electrically connected with the light-emitting control signal line, the first pole of the second transistor is electrically connected with the target node, and the second pole of the second transistor is electrically connected with the first pole of the light-emitting element through the first wiring.

In this way, in the initialization stage, the first transistor is turned on in response to the on level of the first scan signal line, the second transistor is turned off in response to the off level of the light emitting control signal line, and the reference voltage signal transmitted by the reference voltage signal line is transmitted to the first electrode of the light emitting element through the first transistor and the first wire, so that the first electrode of the light emitting element is reset; in the light emitting stage, the first transistor is turned off in response to the turn-off level of the first scanning signal line, the second transistor is turned on in response to the turn-on level of the light emitting control signal line, and the driving current output by the driving module is transmitted to the first pole of the light emitting element through the turned-on second transistor and the first wire to drive the light emitting element to emit light. Like this, can realize through first transistor and second transistor mutually support that time sharing multiplexing is first to be walked the line, promptly through will providing drive current for light emitting element's the first pole in the luminous stage line (can be called the positive pole and walk the line) multiplexing the first line of resetting light emitting element's the first pole, can reduce the quantity that the positive pole was walked the line in the first display area to save the wiring space in first display area, the line of being convenient for in first display area is arranged.

According to any of the embodiments of the first aspect of the present application, the second transistor comprises a double-gate transistor, the double-gate transistor comprises a first sub-transistor and a second sub-transistor which are arranged in series, a gate of the first sub-transistor and a gate of the second sub-transistor are both electrically connected to the light emission control signal line, a first electrode of the first sub-transistor is electrically connected to the target node, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is electrically connected to a first electrode of the light emitting element through the first wire.

In this way, since the second transistor is a dual-gate transistor, the leakage current from the control terminal (i.e., the first node) of the driving module to the first electrode of the light emitting device can be reduced, and the stability and uniformity of the luminance of the light emitting device can be ensured.

According to any of the preceding embodiments of the first aspect of the present application, the pixel circuit may further comprise: the grid electrode of the first light-emitting control transistor is electrically connected with the light-emitting control signal wire, the first pole of the first light-emitting control transistor is electrically connected with the first power supply voltage signal wire, and the second pole of the first light-emitting control transistor is electrically connected with the input end of the driving module; and the grid electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the second light-emitting control transistor is electrically connected with the output end of the driving module, and the second electrode of the second light-emitting control transistor is electrically connected with the target node.

As such, the pixel circuit may further include the first light emission control transistor and the second light emission control transistor, that is, the embodiment of the present application may be applied to various types of pixel circuits such as 7T1C, 7T2C, or 9T 1C.

According to any one of the embodiments of the first aspect of the present application, the first display region includes a main screen region and a transition region, a light transmittance of the transition region is greater than a light transmittance of the main screen region, at least a partial region of the transition region is not provided with a light emitting element, and the pixel circuit is located in the transition region.

Therefore, the transition area is closer to the transparent display area, so that the pixel circuit is arranged in the transition area, the wiring length between the pixel circuit and the light-emitting element in the transparent display area can be shortened, the wiring space of the first display area can be further saved, and the wiring arrangement of the first display area is facilitated.

In a second aspect, embodiments of the present application provide a display panel, which includes a first display region and a transparent display region, the transparent display region including light emitting elements; the first display region includes the pixel circuit as provided in the first aspect, the pixel circuit being electrically connected to the light emitting element in the transparent display region.

According to an embodiment of the second aspect of the present application, the first display region includes a main screen region and a transition region, a light transmittance of the transition region is greater than a light transmittance of the main screen region, at least a partial region of the transition region is not provided with a light emitting element, the transition region is provided with a first pixel circuit and a second pixel circuit, the first pixel circuit is a pixel circuit as provided in the first aspect, and the first pixel circuit and the plurality of second pixel circuits are arranged along a first direction; the second pixel circuit includes: a drive transistor; and the grid electrode of the third light-emitting control transistor is electrically connected with the light-emitting control signal wire, the first pole of the third light-emitting control transistor is electrically connected with the first pole of the driving transistor, and the second pole of the third light-emitting control transistor is electrically connected with the light-emitting element in the transparent display area through a second wiring.

In this way, each first wire can be electrically connected with one row of pixel circuits, and one row of pixel circuits comprises a plurality of pixel circuits, so if the anode wires of the plurality of pixel circuits are all multiplexed with the same first wire, the light emitting elements in the transparent display area can not be driven independently; therefore, the transition area is provided with the second pixel circuits, and each second pixel circuit can be electrically connected with the light-emitting element in the transparent display area through the corresponding second routing line. Therefore, one first pixel circuit and a plurality of second pixel circuits can be arranged in one row of pixel circuits, and independent driving of the light-emitting elements in the transparent display area can be realized while the number of anode wires is reduced.

According to any of the foregoing embodiments of the second aspect of the present application, the transition region includes M second pixel circuits, the M second pixel circuits correspond to the M second routing lines one to one, and the second electrode of the third light-emitting control transistor in each second pixel circuit is electrically connected to the light-emitting element in the transparent display region through the corresponding second routing line.

According to any of the embodiments of the second aspect of the present application, a display panel includes an active layer and a metal layer which are stacked; in at least the transition region, the light emission control signal lines in the metal layer extend in a first direction, and a first portion of the light emission control signal lines overlaps the active layer in a thickness direction of the display panel; the switching module includes a second transistor, and the first portion overlapping the active layer forms a gate of the second transistor.

Therefore, the grid electrode of the second transistor and the light-emitting control signal wire can be prepared by the same process, so that the production process is simplified, and the production cost is reduced.

According to any of the previous embodiments of the second aspect of the present application, the second transistor comprises a double-gate transistor comprising a first sub-transistor and a second sub-transistor arranged in series; the first portion includes first and second sub-portions arranged at intervals, the first sub-portion overlapping the active layer forms a gate of the first sub-transistor, and the second sub-portion overlapping the active layer forms a gate of the second sub-transistor.

In this way, since the second transistor is a dual-gate transistor, the leakage current from the control terminal (i.e., the first node) of the driving module to the first electrode of the light emitting element can be reduced, thereby ensuring the stability and uniformity of the luminance of the light emitting element.

According to any of the embodiments of the second aspect of the present application, a display panel includes an active layer and a metal layer which are stacked; the first scanning signal line positioned in the metal layer comprises a first body part extending along a first direction and a first extending part extending along a second direction, the first body part is electrically connected with the first pixel circuits and the plurality of second pixel circuits which are arranged along the first direction, and the first direction is crossed with the second direction; the first extension part overlaps the active layer in a thickness direction of the display panel; the first reset module includes a first transistor, and the first extension portion overlapping the active layer forms a gate of the first transistor.

Therefore, the grid electrode of the first transistor and the first scanning signal line can be prepared by the same process, so that the production process is simplified, and the production cost is reduced.

According to any of the embodiments of the second aspect of the present application, the main screen area surrounds the transition area, and the first pixel circuits are located on a side of the second pixel circuits of the same row close to the main screen area along the first direction.

Therefore, the first pixel circuit is positioned at the junction of the transition region and the main screen region, namely the first pixel circuit is positioned at the head end of one row of pixel circuits, so that other second pixel circuits in one row of pixel circuits can be closely arranged in a repeating unit, and arrangement of transistors and routing wires in the transition region is facilitated.

In a third aspect, embodiments of the present application provide a display device including the display panel as provided in the second aspect.

The pixel circuit, display panel and display device of this application embodiment, pixel circuit are applied to display panel's pixel drive, and display panel has first display area and transparent display area in the first direction, and transparent display area includes light emitting component, and the light emitting component electricity that is arranged in partial pixel circuit in first display area and transparent display area is connected, and this partial pixel circuit includes: the output end of the driving module is electrically connected with the target node; the control end of the first reset module is electrically connected with the first scanning signal line, the first end of the first reset module is electrically connected with the reference voltage signal line, and the second end of the first reset module is electrically connected with the first pole of the light-emitting element through the first wiring; the control end of the switching module is electrically connected with the light-emitting control signal line, the first end of the switching module is electrically connected with the target node, and the second end of the switching module is electrically connected with the first pole of the light-emitting element through the first wiring; in a light emitting stage, the first reset module is turned off in response to a cut-off level provided by the first scanning signal line, the switching module is turned on in response to a turn-on level provided by the light emitting control signal line, and a driving current output by the driving module is transmitted to the first pole of the light emitting element through the turned-on switching module and the first wire. The first line of this application embodiment through the time sharing multiplex, promptly through will providing drive current for light emitting element's the first utmost point in the luminous stage the line (can be called the positive pole line) multiplex the first line of resetting to light emitting element's the first utmost point, can reduce the quantity of positive pole line in the first display area to save the wiring space in first display area, the line of being convenient for in the first display area arranges.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings may be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a display panel;

fig. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a display panel to which a pixel circuit according to an embodiment of the present disclosure is applied;

fig. 4 is another circuit schematic diagram of a pixel circuit provided in the present application;

fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 6;

fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic view of another structure of a display panel to which a pixel circuit according to an embodiment of the present disclosure is applied;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 11 is a layout of a display panel provided in the embodiment of the present application;

fig. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;

fig. 13 is a partially enlarged view of the first pixel circuit in the layout shown in fig. 11;

fig. 14 is another layout of a display panel provided in the embodiment of the present application;

fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Note that the transistors in the embodiments of the present application are described using P-type transistors as examples, but the transistors are not limited to P-type transistors, and may be replaced with N-type transistors. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

In the embodiments of the present application, the first node and the target node are defined only for convenience of describing the circuit structure, and the first node and the target node are not an actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the related art:

Fig. 1 is a schematic structural diagram of a display panel. As shown in fig. 1, the pixel circuit 100 in the first display area 10 is electrically connected to the anode of the light emitting element in the transparent display area 20 through an anode trace L (i.e., a trace for providing a driving current to the anode of the light emitting element), so as to provide the driving current to the light emitting element and drive the light emitting element to emit light. The anode wires L can extend along the first direction X, and the plurality of anode wires L can be sequentially arranged along the second direction Y. The inventor of the present application has found that when there are many light emitting elements in the transparent display area 20, the number of the anode traces L is also increased, but since the number of the film layers that can serve as the anode traces L is only limited (such as the first metal layer M1, the second metal layer M2, or the anode layer), and the anode traces L need to satisfy a certain interval and line width, the problem that the first display area has insufficient wiring space and the traces are difficult to arrange occurs.

The inventors of the present application further found that the anode trace L extending along the first direction X overlaps other signal lines (e.g., power signal lines, data signal lines) extending along the second direction Y on different layers to form a coupling capacitor. In order to arrange as many anode traces L as possible, the anode traces L are usually disposed in different layers in the related art. Since the film layers where the anode traces L connected to the pixel circuits 100 in different columns are located are different, the coupling capacitances generated by the anode traces L connected to the pixel circuits 100 in different columns are different. In the low gray scale display, mura phenomenon along the second direction Y may occur due to the difference of the light emitting time of the light emitting elements driven by the pixel circuits 100 in different columns. And when the length of the anode wires L is long and the interval between the anode wires L is small, the coupling capacitance generated by the anode wires L is further increased, resulting in a more serious mura phenomenon along the second direction Y.

In view of the above research of the inventor, the embodiments of the present application provide a pixel circuit, a display panel, and a display device, which can solve at least the technical problems of insufficient wiring space in the first display area and difficult wiring layout in the related art.

The technical idea of the embodiment of the application is as follows: the first reset module and the switching module are additionally arranged to realize time-sharing multiplexing of the first wires, namely, the first wires for resetting the first pole of the light-emitting element are multiplexed through the wires (which can be called anode wires) for providing driving current for the first pole of the light-emitting element in the light-emitting stage, so that the number of the anode wires in the first display area is reduced, the wiring space of the first display area is saved, and the wires in the first display area are convenient to arrange.

The pixel circuit provided in the embodiments of the present application will be described first.

Fig. 2 is a circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure. Fig. 3 is a schematic structural diagram of a display panel to which a pixel circuit according to an embodiment of the present disclosure is applied. As shown in fig. 2 and fig. 3, the pixel circuit 100 provided in the embodiment of the present application is applied to pixel driving of the display panel 01. The display panel 01 includes, but is not limited to, an organic light emitting diode OLED display panel. The display panel 01 has a first display region 10 and a transparent display region 20 in a first direction. The first direction here may be any direction parallel to the plane of the display panel. Transparent display area 20 may include light emitting element D1. The light emitting element D1 includes, but is not limited to, a red light emitting element, a green light emitting element, or a blue light emitting element. It should be noted that, the transparent display area 20 may be provided with only the light emitting element D1 without providing the pixel circuit, that is, the pixel circuit is provided in the first display area 10, so as to ensure that the transparent display area 20 has better light transmittance. In the embodiment of the present application, the pixel circuit 100 located in the first display region 10 is electrically connected to the light emitting element D1 in the transparent display region 20 to drive the light emitting element D1 to emit light. It should be noted that the first display region 10 may include other pixel circuits in addition to the pixel circuit 100, and the other pixel circuits are used for driving the light emitting elements in the first display region 10 to emit light.

As shown in fig. 2, in the embodiment of the present application, the pixel circuit 100 includes a driving module 101, a first reset module 102, and a switching module 103. The output terminal of the driving module 101 is electrically connected to the target node Nm. Here, the output of the driving module 101 may be understood as an output of the driving current of the driving module 101.

The control terminal of the first reset module 102 is electrically connected to the first scan signal line S1, the first terminal of the first reset module 102 is electrically connected to the reference voltage signal line Vref, and the second terminal of the first reset module 102 is electrically connected to the first pole of the light emitting device D1 through the first wire L1. Here, the first electrode of the light emitting element D1 may be an anode of the light emitting element D1. In the initialization stage, the first reset module 102 may be turned on in response to the on level provided by the first scan signal line S1, and the reference voltage signal transmitted by the reference voltage signal line Vref may be transmitted to the first pole of the light emitting element D1 through the first reset module 102 and the first wire L1 to reset the first pole of the light emitting element D1.

A control end of the switching module 103 is electrically connected to the light-emitting control signal line EM, a first end of the switching module 103 is electrically connected to the target node Nm, and a second end of the switching module 103 is electrically connected to the first pole of the light-emitting element D1 through the first trace L1. In the initialization phase, the switching module 103 may be turned off in response to the off level provided by the emission control signal line EM to ensure that the first pole of the light emitting element D1 is successfully reset.

In the light emitting phase, the first reset module 102 is turned off in response to the off level provided by the first scan signal line S1, the switching module 103 is turned on in response to the on level provided by the light emitting control signal line EM, and the driving current output by the driving module 101 is transmitted to the first pole of the light emitting element D1 through the turned-on switching module 103 and the first wire L1 to drive the light emitting element D1 to emit light.

That is to say, the first trace L1 can be used to transmit the reference voltage signal during the initialization phase and transmit the driving current output by the driving module 101 during the light emitting phase, that is, the time-division multiplexing effect is achieved.

The pixel circuit of the embodiment of the application realizes time division multiplexing of the first wiring by additionally arranging the first reset module and the switching module, namely, the first wiring for resetting the first pole of the light-emitting element is multiplexed by the wiring (which can be called anode wiring) for providing the driving current for the first pole of the light-emitting element in the light-emitting stage, so that the number of the anode wirings in the first display area can be reduced, the wiring space of the first display area is saved, and the wiring arrangement of the first display area is facilitated.

In addition, with the increase of the wiring space of the first display area, the anode traces in the first display area can be arranged in the same film layer, thereby improving the mura phenomenon of the display panel in the second direction Y (such as column inversion).

Fig. 4 is another circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 4, according to some embodiments of the present application, optionally, the first reset module 102 may include a first transistor M1, a gate of the first transistor M1 is electrically connected to the first scan signal line S1, a first pole of the first transistor M1 is electrically connected to the reference voltage signal line Vref, and a second pole of the first transistor M1 is electrically connected to the first pole of the light emitting element D1 through the first routing line L1. The switching module 103 may include a second transistor M2, a gate of the second transistor M2 being electrically connected to the emission control signal line EM, a first pole of the second transistor M2 being electrically connected to the target node Nm, and a second pole of the second transistor M2 being electrically connected to the first pole of the light emitting element D1 through a first routing L1.

In the initialization stage, the first transistor M1 may be turned on in response to the turn-on level of the first scan signal line S1, the second transistor M2 may be turned off in response to the turn-off level of the emission control signal line EM, and the reference voltage signal transmitted from the reference voltage signal line Vref is transmitted to the first pole of the light emitting element D1 via the first transistor M1 and the first wire L1, thereby resetting the first pole of the light emitting element D1. In the light emitting phase, the first transistor M1 is turned off in response to the turn-off level of the first scan signal line S1, the second transistor M2 is turned on in response to the turn-on level of the light emitting control signal line EM, and the driving current output by the driving module 101 is transmitted to the first pole of the light emitting element D1 through the turned-on second transistor M2 and the first wire L1, so that the light emitting element D1 is driven to emit light.

In this way, the first wires are time-division multiplexed by the cooperation of the first transistor M1 and the second transistor M2, that is, the wires (which may be called anode wires) that provide the driving current for the first pole of the light emitting element during the light emitting stage are multiplexed with the first wires that reset the first pole of the light emitting element, so that the number of anode wires in the first display region can be reduced, the wiring space of the first display region is saved, and the wires in the first display region are conveniently arranged.

With continued reference to fig. 4, according to some embodiments of the present application, the second transistor M2 may optionally be a double-gate transistor including a first sub-transistor M21 and a second sub-transistor M22 arranged in series. The gate of the first sub-transistor M21 and the gate of the second sub-transistor M22 are both electrically connected to the light emission control signal line EM, the first pole of the first sub-transistor M21 is electrically connected to the target node Nm, the second pole of the first sub-transistor M21 is electrically connected to the first pole of the second sub-transistor M22, and the second pole of the second sub-transistor M22 is electrically connected to the first pole of the light emitting element D1 through the first routing line L1.

In this way, since the second transistor M2 is a dual-gate transistor, the leakage current from the control terminal (i.e., the first node N1) of the driving module 101 to the first electrode of the light emitting element D1 can be reduced, thereby ensuring the stability and uniformity of the brightness of the light emitting element D1.

Fig. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 5, according to some embodiments of the present application, optionally, the pixel circuit 100 may further include a first light emitting control transistor M3 and a second light emitting control transistor M4.

The gate of the first light emission controlling transistor M3 is electrically connected to the light emission control signal line EM, the first pole of the first light emission controlling transistor M3 is electrically connected to the first power voltage signal line PVDD, and the second pole of the first light emission controlling transistor M3 is electrically connected to the input terminal of the driving module 101. Illustratively, the driving module 101 may include a driving transistor M0, and the input terminal of the driving module 101 may be specifically a source or a drain of the driving transistor M0.

A gate of the second light emission controlling transistor M4 is electrically connected to the light emission control signal line EM, a first pole of the second light emission controlling transistor M4 is electrically connected to the output terminal of the driving module 101, and a second pole of the second light emission controlling transistor M4 is electrically connected to the target node Nm. When the input end of the driving module 101 is the source of the driving transistor M0, the output end of the driving module 101 is the drain of the driving transistor M0. Conversely, when the input terminal of the driving module 101 is the drain of the driving transistor M0, the output terminal of the driving module 101 is the source of the driving transistor M0.

In a light emitting phase, the first and second light emitting control transistors M3 and M4 are turned on in response to an on level provided by the light emitting control signal line EM, and a forward voltage signal provided by the first power voltage signal line PVDD is transmitted to the first pole of the light emitting element D1 through the first light emitting control transistor M3, the driving transistor M0, the second light emitting control transistor M4, the second transistor M2, and the first wiring L1 in sequence to drive the light emitting element D1 to emit light.

It is noted that the pixel circuit 100 may include other transistors, which collectively constitute a plurality of types of pixel circuits, in addition to the transistors listed above. That is, the embodiment of the present application can be applied to various types of pixel circuits such as 7T1C, 7T2C, or 9T 1C.

For ease of understanding, the following description is provided in connection with some specific application examples.

Fig. 6 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 6, according to some embodiments of the present application, optionally, the pixel circuit 100 may further include a data writing transistor M5, a threshold compensation transistor M6, a second reset transistor M7, a third reset transistor M8, and a storage capacitor Cst.

The gate of the data write transistor M5 is electrically connected to the second scan signal line S2, the first pole of the data write transistor M5 is electrically connected to the data signal line data, and the second pole of the data write transistor M5 is electrically connected to the first pole of the drive transistor M0.

The gate of the threshold compensation transistor M6 is electrically connected to the second scan signal line S2, the first pole of the threshold compensation transistor M6 is electrically connected to the gate of the driving transistor M0, and the second pole of the threshold compensation transistor M6 is electrically connected to the first pole of the driving transistor M0.

The gate of the second reset transistor M7 is electrically connected to the first scan signal line S1, the first pole of the second reset transistor M7 is electrically connected to the reference voltage signal line vref, and the second pole of the second reset transistor M7 is electrically connected to the gate of the driving transistor M0.

The gate of the third reset transistor M8 is electrically connected to the first scan signal line S1, the first pole of the third reset transistor M8 is electrically connected to the second pole of the first transistor M1, and the second pole of the third reset transistor M8 is electrically connected to the first trace L1.

A first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M0, and a second plate of the storage capacitor Cst is electrically connected to the first power voltage signal line PVDD. The second pole of the light emitting element D1 is electrically connected to the second power voltage signal line PVEE.

FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 6. As shown in fig. 7, each frame includes an initialization phase t1, a data writing phase t2, and a light emitting phase t 3.

As shown in fig. 6 and 7, in the initialization period t1, the first scan signal line S1 provides an on level, the second scan signal line S2 provides an off level, and the emission control signal line EM provides an off level. The first transistor M1 may be turned on in response to an on level of the first scan signal line S1, the third reset transistor M8 may be turned on in response to an on level of the first scan signal line S1, the second transistor M2 may be turned off in response to an off level of the emission control signal line EM, and a reference voltage signal transmitted from the reference voltage signal line Vref is transmitted to the first pole of the light emitting element D1 via the first transistor M1 and the first wiring L1, thereby resetting the first pole of the light emitting element D1. The second reset transistor M7 is turned on in response to the turn-on level transmitted by the first scan signal line S1, and the reference voltage signal of the reference voltage signal line Vref is transmitted to the first node N1 through the second reset transistor M7 to reset the first node N1.

In the data writing period t2, the first scan signal line S1 provides an off level, the second scan signal line S2 provides an on level, and the emission control signal line EM provides an off level. The data write transistor M5 and the threshold compensation transistor M6 are turned on in response to the turn-on level transmitted by the second scan signal line S2, the data voltage signal of the data voltage signal line data is transmitted to the first pole of the drive transistor M0, and the threshold compensation transistor M6 connects the gate of the drive transistor M0 and the second pole of the drive transistor M0, completing the compensation of the threshold voltage of the drive transistor M0.

In the light emission period t3, the first scan signal line S1 provides an off level, the second scan signal line S2 provides an off level, and the light emission control signal line EM provides an on level. The first and second light emission controlling transistors M3 and M4 are turned on in response to an on level transmitted by the light emission controlling signal line EM, the first transistor M1 is turned off in response to an off level of the first scan signal line S1, the second transistor M2 is turned on in response to an on level of the light emission controlling signal line EM, the driving transistor M0 is turned on in response to an on level maintained by the storage capacitor Cst, and a forward voltage signal of the first power supply voltage signal line PVDD is transmitted to the first electrode of the light emitting element D1 through the first light emission controlling transistor M3, the driving transistor M0, the second light emission controlling transistor M4, the second transistor M2, and the first wire L1 in sequence to drive the light emitting element D1 to emit light.

Fig. 8 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 8, different from the embodiment shown in fig. 6, the pixel circuit 100 may not be provided with the third reset transistor M8, and other circuit structures are the same as those of the embodiment shown in fig. 6, and are not repeated herein.

In this way, by removing the third reset transistor M8, the wiring of the pixel circuit can be simplified, the wiring space of the first display area can be further saved, and the wiring layout of the first display area is facilitated.

Fig. 9 is a schematic structural diagram of a display panel to which a pixel circuit according to an embodiment of the present disclosure is applied. As shown in fig. 9, according to some embodiments of the present application, the first display area 10 may optionally include a transition area 90 and a main screen area a 2. The light transmittance of the transition region 90 may be greater than that of the main screen region a2, i.e., the pixel density of the transition region 90 may be less than that of the main screen region a 2. The transition area 90 and the transparent display area 20 may form a sub-screen area, electronic devices such as a camera may be disposed below the sub-screen area, and the main screen area a2 is also called a normal display area. At least a partial region of the transition region 90 may not be provided with a light emitting element, and a pixel circuit 100 for driving the light emitting element in the transparent display region 20 to emit light may be provided, so that the pixel circuit 100 may be located in the transition region.

Based on the pixel circuit 100 provided in the above embodiment, accordingly, the present application also provides a specific implementation manner of the display panel. Please see the examples below.

As shown in fig. 9, a display panel 01 provided in an embodiment of the present application may include a first display region 10 and a transparent display region 20, where the transparent display region 20 includes light emitting elements. The first display region 10 may include the pixel circuit 100 provided as the above embodiment, and the pixel circuit 100 may be electrically connected to the light emitting element in the transparent display region 20.

The display panel of this application embodiment, realize the time-sharing multiplexing of first line through addding first reset module and switching module, through will providing drive current for light emitting element's the first utmost point in the luminous phase promptly and walk the line (can be called the positive pole and walk the line) multiplexing the first line that resets to light emitting element's the first utmost point, can reduce the quantity that the positive pole was walked in the first display area to save the wiring space in first display area, the line of being convenient for in first display area is arranged.

Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present application. As shown in conjunction with fig. 9 and 10, according to some embodiments of the present application, the first display area 10 may optionally include a transition area 90 and a main screen area a 2. The light transmittance of the transition region 90 may be greater than that of the main screen region a2, i.e., the pixel density of the transition region 90 may be less than that of the main screen region a 2. The transition area 90 and the transparent display area 20 may form a sub-screen area, electronic devices such as a camera may be disposed below the sub-screen area, and the main screen area a2 is also called a normal display area. At least a portion of the transition region 90 may be provided without light emitting elements, and may be used to provide pixel circuits for driving the light emitting elements in the transparent display region 20 to emit light. The transition region 90 is provided with a first pixel circuit 10a and a second pixel circuit 10b, the first pixel circuit 10a is the pixel circuit 100 provided in the above embodiment, and the first pixel circuit 10a and the plurality of second pixel circuits 10b may be arranged along the first direction X. Wherein the first direction X may be a row direction.

The second pixel circuit 10b may include a driving transistor M0 'and a third light emission controlling transistor M4', a gate of the third light emission controlling transistor M4 'is electrically connected to the light emission control signal line EM, a first pole of the third light emission controlling transistor M4' is electrically connected to a first pole of the driving transistor M0 ', and a second pole of the third light emission controlling transistor M4' is electrically connected to the light emitting element D1 in the transparent display area 20 through a second routing line L2.

That is, the transition region 90 may dispose not only the first pixel circuit 10a but also the second pixel circuit 10 b. The anode trace of the second pixel circuit 10b is not multiplexed with the first trace L1, but is electrically connected to the corresponding light emitting element D1 in the transparent display area 20 through the separate second trace L2, so as to implement independent driving of the light emitting element.

As shown in fig. 10, there may be only one first pixel circuit 10a in a row of pixel circuits (i.e., the first pixel circuit 10a and the second pixel circuit 10b arranged in the first direction X), and the rest may be the second pixel circuits 10 b. The benefits of this are: each first wire can be electrically connected with one row of pixel circuits, and one row of pixel circuits comprise a plurality of pixel circuits, so that if the anode wires of the pixel circuits are all multiplexed with the same first wire, the light-emitting elements in the transparent display area can not be driven independently; therefore, the transition area is provided with the second pixel circuits, and each second pixel circuit can be electrically connected with the light-emitting element in the transparent display area through the corresponding second routing line. Therefore, one first pixel circuit and a plurality of second pixel circuits can be arranged in one row of pixel circuits, and independent driving of the light-emitting elements in the transparent display area can be realized while the number of anode wires is reduced.

It should be noted that the second pixel circuit 10b in the embodiment of the present application may further include other transistors, and the second pixel circuit 10b includes various types of pixel circuits not limited to 7T1C, 7T2C, or 9T1C, and the specific circuit structure is please refer to the embodiment shown in fig. 6, which is not described herein again.

With continued reference to fig. 10, in some specific embodiments, the transition region 90 may include M second pixel circuits 10b, and the M second pixel circuits 10b are in one-to-one correspondence with the M second traces L2. Wherein M is an integer greater than 1. The second trace L2 may extend along the first direction X, and the plurality of second traces L2 may be sequentially arranged along the second direction Y. The second pole of the third light emitting control transistor M4' in each second pixel circuit 10b can be electrically connected to the light emitting element D1 in the transparent display area 20 through the corresponding second routing line L2.

The following describes a film layer structure and a layout structure of the display panel 01 provided in the embodiments of the present application with reference to some embodiments.

Fig. 11 is a layout of a display panel provided in an embodiment of the present application. As shown in fig. 11, according to some embodiments of the present application, the display panel 01 may optionally include an active layer P and a metal layer M that are stacked. At least in the transition region 90, the emission control signal line EM located in the metal layer M extends in the first direction X. The first portion 110 in the emission control signal line EM overlaps the active layer P in the thickness direction of the display panel.

As shown in conjunction with fig. 4 and 11, the switching module 103 includes a second transistor M9, and the first portion 110 overlapping the active layer P forms a gate of the second transistor M9.

In this way, the gate of the second transistor M9 and the emission control signal line EM can be fabricated by the same process, which is beneficial to simplifying the manufacturing process and reducing the manufacturing cost.

As shown in conjunction with fig. 4 and 11, according to some embodiments of the present application, the second transistor M2 may be optionally a double-gate transistor including a first sub-transistor M21 and a second sub-transistor M22 arranged in series. The first portion 110 includes first and second sub-portions 110a and 110b arranged at intervals, wherein the first sub-portion 110a overlapping the active layer P forms a gate of the first sub-transistor M21, and the second sub-portion 110b overlapping the active layer P forms a gate of the second sub-transistor M22.

In this way, since the second transistor M2 is a dual-gate transistor, the leakage current from the control terminal (i.e., the first node) of the driving module to the first electrode of the light emitting device can be reduced, thereby ensuring the stability and uniformity of the luminance of the light emitting device.

With continued reference to fig. 11, according to some embodiments of the present application, optionally, the first scan signal line S1 located in the metal layer M may include a first body part 111a extending in the first direction X and a first extension part 111b extending in the second direction Y, the first direction X intersecting the second direction Y. For example, the first direction X is a row direction of the display panel, and the second direction Y is a column direction of the display panel. The first body portion 111a may be electrically connected to the first pixel circuit 10a and the plurality of second pixel circuits 10b arranged along the first direction X, so as to provide a first scan signal to the first pixel circuit 10a and the plurality of second pixel circuits 10b arranged along the first direction X.

The first extension portion 111b overlaps the active layer P in the thickness direction of the display panel. As shown in conjunction with fig. 4 and 11, the first reset module 102 includes a first transistor M1, and the first extension portion 111b overlapping the active layer P may form a gate of the first transistor M1.

In this way, the gate of the first transistor M1 and the first scan signal line S1 can be prepared by the same process, which is beneficial to simplifying the manufacturing process and reducing the manufacturing cost.

Fig. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. As shown in fig. 12, according to some embodiments of the present application, the display panel 01 may optionally include a substrate 1, a buffer layer 02 on a side of the substrate 1, and a driving device layer 03 disposed on a side of the buffer layer 02 far from the substrate 1. The driving device layer 03 may include a first metal layer M1, a second metal layer M2, and a third metal layer M3, which are stacked in a direction away from the substrate 01. The source layer P is disposed between the first metal layer M1 and the buffer layer 02. Insulating layers are disposed between any adjacent metal layers and between the active layer P and the first metal layer M1. Illustratively, a gate insulating layer GI is disposed between the first metal layer M1 and the active layer P, a capacitor insulating layer IMD is disposed between the second metal layer M2 and the first metal layer M1, and an interlayer dielectric ILD is disposed between the third metal layer M3 and the second metal layer M2. In addition, the display panel 01 may further include a planarization layer PLN, a pixel defining layer PDL, and the light emitting element may include an anode RE, a light emitting layer OM, and a cathode SE, which are stacked.

As shown in connection with fig. 6, according to some embodiments of the present application, the light emission control signal line EM, the first scan signal line S1, the second scan signal line S1, and the gates of the respective transistors may be optionally located at the first metal layer M1. The reference voltage signal line Vref, the first trace L1, the second trace L2, and the second plate of the storage capacitor Cst may be located on the second metal layer M2. The first power signal line PVDD and the data signal line data may be located at the third metal layer M3. Fig. 13 is a partially enlarged view of the first pixel circuit in the layout shown in fig. 11. As shown in fig. 13, in some specific examples, the first pole of the first transistor M1 may be electrically connected to the reference voltage signal line Vref located in the second metal layer M2 through a via h1, and the second pole of the first transistor M1 may be electrically connected to the first trace L1 located in the second metal layer M2 through a via h 2. The second pole of the second transistor M2 may be electrically connected to the first trace L1 located on the second metal layer M2 through the via h 3.

Fig. 14 is another layout of the display panel provided in the embodiment of the present application. As shown in fig. 6 and 13 in conjunction, the third reset transistor M8 is not provided in the layout shown in fig. 14, as compared with the layout shown in fig. 13. Specifically, in the layout shown in fig. 13, the first pole of the third reset transistor M8 is electrically connected to the second pole of the first transistor M1, and the second pole of the third reset transistor M8 is electrically connected to the first trace L1 through the via h and the connection line x extending in the second direction Y. In the layout shown in fig. 14, the via hole h and the connection line x extending in the second direction Y may be removed to disconnect the second pole of the third reset transistor M8 from the first trace L1. The other layout structure of fig. 14 is the same as the layout shown in fig. 13, and is not described again here.

In this way, by removing the third reset transistor M8, the wiring of the pixel circuit can be simplified, the wiring space of the transition region can be further saved, and the wiring arrangement of the transition region is facilitated.

As shown in conjunction with fig. 9 and 11, according to some embodiments of the present application, the primary screen region a2 may optionally surround the transition region 90. Along the first direction X, the first pixel circuit 10a may be located on a side of the second pixel circuit 10b close to the main screen area a2 on the same row.

Therefore, the first pixel circuit is located at the junction of the transition region and the main screen region, that is, the first pixel circuit can be located at the head end of one row of pixel circuits, so that other second pixel circuits in one row of pixel circuits can be closely arranged in a repeating unit, and arrangement of transistors and wires in the transition region is facilitated.

Based on the display panel 01 provided by the above embodiment, correspondingly, the application further provides a display device, which includes the display panel provided by the application. Referring to fig. 15, fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 15 provides a display device 1000 including the display panel 01 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 15, for example, taking a mobile phone as an example, it is understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 01 provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel 01 in each of the above embodiments, which is not repeated herein.

It should be understood that the specific structures of the pixel circuit and the layout structure of the display panel provided in the drawings of the embodiments of the present application are only some examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit applied to pixel driving of a display panel having a first display region and a transparent display region in a first direction, the transparent display region including a light emitting element, a part of the pixel circuit located in the first display region being electrically connected to the light emitting element in the transparent display region, the pixel circuit comprising:

the output end of the driving module is electrically connected with the target node;

the control end of the first reset module is electrically connected with a first scanning signal line, the first end of the first reset module is electrically connected with a reference voltage signal line, and the second end of the first reset module is electrically connected with the first pole of the light-emitting element through a first wire;

a control end of the switching module is electrically connected with a light emitting control signal line, a first end of the switching module is electrically connected with the target node, and a second end of the switching module is electrically connected with a first pole of the light emitting element through the first routing line;

in a light emitting phase, the first reset module is turned off in response to an off level provided by the first scan signal line, the switching module is turned on in response to an on level provided by the light emitting control signal line, and a driving current output by the driving module is transmitted to a first pole of the light emitting element through the turned-on switching module and the first wire.

2. The pixel circuit according to claim 1, wherein the first reset module includes a first transistor, a gate of the first transistor is electrically connected to a first scan signal line, a first pole of the first transistor is electrically connected to the reference voltage signal line, and a second pole of the first transistor is electrically connected to the first pole of the light emitting element through the first trace;

the switching module comprises a second transistor, wherein a grid electrode of the second transistor is electrically connected with the light-emitting control signal line, a first pole of the second transistor is electrically connected with the target node, and a second pole of the second transistor is electrically connected with the first pole of the light-emitting element through the first wiring;

preferably, the second transistor includes a double-gate transistor, the double-gate transistor includes a first sub-transistor and a second sub-transistor that are arranged in series, a gate of the first sub-transistor and a gate of the second sub-transistor are both electrically connected to the emission control signal line, a first electrode of the first sub-transistor is electrically connected to the target node, a second electrode of the first sub-transistor is electrically connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is electrically connected to the first electrode of the light emitting element through the first routing line.

3. The pixel circuit according to claim 1, further comprising:

a first light emission control transistor, a gate of which is electrically connected to the light emission control signal line, a first pole of which is electrically connected to a first power voltage signal line, and a second pole of which is electrically connected to an input terminal of the driving module;

and a gate of the second light emission control transistor is electrically connected to the light emission control signal line, a first electrode of the second light emission control transistor is electrically connected to the output end of the driving module, and a second electrode of the second light emission control transistor is electrically connected to the target node.

4. The pixel circuit according to claim 1, wherein the first display region comprises a main screen region and a transition region, the transition region has a light transmittance greater than that of the main screen region, and the pixel circuit is located in the transition region; preferably, at least a partial region of the transition region is not provided with a light emitting element.

5. A display panel, comprising a first display region and a transparent display region, the transparent display region comprising light emitting elements;

the first display region includes the pixel circuit of any one of claims 1 to 4, which is electrically connected to a light emitting element in the transparent display region.

6. The display panel according to claim 5, wherein the first display region comprises a main screen region and a transition region, a light transmittance of the transition region is greater than that of the main screen region, at least a partial region of the transition region is not provided with a light emitting element, the transition region is provided with a first pixel circuit and a second pixel circuit, and the first pixel circuit is the pixel circuit according to any one of claims 1 to 4; the first pixel circuit and the plurality of second pixel circuits are arranged along a first direction;

the second pixel circuit includes:

a driving transistor;

a gate of the third light emitting control transistor is electrically connected to the light emitting control signal line, a first pole of the third light emitting control transistor is electrically connected to the first pole of the driving transistor, and a second pole of the third light emitting control transistor is electrically connected to the light emitting element in the transparent display area through a second routing line;

preferably, the transition region includes M second pixel circuits, the M second pixel circuits are in one-to-one correspondence with the M second routing lines, and a second electrode of the third light-emitting control transistor in each second pixel circuit is electrically connected to the light-emitting element in the transparent display region through the corresponding second routing line.

7. The display panel according to claim 6, wherein the display panel comprises an active layer and a metal layer which are stacked;

at least in the transition region, the light emission control signal lines in the metal layer extend in a first direction, and a first portion of the light emission control signal lines overlaps the active layer in a thickness direction of the display panel;

the switching module includes a second transistor, the first portion overlapping the active layer forming a gate of the second transistor;

preferably, the second transistor comprises a double-gate transistor comprising a first sub-transistor and a second sub-transistor arranged in series; the first portion includes first and second sub-portions arranged at intervals, the first sub-portion overlapping the active layer forms a gate of the first sub-transistor, and the second sub-portion overlapping the active layer forms a gate of the second sub-transistor.

8. The display panel according to claim 6, wherein the display panel comprises an active layer and a metal layer which are stacked;

the first scanning signal line in the metal layer includes a first body portion extending in a first direction and a first extending portion extending in a second direction, the first body portion is electrically connected to the first pixel circuit and the plurality of second pixel circuits arranged in the first direction, and the first direction crosses the second direction;

the first extension part overlaps the active layer in a thickness direction of the display panel;

the first reset module includes a first transistor, and the first extension portion overlapping the active layer forms a gate of the first transistor.

9. The display panel according to claim 6, wherein the main screen area surrounds the transition area, and the first pixel circuits are located on a side of the second pixel circuits close to the main screen area in the same row along the first direction.

10. A display device characterized by comprising the display panel according to any one of claims 5 to 9.