CN110993612A - Array substrate and manufacturing method thereof - Google Patents
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- CN110993612A CN110993612A CN201911178317.3A CN201911178317A CN110993612A CN 110993612 A CN110993612 A CN 110993612A CN 201911178317 A CN201911178317 A CN 201911178317A CN 110993612 A CN110993612 A CN 110993612A
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- 238000000034 method Methods 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims description 22
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- 238000000059 patterning Methods 0.000 claims description 16
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- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 154
- 230000008569 process Effects 0.000 abstract description 25
- 239000010408 film Substances 0.000 abstract description 10
- 239000011229 interlayer Substances 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 61
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
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- 239000000463 material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
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- 238000000206 photolithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The embodiment of the application discloses an array substrate and a manufacturing method thereof, source drain electrodes and grid electrodes of a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor are arranged on the same layer of the substrate, so that an interlayer dielectric layer is omitted, a film forming process can be simplified, and production cost is saved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof.
Background
The low-temperature polycrystalline silicon thin film transistor has high electron mobility and high response speed, and the oxide thin film transistor has lower leakage current. The LTPO (Low Temperature Polycrystalline Oxide) technology combining the two technologies can combine the advantages of the two technologies, and is a main development direction of the array substrate in the future. However, in the process of manufacturing the array substrate by using the LTPO technology, the number of film forming processes is large, and the production cost is high.
Disclosure of Invention
The application aims to provide an array substrate and a manufacturing method thereof, and the array substrate and the manufacturing method thereof are used for solving the technical problems that in the prior art, the film forming process of the array substrate is more in times and the production cost is high.
The application provides an array substrate, includes:
a substrate;
a buffer layer disposed on the substrate;
the first conducting channel of the low-temperature polycrystalline silicon thin film transistor and the second conducting channel of the oxide thin film transistor are arranged on the buffer layer;
an insulating layer disposed on the first conductive channel and the second conductive channel;
the first grid electrode, the first source electrode and the first drain electrode of the low-temperature polycrystalline silicon thin film transistor are arranged on the insulating layer, and the second grid electrode, the second source electrode and the second drain electrode of the oxide thin film transistor are arranged on the insulating layer;
the first gate, the first source, the first drain, the second gate, the second source and the second drain are arranged in the same layer.
In the array substrate provided by the application, the first conducting channel is made of low-temperature polycrystalline silicon, and the second conducting channel is made of oxide semiconductor.
In the array substrate provided by the application, the thickness of the first conducting channel is 100-1000 angstroms, and the thickness of the second conducting channel is 100-1000 angstroms.
In the array substrate provided by the present application, the first gate, the first source, the first drain, the second gate, the second source, and the second drain are made of a metal material.
In the array substrate provided by the application, the thicknesses of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode are all 1000 angstroms to 10000 angstroms.
In the array substrate provided by the application, the first conductive channel comprises a first heavily doped region and a second heavily doped region, and the second conductive channel comprises a third heavily doped region and a fourth heavily doped region;
a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the insulating layer, the first via hole is arranged corresponding to the first heavily doped region, the second via hole is arranged corresponding to the second heavily doped region, the third via hole is arranged corresponding to the third heavily doped region, and the fourth via hole is arranged corresponding to the fourth heavily doped region;
the first source electrode is connected with the first heavily doped region through the first via hole, the first drain electrode is connected with the second heavily doped region through the second via hole, the second source electrode is connected with the third heavily doped region through the third via hole, and the second drain electrode is connected with the fourth heavily doped region through the fourth via hole.
In the array substrate provided in the present application, the array substrate further includes:
the passivation layer and the flat layer are sequentially arranged on the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor, the flat layer is provided with a fifth through hole, and the fifth through hole extends to the passivation layer and exposes the second source electrode;
and the pixel electrode is arranged on the flat layer and is connected with the second source electrode through the fifth through hole.
The application also provides a manufacturing method of the array substrate, wherein the array substrate comprises a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, and the manufacturing method is characterized by comprising the following steps of:
forming a buffer layer on a substrate;
forming a first conductive channel of the low-temperature polycrystalline silicon thin film transistor and a second conductive channel of the oxide thin film transistor on the buffer layer, wherein the first conductive channel and the second conductive channel are positioned on the same layer;
depositing an insulating layer on the buffer layer, the first conductive channel, and the second conductive channel;
and depositing a metal layer on the insulating layer, and carrying out patterning treatment on the metal layer to form a first grid electrode, a first source electrode and a first drain electrode of the low-temperature polycrystalline silicon thin film transistor, and form a second grid electrode, a second source electrode and a second drain electrode of the oxide thin film transistor.
In the manufacturing method of the array substrate provided by the present application, the step of forming a first conductive channel of the low temperature polysilicon thin film transistor and a second conductive channel of the oxide thin film transistor on the buffer layer, where the first conductive channel and the second conductive channel are located in the same layer, includes:
depositing an amorphous silicon layer on the buffer layer, and performing rapid thermal annealing on the amorphous silicon layer to form a polycrystalline silicon layer;
patterning the polycrystalline silicon layer to form a first conductive channel of the low-temperature polycrystalline silicon thin film transistor;
and depositing an oxide semiconductor layer on the buffer layer and the first conductive channel, and performing patterning treatment on the oxide semiconductor layer to form a second conductive channel of the oxide thin film transistor.
In the manufacturing method of the array substrate provided by the present application, the manufacturing method further includes:
depositing a passivation layer and a flat layer on the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor in sequence, and patterning the passivation layer and the flat layer to form a fifth via hole, wherein the fifth via hole is arranged corresponding to the second source electrode;
and depositing an electrode layer on the flat layer, and patterning the electrode layer to form a pixel electrode, wherein the pixel electrode is connected with the second source electrode through the fifth via hole.
According to the array substrate and the manufacturing method thereof, the source drain electrodes and the grid electrodes of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are arranged on the same layer of the substrate, so that the arrangement of interlayer media is omitted, the film forming process can be simplified, and the production cost is saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of the structure obtained at the stage 101 shown in FIG. 1;
FIGS. 3A-3D are schematic diagrams of the structures obtained at the stage 102 shown in FIG. 1;
FIGS. 4A-4E are schematic diagrams of the structures obtained at the stage 103 shown in FIG. 1;
FIGS. 5A-5C are schematic diagrams of the structure obtained at the stage 104 shown in FIG. 1;
fig. 6 to 7 are schematic structural diagrams obtained by another step of the method for manufacturing an array substrate according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "thickness", "upper", "side", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In the description of the present application, it is to be noted that "patterning" refers to a step of forming a specific pattern structure, and may be a photolithography process, where the photolithography process includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and stripping the photoresist, which is a process understood by those skilled in the art and will not be described herein again.
The embodiment of the application provides an array substrate and a manufacturing method thereof, source drain electrodes and grid electrodes of a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor are arranged on the same layer of the substrate, and meanwhile, an interlayer dielectric layer is omitted, so that a film forming process can be simplified, and the production cost is saved.
Referring to fig. 5C, an embodiment of the present application provides an array substrate 1000, where the array substrate 1000 includes: a substrate 10; a buffer layer 20 disposed on the substrate 10; a first conductive channel 300 of the low temperature polysilicon thin film transistor T1, and a second conductive channel 400 of the oxide thin film transistor T2, disposed on the buffer layer 20; an insulating layer 50 disposed on the first conductive channel 300 and the second conductive channel 400; a first gate electrode 601, a first source electrode 602, and a first drain electrode 603 of a low temperature polysilicon thin film transistor T1, and a second gate electrode 604, a second source electrode 605, and a second drain electrode 606 of an oxide thin film transistor T2, which are disposed on the insulating layer 50; the first gate 601, the first source 602, the first drain 603, the second gate 604, the second source 605, and the second drain 606 are disposed at the same layer.
The first conductive channel 300 is made of low temperature polysilicon. The second conductive channel 400 is made of an oxide semiconductor, for example, metal oxides such as indium gallium zinc oxide, indium tin zinc oxide, and indium gallium tin zinc oxide. The first conductive channel 300 has a thickness of 100 a-1000 a. The second conductive channel 400 has a thickness of 100 a to 1000 a. The materials used for the first gate 601, the first source 602, the first drain 603, the second gate 604, the second source 605, and the second drain 606 are metal materials with excellent conductivity and light shielding property, such as molybdenum, copper, aluminum, or a composite metal. The first gate 601, the first source 602 and the first drain 603, the second gate 604, the second source 605 and the second drain 606 are all 1000 a-10000 a thick.
Further, the first conductive channel 300 includes a first heavily doped region 301 and a second heavily doped region 302. The second conductive channel 400 includes a third heavily doped region 401 and a fourth heavily doped region 402. The first conductive channel 300 and the second conductive channel 400 are located at the same layer. A first via 501, a second via 502, a third via 503 and a fourth via 504 are disposed on the insulating layer 50. The first via 501 is disposed corresponding to the first heavily doped region 301. The second via 502 is disposed corresponding to the second heavily doped region 302. The third via 503 is disposed corresponding to the third heavily doped region 401. The fourth via 504 is disposed corresponding to the fourth heavily doped region 402. The first source 602 is connected to the first heavily doped region 301 through the first via 501. The first drain 603 is connected to the second heavily doped region 302 through the second via 502. The second source 605 is connected to the third heavily doped region 401 through a third via 603. The second drain 606 is connected to the fourth heavily doped region 402 by a fourth via 504.
In some embodiments, referring to fig. 7, the array substrate 1000 further includes: a passivation layer 70 and a planarization layer 80 on the low temperature polysilicon thin film transistor T1 and the oxide thin film transistor T2 are sequentially disposed; the planarization layer 80 is provided with a fifth via hole 801, and the fifth via hole 801 extends to the passivation layer 70 and exposes the second source electrode 605; and a pixel electrode 90 disposed on the planarization layer 80, wherein the pixel electrode 90 is connected to the second source electrode 605 through a fifth via 801.
In the array substrate 1000 provided in the embodiment of the present application, since the first gate 601, the first source 602, and the first drain 603 of the low temperature polysilicon thin film transistor T1, and the second gate 604, the second source 605, and the second drain 605 of the oxide thin film transistor T2 are located on the same layer of the substrate 10, an interlayer dielectric layer having an isolation function may be omitted, so that a film structure of the array substrate 1000 is simplified.
The embodiment of the present application further provides a method for manufacturing the array substrate shown in fig. 5C and fig. 7, please refer to fig. 1, and fig. 1 is a schematic flow chart of the manufacturing method of the array substrate provided in the embodiment of the present application, which includes the specific steps of:
Referring to fig. 2, a substrate 10 is provided, and the substrate 10 is cleaned and pre-baked to remove foreign particles such as oil and grease on the surface of the substrate 10. A buffer layer 20 is then deposited on the substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI flexible substrate (Polyimide Film), or other types of substrates, which are not described herein in detail. The material of the buffer layer 20 may be silicon dioxide, silicon nitride, silicon oxynitride, or amorphous silicon. The buffer layer 20 may be formed by an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process, or other processes.
It should be noted that, in some embodiments, a buffer layer 20 may be formed by sequentially depositing a silicon nitride layer, a silicon oxide layer, and an amorphous silicon layer on the substrate 10; alternatively, a buffer layer 20 may be formed by sequentially depositing a silicon nitride layer and an amorphous silicon layer on the substrate 10; a buffer layer 20 may be formed by sequentially depositing a silicon oxide layer and an amorphous silicon layer on the substrate 10; the buffer layer 20 may also be formed by depositing a silicon oxide layer, a silicon dioxide layer or an amorphous silicon layer on the substrate 10, which is not particularly limited in the embodiments of the present application.
Specifically, step 102 includes: depositing an amorphous silicon layer on the buffer layer, and performing rapid thermal annealing on the amorphous silicon layer to form a polycrystalline silicon layer; patterning the polycrystalline silicon layer to form a first conductive channel of the low-temperature polycrystalline silicon thin film transistor; and depositing an oxide semiconductor layer on the buffer layer and the first conductive channel, and performing patterning treatment on the oxide semiconductor layer to form a second conductive channel of the oxide thin film transistor.
Referring to fig. 3A-3D, first, an amorphous silicon layer is deposited on the buffer layer 20, and the amorphous silicon layer is subjected to rapid thermal annealing or laser annealing to form a polysilicon layer 30. The polysilicon layer 30 is patterned to form the first conductive channel 300 of the low temperature polysilicon thin film transistor T1. Then, the oxide semiconductor layer 40 is deposited on the buffer layer 20 and the first conductive channel 300. To the oxide semiconductor layer 40The patterning process is performed to form the second conductive channel 400 of the oxide thin film transistor T2. Wherein the thickness of the polysilicon layer 30 is 100 angstroms-
The thickness of the oxide semiconductor layer 40 is 100 to 1000 angstroms. The material of the oxide semiconductor layer 40 may be metal oxide such as indium gallium zinc oxide, indium tin zinc oxide, and indium gallium tin zinc oxide, which is not specifically limited in this embodiment.
Referring to fig. 4A, an insulating layer 50 is deposited on the buffer layer 20, the first conductive channel 300, and the second conductive channel 400. The insulating layer 50 may be a silicon oxide layer or a silicon nitride layer, or may be a multi-film layer combination structure of silicon oxide and silicon nitride, which is not specifically limited in this embodiment of the application.
Further, the first conductive channel and the second conductive channel are doped to form a first heavily doped region and a second heavily doped region on the first conductive channel, and to form a third heavily doped region and a fourth heavily doped region on the second conductive channel.
Specifically, the method comprises the following steps: depositing a first photoresist layer on the insulating layer; exposing and developing the first photoresist layer to form a first photoresist pattern, wherein the first photoresist pattern comprises a first sub-photoresist block and a second sub-photoresist block, the projection of the first sub-photoresist block on the substrate is positioned in the middle of the projection of the first conductive channel on the substrate, and the projection of the second sub-photoresist block on the basic is positioned in the middle of the projection of the second conductive channel on the substrate; performing an ion implantation process on the first conductive channel and the second conductive channel by using the first photoresist pattern as a mask to form a first heavily doped region and a second heavily doped region on the first conductive channel, and to form a third heavily doped region and a fourth heavily doped region on the second conductive channel; and removing the first photoresist pattern.
With continued reference to fig. 4B-4D, a first photoresist layer 51 is first deposited over the insulating layer 50. The first photoresist layer 51 is exposed to light and developed to form a first photoresist pattern 510. The first photoresist pattern 510 includes a first sub photoresist block 511 and a second sub photoresist block 512. The projection of the first sub-photoresist block 511 on the substrate 10 is located in the middle of the projection of the first conductive channel 300 on the substrate 10. The projection of the second sub-photoresist block 512 on the substrate 10 is located in the middle of the projection of the second conductive channel 400 on the substrate 10. The first conductive channel 300 and the second conductive channel 400 are subjected to an ion implantation process using the first photoresist pattern 510 as a mask, to form a first heavily doped region 301 and a second heavily doped region 302 on the first conductive channel 300, and to form a third heavily doped region 401 and a fourth heavily doped region 402 on the second conductive channel 400. Finally, the first photoresist pattern 510 is removed.
The first heavily doped region 301, the second heavily doped region 302, the third heavily doped region 401, and the fourth heavily doped region 402 may be N-type heavily doped or P-type heavily doped.
In the process of manufacturing the array substrate according to the embodiment of the present invention, the insulating layer 50 is first deposited on the buffer layer 20, the first conductive channel 300 and the second conductive channel 400, and then the ion implantation process is performed on the first conductive channel 300 and the second conductive channel 400. Based on this process, since the insulating layer 50 is formed first, the insulating layer 50 has a planarization effect, so that the photoresist 51 formed on the insulating layer 50 is more uniformly distributed. Further, when the photoresist 510 is used as a mask to perform an ion implantation process, the formed first heavily doped region 301, second heavily doped region 302, third heavily doped region 401 and fourth heavily doped region 402 are doped more uniformly, so that the performance of the array substrate is improved. Meanwhile, the insulating layer 50 also functions as a protective layer for the first and second conductive channels 300 and 400 during the exposure and development of the photoresist 51.
Further, please continue to refer to fig. 4E, a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the insulating layer, the first via hole is disposed corresponding to the first heavily doped region, the second via hole is disposed corresponding to the second heavily doped region, the third via hole is disposed corresponding to the third heavily doped region, and the fourth via hole is disposed corresponding to the fourth heavily doped region.
Specifically, the insulating layer 50 is etched to form a first via 501, a second via 502, a third via 503, and a fourth via 504. The first via 501 is disposed corresponding to the first heavily doped region 301 and exposes a side of the first heavily doped region 301 away from the substrate 10. The second via 502 is disposed corresponding to the second heavily doped region 302 and exposes a side of the second heavily doped region 302 away from the substrate 10. The third via 503 is disposed corresponding to the third heavily doped region 401 and exposes a side of the third heavily doped region 401 away from the substrate 10. The fourth via 504 is disposed corresponding to the fourth heavily doped region 402 and exposes a side of the fourth heavily doped region 402 away from the substrate 10.
And 104, depositing a metal layer on the insulating layer, and performing patterning treatment on the metal layer to form a first grid electrode, a first source electrode and a first drain electrode of the low-temperature polycrystalline silicon thin film transistor, and to form a second grid electrode, a second source electrode and a second drain electrode of the oxide thin film transistor.
The first source electrode is connected with the first heavily doped region through the first via hole, the first drain electrode is connected with the second heavily doped region through the second via hole, the second source electrode is connected with the third heavily doped region through the third via hole, and the second drain electrode is connected with the fourth doped region through the fourth via hole.
Specifically, step 104 includes: depositing a metal layer and a second photoresist layer on the insulating layer; exposing and developing the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern comprises a third sub photoresist block, a fourth sub photoresist block, a fifth sub photoresist block, a sixth sub photoresist block, a seventh sub photoresist block and an eighth sub photoresist block; etching the metal layer by taking the second photoresist pattern as a mask to form a first grid, a second grid, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the third sub photoresist block is arranged corresponding to the first source electrode, the fourth sub photoresist block is arranged corresponding to the first grid, the fifth sub photoresist block is arranged corresponding to the first drain electrode, the sixth sub photoresist block is arranged corresponding to the second source electrode, the seventh sub photoresist block is arranged corresponding to the second grid electrode, and the eighth sub photoresist block is arranged corresponding to the second drain electrode; and removing the second photoresist pattern.
Referring to fig. 5A-5C, first, a metal layer 60 and a second photoresist layer 61 are deposited on the insulating layer 50. The second photoresist layer 61 is exposed and developed to form a second photoresist pattern 610, and the second photoresist pattern 610 includes a third sub photoresist block 611, a fourth sub photoresist block 612, a fifth sub photoresist block 613, a sixth sub photoresist block 614, a seventh sub photoresist block 615, and an eighth sub photoresist block 616. Then, the metal layer 60 is etched using the second photoresist pattern 610 as a mask, thereby forming a first gate 601, a first source 602, and a first drain 603 of the low temperature polysilicon tft T1, and forming a second gate 604, a second source 605, and a second drain 606 of the oxide tft T2. The third sub-photoresist block 611 is disposed corresponding to the first source 602, the fourth sub-photoresist block 612 is disposed corresponding to the first gate 601, the fifth sub-photoresist block 613 is disposed corresponding to the first drain 603, the sixth sub-photoresist block 614 is disposed corresponding to the second source 605, the seventh sub-photoresist block 615 is disposed corresponding to the second gate 604, and the eighth sub-photoresist block 616 is disposed corresponding to the second drain 606. Finally, the second photoresist pattern 610 is removed.
Wherein the thickness of the metal layer 60 is 1000 a to 10000 a. The material of the metal layer 60 is a metal having excellent conductivity and light shielding property, and is generally molybdenum, copper, aluminum or a composite metal, which is not limited in the embodiment of the present application.
It should be noted that the first source 602 and the first drain 603 of the low temperature polysilicon tft T1 are symmetrically disposed, so the first source 602 and the first drain 603 can be interchanged. The second source electrode 605 and the second drain electrode 606 of the oxide thin film transistor T2 are symmetrically disposed, so the second source electrode 605 and the second drain electrode 606 can be interchanged.
In the prior art, because the source drain and the gate are located at different layers, for the purpose of protection, an interlayer dielectric layer needs to be formed between the source drain and the gate to effectively isolate the source drain and the gate. However, in the embodiment of the present invention, since the first gate 601, the first source 602, and the first drain 603 of the low temperature polysilicon tft T1 and the second gate 604, the second source 605, and the second drain 606 of the oxide tft T2 are formed in the same layer by a photolithography process, the interlayer dielectric layer is omitted, and the film forming process is simplified.
In some embodiments, the method for manufacturing the array substrate further includes forming a passivation layer, a planarization layer, and a pixel electrode.
Referring to fig. 6 to 7, a passivation layer 70 and a planarization layer 80 are sequentially deposited on the low temperature polysilicon thin film transistor T1 and the oxide thin film transistor T2. The passivation layer 70 and the planarization layer 80 are etched to form a fifth via hole 801, and the fifth via hole 801 is disposed corresponding to the second source electrode 605. Specifically, the fifth via 801 penetrates through the planarization layer 80 and extends to the passivation layer 70, while exposing a side of the second source electrode 605 away from the substrate 10. Thereafter, an electrode layer is deposited on the planarization layer 80 and is subjected to patterning processing to form a pixel electrode 90. The pixel electrode 90 is connected to the second source 602 through the fifth via 801. Also, the passivation layer 70 and the planarization layer 80 may be formed using an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process, or other processes.
The passivation layer 70 completely covers the first gate 601, the first source 602, the first drain 603, the second gate 604, the second source 605 and the second drain 606, so that the first gate 601, the first source 602, the first drain 603, the second gate 604, the second source 605 and the second drain 606 are isolated from each other, thereby functioning as an isolation layer and having a protection function.
In the manufacturing method of the array substrate provided by the embodiment of the application, the first gate 601, the first source 602, and the first drain 603 of the low temperature polysilicon thin film transistor T1, and the second gate 604, the second source 605, and the second drain 606 of the oxide thin film transistor T2 are disposed on the same layer of the substrate 10, so that the film structure is simplified, and the film forming process is reduced. Further, the passivation layer 70 is disposed to completely cover and isolate the first gate electrode 601, the first source electrode 602, and the first drain electrode 603, and the second gate electrode 604, the second source electrode 605, and the second drain electrode 605 of the oxide thin film transistor T2, which can function as a protective isolation similar to an interlayer dielectric layer.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
a buffer layer disposed on the substrate;
the first conducting channel of the low-temperature polycrystalline silicon thin film transistor and the second conducting channel of the oxide thin film transistor are arranged on the buffer layer;
an insulating layer disposed on the first conductive channel and the second conductive channel;
the first grid electrode, the first source electrode and the first drain electrode of the low-temperature polycrystalline silicon thin film transistor are arranged on the insulating layer, and the second grid electrode, the second source electrode and the second drain electrode of the oxide thin film transistor are arranged on the insulating layer;
the first gate, the first source, the first drain, the second gate, the second source and the second drain are arranged in the same layer.
2. The array substrate of claim 1, wherein the first conductive channel is made of low temperature polysilicon, and the second conductive channel is made of oxide semiconductor.
3. The array substrate of claim 2, wherein the first conductive channel has a thickness of 100-1000 angstroms and the second conductive channel has a thickness of 100-1000 angstroms.
4. The array substrate of claim 1, wherein the first gate, the first source, the first drain, the second gate, the second source, and the second drain are made of a metal material.
5. The array substrate of claim 4, wherein the first gate, the first source, the first drain, the second gate, the second source, and the second drain are all 1000 angstroms to 10000 angstroms thick.
6. The array substrate of claim 1, wherein the first conductive channel comprises a first heavily doped region and a second heavily doped region, and the second conductive channel comprises a third heavily doped region and a fourth heavily doped region;
a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the insulating layer, the first via hole is arranged corresponding to the first heavily doped region, the second via hole is arranged corresponding to the second heavily doped region, the third via hole is arranged corresponding to the third heavily doped region, and the fourth via hole is arranged corresponding to the fourth heavily doped region;
the first source electrode is connected with the first heavily doped region through the first via hole, the first drain electrode is connected with the second heavily doped region through the second via hole, the second source electrode is connected with the third heavily doped region through the third via hole, and the second drain electrode is connected with the fourth heavily doped region through the fourth via hole.
7. The array substrate of claim 1, further comprising:
the passivation layer and the flat layer are sequentially arranged on the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor, the flat layer is provided with a fifth through hole, and the fifth through hole extends to the passivation layer and exposes the second source electrode;
and the pixel electrode is arranged on the flat layer and is connected with the second source electrode through the fifth through hole.
8. A manufacturing method of an array substrate, wherein the array substrate comprises a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, and the manufacturing method comprises the following steps:
forming a buffer layer on a substrate;
forming a first conductive channel of the low-temperature polycrystalline silicon thin film transistor and a second conductive channel of the oxide thin film transistor on the buffer layer, wherein the first conductive channel and the second conductive channel are positioned on the same layer;
depositing an insulating layer on the buffer layer, the first conductive channel, and the second conductive channel;
and depositing a metal layer on the insulating layer, and carrying out patterning treatment on the metal layer to form a first grid electrode, a first source electrode and a first drain electrode of the low-temperature polycrystalline silicon thin film transistor, and form a second grid electrode, a second source electrode and a second drain electrode of the oxide thin film transistor.
9. The method for manufacturing the array substrate according to claim 8, wherein the step of forming the first conducting channel of the LTPS TFT and the second conducting channel of the oxide TFT on the buffer layer, the first conducting channel and the second conducting channel being in the same layer comprises:
depositing an amorphous silicon layer on the buffer layer, and performing rapid thermal annealing on the amorphous silicon layer to form a polycrystalline silicon layer;
patterning the polycrystalline silicon layer to form a first conductive channel of the low-temperature polycrystalline silicon thin film transistor;
and depositing an oxide semiconductor layer on the buffer layer and the first conductive channel, and performing patterning treatment on the oxide semiconductor layer to form a second conductive channel of the oxide thin film transistor.
10. The method for manufacturing the array substrate according to claim 8, further comprising:
depositing a passivation layer and a flat layer on the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor in sequence, and patterning the passivation layer and the flat layer to form a fifth via hole, wherein the fifth via hole is arranged corresponding to the second source electrode;
and depositing an electrode layer on the flat layer, and patterning the electrode layer to form a pixel electrode, wherein the pixel electrode is connected with the second source electrode through the fifth via hole.
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| WO2023221209A1 (en) * | 2022-05-17 | 2023-11-23 | 广州华星光电半导体显示技术有限公司 | Display panel and fabricating method therefor |
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Application publication date: 20200410 |