TWI643253B - Method of fabricating power mosfet - Google Patents

Abstract

A method for fabricating a power MOS field effect transistor includes forming a semiconductor layer on a substrate, forming at least one first trench in the semiconductor layer, and sequentially forming a thermal oxide layer, a tantalum nitride layer, and a layer on the surface of the trench a CVD oxide layer, forming a first gate in the first trench, forming a second CVD oxide layer on the first gate in the first trench, and forming a mask on the second CVD oxide layer in the first trench The second layer is formed between the mask layer and the thermal oxide layer, and the second gate is formed in the second trench.

Description

Method for manufacturing power MOS semiconductor field effect transistor

The present invention relates to a method of fabricating a MOS field effect transistor, and more particularly to a method of fabricating a power MOS field effect transistor.

A split-gate power MOSFET can also be called a shielded gate-power MOSFET, which is constructed as a trench-type gold MOSFET. The gate structure in the oxygen half field effect transistor is separated by an inter-poly-dielectric (IPD) and is divided into two potentials. The upper gate is called the channel for the gold-oxygen half-effect transistor, and the lower gate is electrically coupled to the source potential with the metal interconnect for blocking. The two-dimensional charge balance is generated under operation, and the excessive gate-to-drain capacitance in the conventional trench-type MOS field-effect transistor is improved by the polysilicon inter-turn dielectric layer, thereby reducing switching loss.

However, the thermal oxidation method used in the fabrication of the gate-power MOS field effect transistor causes diffusion of dopant ions, so that the above two separated gates cannot be effectively isolated. Further, when the gate-type power MOS field effect transistor is applied for high voltage, it cannot withstand higher potential.

The invention provides a method for manufacturing a power MOS field effect transistor, which can produce a power MOS field effect transistor capable of maintaining performance under a high voltage field, and can improve the reliability of manufacturing.

The method for fabricating a power MOS field effect transistor of the present invention comprises forming a semiconductor layer on a substrate, and forming at least one first trench in the semiconductor layer. Then, forming a first thermal oxide layer, a tantalum nitride layer and a first CVD oxide layer on the surface of the first trench, forming a first gate in the first trench, and first in the first trench A second CVD oxide layer is formed on the gate. Next, a mask layer is formed on the second CVD oxide layer in the first trench, wherein a second trench is formed between the mask layer and the first thermal oxide layer. Thereafter, a second gate is formed in the second trench.

In an embodiment of the invention, a second thermal oxide layer may be formed on the first gate before the second CVD oxide layer is formed on the first gate in the first trench.

In an embodiment of the invention, the step of forming the second thermal oxide layer may first perform an implantation process on the first gate, and then remove a portion of the first CVD oxide layer to expose the first gate. The first CVD oxide layer is thinned and then thermally oxidized to form the second thermal oxide layer and fillet the first gate.

In an embodiment of the invention, before forming the second CVD oxide layer on the first gate and after forming the second thermal oxide layer, the method further includes forming a third on the second thermal oxide layer. Thermal oxide layer.

In an embodiment of the invention, the first gate in the first trench is shaped The method of forming the second CVD oxide layer may be performed by forming a second CVD oxide layer on the semiconductor layer and the first trench by using a CVD process, and forming the mask layer in the first trench to expose a portion of the second layer. The CVD oxide layer, with the mask layer as an etch mask, removes the exposed second CVD oxide layer to expose a portion of the tantalum nitride layer, and then removes the exposed tantalum nitride layer to form a second trench.

In an embodiment of the invention, the second gate may also cover the mask layer.

In an embodiment of the invention, the mask layer is, for example, a conductive material or a non-conductive material.

In an embodiment of the invention, the method of forming the first CVD oxide layer and the second CVD oxide layer comprises a high temperature CVD process or a CVD process using tetraethoxy decane (TEOS) as a raw material.

In another embodiment of the present invention, after the first gate is formed in the first trench, a portion of the first CVD oxide layer on the sidewall of the first trench may also be removed to thin the first CVD oxide. Floor.

Based on the above, the power MOS field effect transistor of the present invention can effectively prevent leakage under high operating voltage by separating the first gate and the second gate by the CVD oxide layer formed in the trench. occur. Moreover, by forming the second CVD oxide layer, the oxide layer between the first gate and the second gate can be thickened so that the power MOS field effect transistor of the present invention can withstand the cross The pressure increases. In addition, since the mask layer formed in the manufacturing process of the present invention can also be used as a part of the second gate, the variability of the process can be increased.

The above described features and advantages of the invention will be apparent from the following description.

100, 300‧‧‧ substrate

102, 302‧‧‧ semiconductor layer

102a, 302a‧‧‧ first ditches

104, 304‧‧‧ Well Area

106, 306‧‧‧First thermal oxide layer

108, 312‧‧‧ first gate

108a, 312a‧‧‧ rounded corners

110, 314‧‧‧ implant process

112, 316‧‧‧ corners

114, 318‧‧‧Second thermal oxide layer

118, 118a, 310, 322, 322a‧‧‧ CVD oxide layer

120, 120a, 200, 324, 324a, 400‧‧ ‧ cover layer

122, 202, 326, 402‧‧‧Second ditches

124, 204, 328, 404‧‧‧ second gate

126, 330‧‧‧ source area

116, 116a, 308‧‧‧ layer of tantalum nitride

320‧‧‧ Third thermal oxide layer

1A through 1H are schematic cross-sectional views showing a manufacturing process of a power MOS field effect transistor in accordance with a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views showing a manufacturing process of a modification of the first embodiment.

3A through 3H are schematic cross-sectional views showing a manufacturing process of a power MOS field effect transistor in accordance with a second embodiment of the present invention.

4A to 4D are schematic cross-sectional views showing a manufacturing process of a modification of the second embodiment.

The drawings in the following embodiments are intended to provide a more complete description of the exemplary embodiments of the present invention, but the invention may be practiced in many different forms and should not be construed as being limited Example. In the drawings, the relative thickness and position of layers, regions, and/or structural elements may be reduced or exaggerated for clarity. In addition, "first", "second", etc. are used herein to describe different regions, layers, and/or blocks, but such terms are only used to distinguish one region, layer or block from another region, film. Layer or block. Therefore, the first area, film layer or A block may be referred to as a second region, layer or block without departing from the teachings of the embodiments.

1A through 1H are schematic cross-sectional views showing a manufacturing process of a power MOS field effect transistor in accordance with a first embodiment of the present invention.

Referring first to FIG. 1A, a semiconductor layer 102 is formed on the substrate 100. In the present embodiment, the substrate 100 is not particularly limited. The semiconductor layer 102 is, for example, a doped germanium layer or a doped epitaxial layer. Thereafter, a first trench 102a is formed in the semiconductor layer 102, and the formation method thereof is, for example, a photolithography etching process. For example, a patterned mask layer (not shown) is first formed on the semiconductor layer 102 to expose a portion of the semiconductor layer 102. Thereafter, the exposed portion of the semiconductor layer 102 is etched by using the patterned mask layer as a mask, and then the patterned mask layer is removed. In addition, the well region 104 may be formed in the semiconductor layer 102 before the first trench 102a is formed in the semiconductor layer 102, but the invention is not limited thereto; that is, the well region 104 may also be formed in a subsequent process.

Then, referring to FIG. 1B, a first thermal oxide layer 106 is formed on the surface of the first trench 102a. The method of forming the first thermal oxide layer 106 is, for example, a thermal oxidation process. In the present embodiment, the first thermal oxide layer 106 fabricated by the thermal oxidation process is, for example, subjected to a higher process temperature (900 ° C to 1200 ° C) during fabrication, and thus the material of the first thermal oxide layer 106 formed. (for example, cerium oxide) has a high density, which can be used as a surface protection for subsequent processes.

Next, referring to FIG. 1C, a first gate 108 is formed in the first trench 102a. In this embodiment, the first gate 108 is formed as follows: First, by chemical vapor deposition (Chemical Vapor Deposition), physical vapor deposition (Physical) Vapor deposition or other suitable film forming process for forming a conductor layer on the semiconductor layer 102 and in the first trench 102a, and then performing a chemical mechanical polishing (CMP) process on the conductor layer and non-equal The etch process is performed to form a first gate 108 in the first trench 102a. In addition, since the first gate 108 can be rounded up, the first gate 108 can be selectively implanted 110 to improve the oxidation of the first gate 108 in the subsequent thermal oxidation process. effectiveness.

Then, referring to FIG. 1D, a portion of the first thermal oxide layer 106 is removed to thin the first thermal oxide layer 106. In the present embodiment, the method of removing a portion of the first thermal oxide layer 106 is, for example, performing a wet etching process to remove a portion of the first thermal oxide layer 106 of the sidewall of the first trench 102a. The process of continuously removing the first thermal oxide layer 106 may expose the corners 112 of the first gate 108 to facilitate subsequent thermal oxidation to fillet the first gate 108.

Next, referring to FIG. 1E, a thermal oxidation process is performed to form a second thermal oxide layer 114 and fillet the first gate 108. In the present embodiment, by thermally oxidizing the first gate 108, the surface of the first gate 108 having a higher doping concentration can be oxidized faster to form the rounded corner 108a, but the present invention is not limited thereto. If the corners of the first gate 108 are round rather than having protruding tip structures, the input capacitance (eg, gate-source capacitance ( _Cgs )) can be reduced, or the reverse can be reduced. Leakage current (eg, gate leakage current (I _gss )) can improve the reliability of power _MOS field effect transistors.

Then, referring to FIG. 1F, a layer of tantalum nitride 116 is formed on the substrate 100. The first thermal oxide layer 106 in the first trench 102a is covered, and the first CVD oxide layer 118 is formed on the first gate 108 in the first trench 102a. In this embodiment, a method of forming the first CVD oxide layer 118, such as a high temperature CVD process, or a CVD process using tetraethyl orthosilicate (TEOS) as a raw material, and such as a low pressure chemical vapor deposition process . In this embodiment, the oxide layer on the first gate 108 can be thickened by forming the first CVD oxide layer 118 on the first gate 108 in the first trench 102a, thereby improving the power MOS. The voltage across the field effect transistor can withstand. In addition, in this embodiment, before the formation of the first CVD oxide layer 118 and after the formation of the tantalum nitride layer 116, a thermal oxidation process may be further performed to the first gate 108 and the first CVD oxide. A thermal oxide layer (not shown) is formed between the layers 118 to further thicken the oxide layer on the first gate 108 to the thickness of the component design. Thereafter, a mask layer 120 is formed in the first trench 102a, wherein the mask layer 120 is, for example, a conductive material or a non-conductive material. In this embodiment, the mask layer 120 may be a conductive material such as metal, polysilicon or amorphous germanium, and the forming method thereof is, for example, chemical vapor deposition, physical vapor deposition or other suitable film forming processes. In an embodiment, the mask layer 120 may fill the first trench 102a, but the invention is not limited thereto.

Next, referring to FIG. 1G, the mask layer 120 of FIG. 1F may be etched back (ie, an anisotropic etching process), and the sidewall of the first trench 102a is removed by using the mask layer 120a as an etching mask. a CVD oxide layer (118 of FIG. 1F) to expose the tantalum nitride layer 116 of FIG. 1F, wherein the tantalum nitride layer 116 can protect the first thermal oxide layer 106 from etching the first CVD oxide layer influences. Then, the first ditch The exposed tantalum nitride layer 116 on the sidewall of 102a is removed to form a second trench 122. At this time, the structure between the first gate 108 and the mask layer 120a has a second thermal oxide layer 114, a tantalum nitride layer 116a and a first CVD oxide layer 118a.

Thereafter, referring to FIG. 1H, a second gate 124 is formed in the second trench 122. The second gate 124 is formed on the semiconductor layer 102 by chemical vapor deposition, physical vapor deposition or other suitable film forming process, and a conductor layer filling the second trench 122 in the first trench 102a, for example, and The conductor layer is formed by a chemical mechanical polishing process. Thereafter, the source region 126 can be formed in the well region 104 by means of an implant process or the like. In the present embodiment, since the mask layer 120a is a conductive material, the mask layer 120a itself can also serve as the second gate of the power MOS field effect transistor. Moreover, since the mask layer 120a and the second gate 124 are not formed at the same time, the material of the mask layer 120a may be different from the material of the second gate 124. Moreover, during the fabrication of the power MOS field effect transistor, the mask layer 120a serves as a protective layer for protecting the first CVD oxide layer 118a during the etching process, so the mask layer 120a preferably has a lower etching than the oxide. An etching rate material is used to protect the first CVD oxide layer 118a formed between the first gate 108 and the second gate 124. At the same time, the second gate 124 is located on the sidewall of the mask layer 120a and is in direct contact with it, so that the second gate 124 can repair the defects caused by the side surface of the mask layer 120a during the etching process as an etching process and fill in The gap filling of the second trench 122 in Fig. 1G is completed. In addition, since the oxide quality of the first CVD oxide layer 118a is superior to that of the oxide layer formed by the thermal oxidation method, the first CVD oxide formed between the first gate 108 and the second gate 124 is formed. Layer 118a can effectively isolate the first A gate 108 and a second gate 124 enable the power MOS field effect transistor of the present embodiment to withstand higher potential without leakage.

Referring to FIG. 1H, the first thermal oxide layer 106 between the second gate 124 and the well region 104 can serve as a gate oxide layer. The drain region (not shown) is usually disposed on the side of the substrate 100 where the semiconductor layer 102 is not formed. In addition, a film layer such as an insulating layer (not shown) may be disposed on the second gate 124 according to the design.

2A to 2C are schematic cross-sectional views showing a manufacturing process of a modification of the first embodiment, in which the same or similar components are denoted by the same reference numerals as in the first embodiment, and the related description thereof will not be repeated.

Referring to FIG. 2A, after performing the process as described in FIG. 1A to FIG. 1F, the mask layer can be etched back (ie, an anisotropic etching process) to obtain a mask layer 200 as shown in FIG. 2A, and the mask is covered. The curtain layer 200 may be made of a non-conductive material having a lower etching rate than the oxide, such as a non-conductive material such as tantalum nitride, in addition to a conductive material such as a metal, a polysilicon or an amorphous germanium which is generally used as a gate.

Next, referring to FIG. 2B, the exposed first CVD oxide layer (as shown in FIG. 2A) is removed to expose the tantalum nitride layer 116 of FIG. 2A, and the tantalum nitride layer 116 is used as the protection in the etching process. A protective layer of a thermal oxide layer 106. The exposed tantalum nitride layer 116 is then removed to form a second trench 202. At this time, the mask layer 200 serves as a protective layer for protecting the first CVD oxide layer 118a in the etching process.

Thereafter, referring to FIG. 2C, the second gate 204 is filled in the first trench 102a. The second gate 204 is formed, for example, by chemical vapor deposition, physical vapor deposition, or other suitable film formation process on the semiconductor layer 102 and in the first trench 102a. The bulk layer is formed by performing a chemical mechanical polishing process or an anisotropic etching process on the conductor layer. In the present embodiment, the second gate 204 fills the first trench 102a and covers the mask layer 200. Source region 126 can then be formed in well region 104. In the present embodiment, since the mask layer 200 and the second gate 204 are not formed at the same time, the material of the mask layer 200 may be different from the material of the second gate 204. Furthermore, since the mask layer 200 is covered with the second gate 204, the mask layer 200 may be selected to have a lower specific oxide than a conductive material such as a metal, a polysilicon or an amorphous germanium. The etch rate of the non-conductive material, such as tantalum nitride. At the same time, the second gate 204 covers the entire mask layer 200, so the second gate 204 can repair the damage of the mask layer 200 during the etching process, and can also fill the gap of the second trench 202 in FIG. 2B. Gap filling, even if the mask layer 200 is a non-conductive material, because the second gate 204 is disposed in the active region, the power MOS field effect transistor can operate smoothly.

3A through 3H are schematic cross-sectional views showing a manufacturing process of a power MOS field effect transistor in accordance with a second embodiment of the present invention.

Referring to FIG. 3A, a semiconductor layer 302 is formed on the substrate 300, and a first trench 302a is formed in the semiconductor layer 302. In addition, the well region 304 may be formed in the semiconductor layer 302 prior to forming the first trench 302a, but the invention is not limited thereto; that is, the well region 304 may also be formed in a subsequent process. The detailed manufacturing method, structure, and material of the semiconductor layer 302 and the well region 304 can be referred to the same components of the first embodiment, and thus will not be described again. Thereafter, a first thermal oxide layer 306, a tantalum nitride layer 308, and a CVD oxide layer 310 are sequentially formed on the surface of the first trench 302a, and then A first gate 312 is formed in a trench 302a. The detailed manufacturing method, structure, and material of the first thermal oxide layer 306 and the first gate 312 can be referred to the same components of the first embodiment, and thus will not be described again. The method of forming the tantalum nitride layer 308 is, for example, by chemical vapor deposition or other suitable film formation process. The tantalum nitride layer 308 can be used to prevent further diffusion of doping elements in the semiconductor layer 302, effectively isolating the semiconductor layer 302 from the subsequently formed conductor layer, so that the reliability of the power MOS field effect transistor of the second embodiment is achieved. Get promoted. The method of forming the CVD oxide layer 310 is, for example, a high temperature CVD process or a TEOS-based (low pressure) CVD process. In the present embodiment, the CVD oxide layer 310 is interposed between the first gate 312 and the tantalum nitride layer 308 to avoid interface defect problems caused by the first gate 312 directly contacting the tantalum nitride layer 308. Then, the first gate 312 is selectively implanted 314 to increase the oxidation efficiency of the first gate 312 in the thermal oxidation process.

Next, referring to FIG. 3B, a portion of the CVD oxide layer 310 is removed to expose the corners 316 of the first gate 312 and thin the CVD oxide layer 310. In the present embodiment, the method of removing a portion of the CVD oxide layer 310 is, for example, a wet etching process. In the present embodiment, exposing the corner 316 of the first gate 312 will facilitate subsequent thermal oxidation to fillet the first gate 312 to enhance the reliability of the power MOS field effect transistor.

Subsequently, referring to FIG. 3C, a thermal oxidation process is performed to form a second thermal oxide layer 318 and fillet the first gate 312. In this embodiment, by thermally oxidizing the first gate 312, the surface of the first gate 312 having a higher doping concentration can be oxidized faster to form a rounded corner 312a; that is, the first gate 312 does not have prominent fangs, so it can reduce input capacitance (such as: gate-source capacitance ( _Cgs )) or reduce reverse leakage current (for example: gate leakage current (I) _Gss )) can improve the reliability of power _MOS field effect transistors.

Then, referring to FIG. 3D, the remaining CVD oxide layer 310 on the sidewall of the first trench 302a is removed, and the tantalum nitride layer 308 on the sidewall of the first trench 302a is exposed. In the present embodiment, the method of removing the remaining CVD oxide layer 310 is, for example, a wet etching process. Since the other oxidation process is performed later, the remaining first thermal oxide layer 306 on the sidewall of the first trench 302a is removed, thereby avoiding the formation of additional oxides and causing the oxide layer of the well region 304 to be excessively thick. .

Next, referring to FIG. 3E, a third thermal oxide layer 320 is formed on the second thermal oxide layer 318, and another CVD oxide layer 322 is formed on the first gate 312 in the first trench 302a. The third thermal oxide layer 320 is formed, for example, by a thermal oxidation process. The formation of the third thermal oxide layer 320 can thicken the oxide layer on the first gate 312 to the thickness required for the component design. The detailed manufacturing method, structure, and material of the CVD oxide layer 322 can be referred to the same components of the first embodiment, and thus will not be described again.

Thereafter, referring to FIG. 3F, a mask layer 324 is formed on the CVD oxide layer 322 in the first trench 302a. The detailed manufacturing method, structure, and material of the mask layer 324 can be referred to the same components of the first embodiment, and thus will not be described again.

Then, referring to FIG. 3G, the mask layer 324 of FIG. 3F may be etched back (ie, an anisotropic etching process), and the exposed CVD oxide layer 322 is removed by using the mask layer 324a as an etching mask. Thereafter, the exposed tantalum nitride layer 308 is removed to form the first Two ditches 326. In the present embodiment, the mask layer 324a can protect the oxide between it and the first gate 312 (such as the second thermal oxide layer 318, the third thermal oxide layer 320, and the CVD oxide layer 322a).

Next, referring to FIG. 3H, a second gate 328 is formed in the second trench 326. The detailed manufacturing method of the second gate 328 can refer to the same components of the first embodiment, and therefore will not be described again. After the second gate 328 is formed, the source region 330 may be formed in the well region 304 by means of an implant process or the like. In the present embodiment, the mask layer 324a is a conductive material that can be used as the second gate of the power MOS field effect transistor, and since the mask layer 324a and the second gate 328 are not simultaneously formed, The material of the mask layer 324a may be different from the material of the second gate 328. In addition, since the oxide quality of the CVD oxide layer 322a is superior to that of the oxide layer formed by the thermal oxidation method, the CVD oxide layer 322a formed between the first gate 312 and the second gate 328 can be effectively isolated. A gate 312 and a second gate 328 enable the power MOS field effect transistor of the present embodiment to withstand higher potential without leakage. The first thermal oxide layer 306 located in the well region 304 can serve as a gate oxide layer, and the drain region (not shown) is typically disposed on the side of the substrate 300 where the semiconductor layer 302 is not formed. In addition, the height of the second gate 328 or the film layer on which an insulating layer (not shown) is disposed may be changed according to design.

4A to 4D are schematic cross-sectional views showing a manufacturing process of a modification of the second embodiment, in which the same or similar components are denoted by the same reference numerals as in the second embodiment, and the related description is not described herein.

Referring to FIG. 4A, after performing the process as described in FIG. 3A to FIG. 3F, The mask layer is etched back (ie, an anisotropic etching process) to obtain a mask layer 400 as shown in FIG. 4A, and the mask layer 400 is not only a conductive material such as a metal, a polysilicon or an amorphous germanium which can be used as a gate. In addition, a non-conductive material having a lower etching rate than the oxide, such as a non-conductive material such as tantalum nitride, may also be selected.

Then, referring to FIG. 4B, the exposed CVD oxide layer (FIG. 4A, 322) is removed with the mask layer 400 as an etch mask to expose a portion of the tantalum nitride layer 308. At this time, the mask layer 400 serves as a protective layer for protecting the CVD oxide layer 322a in the etching process.

Subsequently, referring to FIG. 4C, the exposed tantalum nitride layer 308 is removed to form a second trench 402.

Finally, referring to FIG. 4D, a second gate 404 is formed in the first trench 302a. The second gate 404 is formed, for example, by chemical vapor deposition, physical vapor deposition or other suitable film forming process on the semiconductor layer 302 and the first trench 302a, and the conductive layer is chemically mechanically Formed by a grinding process or an anisotropic etching process. Thereafter, source region 330 can be formed in well region 304. In the present embodiment, the mask layer 400 is, for example, a material having a lower etching rate than the oxide, and since the mask layer 400 is covered with the second gate 404, it is generally used as a gate. In addition to conductive materials such as metal, polysilicon, amorphous germanium, etc., the mask layer 400 may also use a non-conductive material (such as tantalum nitride) having a lower etching rate than the oxide, without affecting the power MOSFET. The operation of the crystal. Meanwhile, since the second gate 404 of the second embodiment covers the entire mask layer 400, the second gate 404 can also repair the damage that the mask layer 400 receives during the etching process.

In summary, the present invention effectively forms the CVD oxide layer between the first gate and the second gate to effectively improve the oxide quality between the first gate and the second gate. The power MOS field effect transistor can withstand higher operating voltage without leakage, thereby improving the reliability of the component itself. Further, the mask layer formed by the method of manufacturing the power MOS field effect transistor of the present invention can also be used as a part of the second gate, thereby increasing the variability of the process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (10)

A method for fabricating a power MOS field effect transistor, comprising: forming a semiconductor layer on a substrate; forming at least one first trench in the semiconductor layer; forming a first thermal oxide layer on a surface of the first trench Forming a tantalum nitride layer on the first thermal oxide layer; forming a first CVD oxide layer on the tantalum nitride layer; forming a first gate in the first trench; Forming a second CVD oxide layer on the first gate in a trench; forming a mask layer on the second CVD oxide layer in the first trench, wherein the mask layer and the first layer a second trench is disposed between the thermal oxide layers; and a second gate is formed in the second trench. The method of manufacturing a power MOS field effect transistor according to claim 1, wherein before the forming the second CVD oxide layer on the first gate in the first trench, Forming a second thermal oxide layer on the first gate. The method of manufacturing a power MOS field effect transistor according to claim 2, wherein the step of forming the second thermal oxide layer comprises: performing an implantation process on the first gate; Part of the first CVD oxide layer to expose a corner of the first gate and thin the first CVD oxide layer; and performing a thermal oxidation process to form the second thermal oxide layer The first gate is rounded. The method of manufacturing a power MOS field effect transistor according to claim 3, wherein before forming the second CVD oxide layer on the first gate and forming the second thermal oxide layer Thereafter, a third thermal oxide layer is further formed on the second thermal oxide layer. The method of fabricating a power MOS field effect transistor according to claim 1, wherein the method of forming the second CVD oxide layer on the first gate in the first trench comprises: Forming the second CVD oxide layer on the semiconductor layer and the first trench by a CVD process; forming the mask layer in the first trench to expose a portion of the second CVD oxide a layer; removing the exposed second CVD oxide layer with the mask layer as an etch mask to expose a portion of the tantalum nitride layer; and removing the exposed tantalum nitride layer to form The second ditch. The method of fabricating a power MOS field effect transistor according to claim 1, wherein the second gate further comprises covering the mask layer. The method of manufacturing a power MOS field effect transistor according to claim 6, wherein the mask layer comprises a conductive material or a non-conductive material. The method of manufacturing a power MOS field effect transistor according to claim 1, wherein the mask layer comprises a conductive material. The method of manufacturing a power MOS field effect transistor according to claim 1, wherein the method of forming the first CVD oxide layer and the second CVD oxide layer each comprise a high temperature CVD process or A CVD process using tetraethoxy decane (TEOS) as a raw material. The method of manufacturing the power MOS field effect transistor of claim 1, wherein after forming the first gate in the first trench, further comprising removing sidewalls of the first trench a portion of the first CVD oxide layer to thin the first CVD oxide layer.