JP5092313B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, a method for manufacturing the same, and a semiconductor integrated circuit device. In particular, the present invention is characterized by a configuration for improving high-frequency characteristics of a high voltage transistor having a dummy gate adjacent to a main gate for inputting a signal. The present invention relates to a semiconductor device, a manufacturing method thereof, and a semiconductor integrated circuit device.

  A high voltage MOSFET is used as a high frequency power amplifying element used in a transmission part of a mobile communication device such as a mobile phone. This transistor has not only good high frequency characteristics but also a large drain breakdown voltage, It is expected that it can be integrated on the same chip as the CMOS integrated circuit at low cost.

  Conventionally, such a high breakdown voltage MOSFET has been formed using a process of masking a low concentration drain region with a resist (see, for example, Patent Document 1).

In such a manufacturing method,
a. A mask process that aligns with the gate is necessary, making it difficult to make the gate finer.
b. Since gate injection cannot be performed at the same time as source / drain injection, the number of processes increases.
c. An additional step is required to prevent the low concentration drain region from being silicided.
There are problems such as.

On the other hand, as a solution to such a problem, it has been proposed to mask high concentration source / drain implantation by a dummy gate and a sidewall spacer (see, for example, Patent Document 2).
This proposal can solve the above-mentioned problems b and c.
Japanese Patent Laid-Open No. 11-186543 JP 2004-235527 A

  However, in the case of the above-mentioned Patent Document 2, a low-concentration drain region is formed in advance, a dummy gate is disposed thereon, and the main gate and the low-concentration drain region overlap each other. Since the alignment has to be performed, there is a problem that the problem a described above, that is, the problem that it is difficult to miniaturize the gate is still not solved.

Further, since the dummy gate is electrically floating, the parasitic capacitance C _dg may increase, thereby _causing problems such as poor high frequency characteristics and large variations in characteristics.

  Accordingly, an object of the present invention is to improve high-frequency characteristics of a high voltage transistor having a dummy gate and to improve manufacturing variations.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
Reference numerals 3 and 6 in the figure denote a gate insulating film and a sidewall, respectively.
In order to solve the above-described problem, the present invention provides a method of manufacturing a semiconductor device by implanting a first impurity into a semiconductor substrate to form a first impurity region of a first conductivity type, A step of implanting a second impurity into a part of the first impurity region to form a second impurity region to be a first low-concentration drain region of a second conductivity type having a conductivity type different from the first conductivity type; Forming a first gate insulating film and a gate electrode in the first impurity region, forming a second gate insulating film and a dummy gate in the second impurity region, and using the gate electrode and the dummy gate as a mask. A third impurity of the second conductivity type is implanted into the first impurity region and the second impurity region, so that a low-concentration source region is formed in the first impurity region, and a second impurity is formed in the second impurity region. Low Forming a third impurity region to be a concentration drain region ; forming an insulating film covering the gate electrode, the dummy gate, and the third impurity region; etching the insulating film; and a step of leaving the insulating film between the gate electrode while removing the insulating film from the surface and the dummy gate, the gate electrode, the dummy gate, and the insulating film remaining as a mask, the third Injecting a fourth impurity of the second conductivity type into the impurity region to form a fourth impurity region which becomes a source region in the first impurity region and a drain region in the second impurity region ; the a, the first depth of the relationship between the impurity regions to fourth impurity region, a second impurity region> fourth impurity regions> a third impurity region, and, With first impurity region> The fourth impurity regions, in the step of injecting a third impurity in a portion in contact with the second gate insulating film of the semiconductor substrate surface, as the second impurity region remains The third impurity is implanted.

By adopting such a configuration, it is possible to avoid an increase in parasitic resistance due to the low-concentration drain layer and the main gate 4 not sufficiently overlapping, and to suppress variation in characteristics.
Further, since it is not necessary to align the first low-concentration drain region 2 and the main gate 4, the gate length of the main gate 4 can be shortened, thereby improving high frequency characteristics.

In this case, it is desirable that the dummy gate 5 is connected to either the source region or the substrate 1, and thereby the dummy gate 5 does not float electrically, so that the parasitic capacitance C _dg does not increase, High frequency characteristics improve high frequency characteristics.

  For example, the connection to either the source region of the dummy gate 5 or the substrate 1 is performed using the contact plug 9 and the upper wiring layer 10 to the dummy gate 5, and in particular, the upper wiring layer 10 connects the main gate 4. It is desirable to arrange so that the electric field of the main gate 4 can be shielded.

  The gap between the main gate 4 and the dummy gate 5 is preferably filled with a sidewall spacer 7 formed on the gate sidewall, thereby masking implanted ions in the high concentration source / drain implantation step. And the number of processes can be reduced.

Further, the third impurity region ( second low-concentration drain region 8 ) is formed by ion implantation in a self-aligned manner with respect to the main gate 4 and the dummy gate 5 after the formation of the main gate 4 and the dummy gate 5. Since the alignment becomes unnecessary, the gate can be miniaturized.

  In the case of integration, the first low-concentration drain region 2 is used as the first conductive type in the complementary field-effect semiconductor device (CMOS) process when the first low-concentration drain is of the first conductive type. It is desirable to form well regions simultaneously using a well region forming step, whereby the increase in the number of steps can be suppressed and the cost can be reduced.

  Such a manufacturing process may be performed for either an n-channel element or a p-channel element, or may be performed for both an n-channel element or a p-channel element. is there.

  In the case of configuring a semiconductor integrated circuit device, the above-described semiconductor device may be monolithically integrated on the same substrate as the complementary field effect (CMOS) logic, memory, and analog circuit.

  According to the present invention, an LDD (Lightly Doped Drain) region is formed in a self-aligned manner with respect to a dummy gate provided on a main gate and a lightly doped drain region, thereby increasing the number of manufacturing steps without increasing the number of manufacturing steps. The high frequency characteristics of the transistor can be improved and the cost can be reduced.

  In the present invention, a dummy gate is provided on the first lightly doped drain region, and a second lightly doped drain region, that is, an LDD region is formed in a self-aligned manner by ion implantation using the main gate and the dummy gate as a mask. After forming the sidewall, the gap between the main gate and the dummy gate is filled with a sidewall spacer, and then ion implantation is performed as the main gate, the dummy gate, and the sidewall mask to form a high concentration source / drain region. A silicide electrode is formed on the main gate, the dummy gate and the high concentration source / drain region by a silicide process, and then the dummy gate and the high concentration source region are covered with the contact plug and the upper wiring layer so as to cover the main gate. The connection electrode which connects is formed.

  In this case, if the ion implantation step of the first low-concentration drain region is a step common to the N well implantation of the CMOS process and the LDD implantation is a step common to the implantation of the I / O transistor of the CMOS process, the CMOS A high voltage transistor can be fabricated without any additional steps to the process.

Here, with reference to FIG. 2 thru | or FIG. 5, the manufacturing process of the high voltage | pressure-resistant MOSFET of Example 1 of this invention is demonstrated.
See Figure 2
First, an element isolation region 12 having a shallow trench isolation structure is formed on a p-type silicon substrate 11 having a p-type impurity concentration of, for example, 1.0 × 10 ¹⁵ cm ⁻³ , and then B is ion-implanted. Thus, the p-type well region 13 having a B concentration of, for example, 1.0 × 10 ¹⁶ cm ⁻³ and a depth of 350 nm is formed.

Next, using the resist pattern 14 as a mask, P is ion-implanted into the p-type well region 13 using a process for forming an n-type well region of a CMOS process, and the P concentration is, for example, 1.0 × 10 ¹⁶ cm ⁻³ . An n-type well region 15 having a depth of 300 nm is formed.

  Next, after removing the resist pattern 14, thermal oxidation is performed to form a gate insulating film 16 having a thickness of, for example, 6 nm on the surface.

See Figure 3
Next, after depositing a polycrystalline silicon film on the entire surface, patterning is performed using a photolithography process to form a gate electrode 17 having a width of, for example, 300 nm and a dummy gate 18 having a width of, for example, 300 nm, The exposed portion of the gate insulating film 16 is also removed by etching.
Note that the gap between the gate electrode 17 and the dummy gate 18 is, for example, 200 nm.

Next, using the gate electrode 17 and the dummy gate 18 as a mask, P is ion-implanted using an I / O transistor implantation process in a CMOS process, so that the P concentration is, for example, 1.0 × 10 ¹⁹ cm ^−3. Thus, an n-type LDD region 19 having a depth of 50 nm is formed.

Next, the SiO ₂ film 20 is deposited thickly on the entire surface by CVD so as to completely fill the gap between the gate electrode 17 and the dummy gate 18.

See Figure 4
Next, sidewalls 21 are formed on the side walls of the gate electrode 17 and the dummy gate 18 by performing anisotropic etching.
At this time, the gap between the gate electrode 17 and the dummy gate 18 is filled with the sidewall spacer 22.

Next, ion implantation is performed using the gate electrode 17, the dummy gate 18, the side wall 21, and the side wall spacer 22 as a mask, so that the P concentration is, for example, 5.0 × 10 ²⁰ cm ⁻³ and the depth is 100 nm. ^{A +} type drain region 23 and an n ⁺ type source region 24 are formed.
Next, an activation annealing process is performed to activate the implanted ions.

Next, after depositing a Co film on the entire surface, heat treatment is performed to form Co silicide films 25 and 26 on the surfaces of the n ⁺ -type drain region 23, the n ⁺ -type source region 24, the gate electrode 17, and the dummy gate 18. After the unreacted Co film is washed out, a secondary heat treatment is performed to convert the Co silicide films 25 and 26 into low resistance phase Co silicide.

See Figure 5
Next, an etching stopper layer 27 made of a SiN film and an interlayer insulating film 28 made of a plasma TEOS-NSG film are sequentially formed on the entire surface, and then the surface of the interlayer insulating film 28 is planarized, and then the Co silicide films 25 and 26 are formed. Contact holes 29 and 30 reaching to are formed.

  Next, for example, after depositing a glue layer 31 made of TiN, for example, a W layer 32 is deposited by CVD to completely fill the contact hole, and then an unnecessary metal layer on the interlayer insulating film 28 is formed by CMP. The plugs 33 and 34 are formed by removing.

Next, after depositing a Cu film that forms the upper layer wiring on the entire surface, patterning into a predetermined shape, thereby forming the internal local wiring 35 that connects the dummy gate 18 and the n ⁺ type source region 24, The basic configuration of the high voltage MOSFET of Example 1 of the present invention is completed.

  As described above, in the present invention, even when the dummy gate is provided, the LDD region is formed by using the self-alignment process. Therefore, the parasitic resistance due to the n-type well region and the gate electrode not sufficiently overlapping. Can be avoided, and variations in characteristics can be suppressed.

  Further, since it is not necessary to align the n-type well region and the gate electrode, the gate length of the gate electrode can be shortened, thereby improving high frequency characteristics.

Furthermore, since the dummy gate is not electrically floated by connecting the dummy gate to the n ⁺ type source region, the parasitic capacitance C _dg does not increase and the high frequency characteristics are improved.

Particularly, since the internal local wiring connecting the dummy gate and the n + -type source region is formed so as to cover the gate electrode , the electric field from the gate electrode is shielded, thereby improving the high frequency characteristics.

  The embodiments of the present invention have been described above, but the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, the embodiments described in the above-described first embodiment The impurity concentration, depth, thickness, gate length, and gap length are merely examples, and are appropriately set according to the required high breakdown voltage characteristics and high frequency characteristics.

In the above embodiment, the dummy gate is connected to the n ⁺ type source region. However, as shown in the embodiment, when a p type silicon substrate is used, the dummy gate is formed on the p type silicon substrate. It can be connected.

Further, in the description of the above embodiment, the semiconductor integrated circuit device in which the high voltage MOSFET is monolithically integrated with the CMOS logic, the memory, and the analog circuit is described in mind. It may be formed individually as a discrete device.
In this case, the impurity concentration and depth of each region can be arbitrarily set without being affected by other regions and processes.

In the above embodiment, the high-breakdown-voltage MOSFET is described as an n-channel MOSFET. However, the high-voltage MOSFET may be formed as a p-channel MOSFET. What is necessary is just to reverse a conductivity type.
Further, the n-channel high voltage MOSFET and the p-channel high voltage MOSFET may be formed on the same substrate.

  As an application example of the present invention, a high-frequency power amplifying element used in a transmission part of a mobile communication device such as a mobile phone is typical. However, when high breakdown voltage and high-frequency characteristics are required in other applications. Is also applicable.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 4 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 First low concentration drain region 3 Gate insulating film 4 Main gate 5 Dummy gate 6 Side wall 7 Side wall spacer 8 Second low concentration drain region 9 Contact plug 10 Upper wiring layer 11 P-type silicon substrate 12 Element isolation Region 13 p-type well region 14 resist pattern 15 n-type well region 16 gate insulating film 17 gate electrode 18 dummy gate 19 n-type LDD region 20 SiO ₂ film 21 side wall 22 side wall spacer 23 n ⁺ type drain region 24 n ⁺ type Source region 25 Co silicide film 26 Co silicide film 27 Etching stopper layer 28 Interlayer insulating film 29 Contact hole 30 Contact hole 31 Glue layer 32 W layer 33 Plug 34 Plug 35 Internal local wiring

Claims (1)

Injecting a first impurity into a semiconductor substrate to form a first impurity region of a first conductivity type;
A second impurity is implanted into a part of the first impurity region to form a second impurity region to be a first low-concentration drain region of a second conductivity type having a conductivity type different from the first conductivity type. Process,
Forming a first gate insulating film and a gate electrode in the first impurity region, and forming a second gate insulating film and a dummy gate in the second impurity region;
Using the gate electrode and the dummy gate as a mask, a third impurity of the second conductivity type is implanted into the first impurity region and the second impurity region, and a low-concentration source region is formed in the first impurity region, and Forming a third impurity region to be a second low-concentration drain region in the second impurity region ;
Forming an insulating film covering the gate electrode, the dummy gate, and the third impurity region;
Etching the insulating film, removing the insulating film from the surface of the semiconductor substrate and leaving the insulating film between the gate electrode and the dummy gate ;
Using the gate electrode, the dummy gate, and the remaining insulating film as a mask, the fourth impurity of the second conductivity type is implanted into the third impurity region to become a source region in the first impurity region, and Forming a fourth impurity region to be a drain region in the second impurity region ;
Have
The depth relationship between the first impurity region to the fourth impurity region is second impurity region> fourth impurity region> third impurity region, and first impurity region> fourth impurity region,
In the step of implanting the third impurity, the third impurity is implanted so that the second impurity region remains in a portion of the surface of the semiconductor substrate that is in contact with the second gate insulating film. A method for manufacturing a semiconductor device.

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