CN115692419A

CN115692419A - Semiconductor structure and forming method thereof

Info

Publication number: CN115692419A
Application number: CN202110864522.6A
Authority: CN
Inventors: 汪涵
Original assignee: North Ic Technology Innovation Center Beijing Co ltd
Current assignee: North Ic Technology Innovation Center Beijing Co ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2023-02-03

Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises a substrate, the substrate comprising adjacent first and second regions; a plurality of channel layers respectively located on the first region and the second region; the side wall is positioned between the adjacent channel layers; source-drain doped layers positioned on two sides of the stacked channel layers; the grid structure is positioned on the substrate, surrounds the channel layers and spans the first region and the second region; the dielectric layer is positioned on the substrate, covers the side wall of the grid structure, and the top surface of the dielectric layer is higher than that of the grid structure, so that a conductive opening is formed in the dielectric layer and exposes the top surface of the grid structure; and the conductive layer is positioned in the conductive opening and is connected with the grid structure positioned on the first region and the second region. The semiconductor structure can simplify an electric connection structure between the grid structure on the first region and the grid structure on the second region, so that the process steps are simplified, and the process difficulty is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

Complementary Metal-Oxide-Semiconductor (CMOS) transistors have become a common Semiconductor device in integrated circuits. The CMOS transistor includes: p-type metal oxide semiconductor (PMOS) transistors and N-type metal oxide semiconductor (NMOS) transistors.

As the element density and integration of semiconductor devices increase, the gate size of PMOS transistors or NMOS transistors becomes shorter than ever before. However, the gate size of the PMOS transistor or the NMOS transistor becomes short, which causes short channel effect, further generating leakage current, and affecting the electrical performance of the CMOS transistor. In the prior art, the carrier mobility is improved mainly by improving the stress of a channel region of a transistor, so that the driving current of the transistor is improved, and the leakage current in the transistor is reduced.

In the prior art, in order to increase the stress of the channel region of the PMOS transistor or the NMOS transistor, stress layers are formed in the source region and the drain region of the PMOS transistor or the NMOS transistor. The stress layer of the PMOS transistor is made of germanium-silicon (SiGe), and the silicon and the germanium-silicon form compressive stress due to lattice mismatch, so that the performance of the PMOS transistor is improved; the stress layer of the NMOS transistor is made of silicon carbide (SiC), and the silicon and the SiC form tensile stress due to lattice mismatch, so that the performance of the NMOS transistor is improved.

However, the prior art still has many problems in the process of CMOS transistors.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can effectively reduce the process difficulty and improve the performance of the semiconductor structure.

To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate comprising adjacent first and second regions, devices formed on the first and second regions being the same or different; the first channel layer, the second channel layer and the third channel layer are respectively positioned on the first region and the second region, and the first channel layer, the second channel layer and the third channel layer are sequentially stacked along the normal direction of the surface of the substrate; the first inner side wall is positioned between the first channel layer and the substrate, the first inner side wall is positioned on the substrate and supports two ends of the first channel layer, and the end face of the first inner side wall and the end face of the first channel layer are in a common vertical plane; the second inner side wall is positioned between the first channel layer and the second channel layer, the second inner side wall is positioned on the first channel layer and supports two ends of the second channel layer, and the end surface of the second inner side wall and the end surface of the second channel layer are in a common vertical plane; the third inner side wall is positioned between the second channel layer and the third channel layer, the third inner side wall is positioned on the second channel layer and supports two ends of the third channel layer, and the end surface of the third inner side wall and the end surface of the third channel layer are in a coplanar vertical plane; the source-drain doping layers are positioned on two sides of the stacked first channel layer, second channel layer and third channel layer, and the source-drain doping layers are connected with the end parts of the first channel layer, the second channel layer, the third channel layer, the first inner side wall, the second inner side wall and the third inner side wall; a gate structure on the substrate, the gate structure surrounding the first, second and third channel layers in a direction perpendicular to an extension direction of the first, second and third channel layers, and the gate structure crossing the first and second regions; a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the gate structure, and a top surface of the dielectric layer being higher than a top surface of the gate structure, such that a conductive opening is formed in the dielectric layer, the conductive opening exposing the top surface of the gate structure; a conductive layer within the conductive opening, the conductive layer connecting the gate structures on the first and second regions.

Optionally, the method further includes: a fourth channel layer on the third channel layer; and the fourth inner side wall is positioned on the third channel layer and supports two ends of the fourth channel layer, and the end surface of the fourth inner side wall is coplanar with the end surface of the fourth channel layer.

Optionally, the method further includes: a fifth channel layer on the fourth channel layer; and the fifth inner side wall is positioned between the fourth channel layer and the fifth channel layer, the fifth inner side wall is positioned on the fourth channel layer and supports two ends of the fifth channel layer, and the end surface of the fifth inner side wall is coplanar with the end surface of the fifth channel layer.

Optionally, the material of the conductive layer comprises a metal; the metal comprises aluminum.

Optionally, the gate structure on the first region and the gate structure on the second region are separately formed, and a gate dielectric layer is provided between the gate structure on the first region and the gate structure on the second region.

Optionally, the gate structure on the first region and the gate structure on the second region are formed simultaneously.

Optionally, the source-drain doped layer located on the first region has first source-drain ions; and second source drain ions are arranged in the source drain doped layer on the second region, and the electrical types of the first source drain ions and the second source drain ions are different.

Optionally, the materials of the first channel layer, the second channel layer, and the third channel layer include silicon.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising adjacent first and second regions, the devices formed on the first and second regions being the same or different; forming a first channel layer, a second channel layer and a third channel layer on the first region and the second region respectively, wherein the first channel layer, the second channel layer and the third channel layer are stacked in sequence along the normal direction of the surface of the substrate; forming a first inner side wall, a second inner side wall and a third inner side wall, wherein the first inner side wall is located between the first channel layer and the substrate, the first inner side wall is located on the substrate and supports two ends of the first channel layer, the end surface of the first inner side wall is coplanar with the end surface of the first channel layer, the second inner side wall is located between the first channel layer and the second channel layer, the second inner side wall is located on the first channel layer and supports two ends of the second channel layer, the end surface of the second inner side wall is coplanar with the end surface of the second channel layer, the third inner side wall is located between the second channel layer and the third channel layer, the third inner side wall is located on the second channel layer and supports two ends of the third channel layer, and the end surface of the third inner side wall is coplanar with the third end surface; the source-drain doping layers are arranged on two sides of the stacked first channel layer, the second channel layer and the third channel layer and are connected with the end parts of the first channel layer, the second channel layer, the third channel layer, the first inner side wall, the second inner side wall and the third inner side wall; forming a dielectric layer and a gate structure on the substrate, wherein the gate structure surrounds the first channel layer, the second channel layer and the third channel layer along an extending direction perpendicular to the first channel layer, the second channel layer and the third channel layer, the gate structure stretches across the first region and the second region, the dielectric layer covers the side wall of the gate structure, and the top surface of the dielectric layer is flush with the top surface of the gate structure; etching the grid structure back to enable the top surface of the dielectric layer to be higher than the top surface of the grid structure, forming a conductive opening in the dielectric layer, and enabling the conductive opening to expose the top surface of the grid structure; and forming a conductive layer in the conductive opening, wherein the conductive layer is connected with the gate structures on the first region and the second region.

Optionally, before forming the gate structure and the dielectric layer, the method further includes: forming a dummy gate structure on the substrate, the dummy gate structure crossing the first, second, and third channel layers in a direction perpendicular to an extending direction of the first, second, and third channel layers, and the gate structure crossing the first and second regions; the dielectric layer covers the side wall of the pseudo gate structure.

Optionally, the forming method of the gate structure includes: forming a first patterning layer on the dielectric layer, wherein part of the pseudo gate structure is exposed out of the first patterning layer; etching the pseudo gate structure by taking the first patterning layer as a mask, and forming a first gate opening in the dielectric layer, wherein the first gate opening is positioned in the first region; forming the gate structure in the first gate opening on the first region, wherein the gate structure comprises a gate dielectric layer on the side wall and the bottom surface of the first gate opening and a gate layer on the gate dielectric layer; after the grid electrode structure is formed on the first area, removing the first patterning layer, and forming a second patterning layer on the dielectric layer, wherein the second patterning layer exposes another part of the pseudo grid electrode structure; etching the pseudo gate structure by taking the second patterning layer as a mask, and forming a second gate opening in the dielectric layer, wherein the second gate opening is positioned in the second region; and forming the grid structure in the second grid opening on the second area, wherein the grid structure comprises a grid dielectric layer positioned on the side wall and the bottom surface of the second grid opening and a grid layer positioned on the grid dielectric layer.

Optionally, the method for forming the conductive layer in the conductive opening includes: forming a conductive material layer in the conductive opening and on the top surface of the dielectric layer; and carrying out planarization treatment on the conductive material layer until the top surface of the dielectric layer is exposed, so as to form the conductive layer.

Optionally, a source-drain doped layer located on the first region has first source-drain ions; and second source drain ions are arranged in the source drain doped layer on the second region, and the electrical types of the first source drain ions and the second source drain ions are different.

Optionally, the first source-drain ions include N-type ions or P-type ions; the second source-drain ions comprise P-type ions or N-type ions.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the structure of the technical scheme of the invention comprises a conductive opening positioned in the dielectric layer, wherein the conductive opening exposes the top surface of the grid structure positioned on the first region and the second region; a conductive layer within the conductive opening, the conductive layer connecting the gate structures on the first and second regions. The electric connection structure between the grid electrode structures on the first region and the second region can be simplified, so that the process steps are simplified, and the process difficulty is reduced.

In the forming method of the technical scheme, the top surface of the dielectric layer is higher than that of the grid structure by back etching the grid structure, a conductive opening is formed in the dielectric layer, and the conductive opening is exposed out of the top surface of the grid structure; and forming a conductive layer in the conductive opening, wherein the conductive layer is connected with the gate structures on the first region and the second region. The electric connection structure between the grid electrode structures on the first region and the second region can be simplified, so that the process steps are simplified, and the process difficulty is reduced.

Drawings

FIGS. 1 and 2 are schematic structural diagrams of a semiconductor structure;

fig. 3 to 19 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the present invention.

Detailed Description

As mentioned in the background, the prior art still has problems in the process of CMOS transistors. The following detailed description will be made in conjunction with the accompanying drawings.

Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 has a first fin structure 101 and a second fin structure 102 arranged in parallel along a first direction X; a first gate structure 103, a second gate structure 104 and a first dielectric layer 105 are formed on the substrate 100, the first gate structure 103 crosses the first fin structure 101, a first source-drain doping layer (not shown) is arranged in the first fin structure 101 on two sides of the first gate structure 103, first source-drain ions are arranged in the first source-drain doping layer, the second gate structure 104 crosses the second fin structure 102, a second source-drain doping layer is arranged in the second fin structure 102 on two sides of the second gate structure 104, second source-drain ions are arranged in the second source-drain doping layer, the first source-drain ions are different from the second source-drain ions in electrical type, and the first dielectric layer 105 covers the side walls of the first gate structure 103 and the second gate structure 104.

Referring to fig. 2, a second dielectric layer 106 is formed on the first dielectric layer 105; forming a first conductive plug 107 and a second conductive plug 108 in the second dielectric layer 106, wherein the first conductive plug 107 is electrically connected with the first gate structure 103, and the second conductive plug 108 is electrically connected with the second gate structure 104; a conductive layer 109 is formed in the second dielectric layer 106, and the conductive layer 109 is electrically connected to the first conductive plug 107 and the second conductive plug 108, respectively.

In this embodiment, a CMOS transistor is formed by electrically connecting the formed NMOS transistor and PMOS transistor.

However, in this embodiment, the first conductive plug 107 and the second conductive plug 108 are formed to be electrically connected to the first gate structure 103 and the second gate structure 104, respectively, and then the conductive layer 109 is electrically connected to the first conductive plug 107 and the second conductive plug 108, respectively, so as to realize the electrical connection between the NMOS transistor and the PMOS transistor. The process is not only complicated, but also the first conductive plug 107 and the second conductive plug 108 have small volumes and large contact resistance with the first gate structure 103 and the second gate structure 104, thereby affecting the performance of the finally formed semiconductor structure.

On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein a conductive opening is formed in the dielectric layer and a conductive layer is formed in the conductive opening by back etching a part of the first gate dielectric structure and a part of the second gate dielectric structure at the joint of the first gate structure and the second gate structure, and the conductive layers are respectively and electrically connected with the first gate structure and the second gate structure. The electric connection structure between the grid electrode structures on the first region and the second region can be simplified, so that the process steps are simplified, and the process difficulty is reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 19 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 3, a substrate 200 is provided, where the substrate 200 includes a first region I and a second region II adjacent to each other, and devices formed on the first region I and the second region II may be the same or different.

In this embodiment, the substrate 200 is made of silicon.

With reference to fig. 3, a plurality of channel layers and a plurality of sacrificial layers are formed on the first region I and the second region II, respectively, and the plurality of channel layers and the plurality of sacrificial layers are stacked at intervals along a normal direction of the surface of the substrate 200.

In this embodiment, several of the channel layers include: a first channel layer 201, a second channel layer 202, and a third channel layer 203; a number of the sacrificial layers include: a first sacrificial layer 204, a second sacrificial layer 205 and a third sacrificial layer 206, wherein the first sacrificial layer 204 is located between the first channel layer 201 and the substrate 200, the second sacrificial layer 205 is located between the first channel layer 201 and the second channel layer 202, and the third sacrificial layer 206 is located between the second channel layer 202 and the third channel layer 203.

In the present embodiment, the materials of the first channel layer 201, the second channel layer 202, and the third channel layer 203 are different from the materials of the first sacrificial layer 204, the second sacrificial layer 205, and the third sacrificial layer 206; the purpose of the method is to remove the first sacrificial layer 204, the second sacrificial layer 205 and the third sacrificial layer 206 when a gate structure is formed subsequently, so that the first sacrificial layer 204, the second sacrificial layer 205 and the third sacrificial layer 206 made of different materials have a larger etching selection ratio with respect to the first channel layer 201, the second channel layer 202 and the third channel layer 203, and damage to the first channel layer 201, the second channel layer 202 and the third channel layer 203 in a process of removing the first sacrificial layer 204, the second sacrificial layer 205 and the third sacrificial layer 206 is reduced.

In this embodiment, the material of the first sacrificial layer 204, the second sacrificial layer 205 and the third sacrificial layer 206 is silicon germanium, and the material of the first channel layer 201, the second channel layer 202 and the third channel layer 203 is silicon.

In other embodiments, the method may further include: a fourth channel layer on the third channel layer; a fourth sacrificial layer between the third channel layer and the fourth channel layer.

In other embodiments, the method may further include: a fifth channel layer on the fourth channel layer; a fifth sacrificial layer between the fourth channel layer and the fifth channel layer.

Referring to fig. 4, after forming several sacrificial layers and several channel layers, an isolation layer 220 is formed on the substrate 200.

In this embodiment, the method for forming the isolation layer 220 includes: forming an isolation material layer (not shown) on the substrate 200, the isolation material layer covering the sacrificial layers and the channel layers; the isolation material layer is etched back to form the isolation layer 220.

The material of the isolation layer 220 includes silicon oxide or silicon nitride. In this embodiment, the material of the isolation layer 220 is silicon oxide.

Referring to fig. 5, after the isolation layer 220 is formed, a dummy gate structure 207 is formed on the substrate 200, wherein the dummy gate structure 207 crosses the first channel layer 201, the second channel layer 202, and the third channel layer 203 along a direction perpendicular to an extending direction of the first channel layer 201, the second channel layer 202, and the third channel layer 203, and the gate structure crosses the first region I and the second region II.

In this embodiment, the dummy gate structure 207 also spans the first sacrificial layer 204, the second sacrificial layer 205, and the third sacrificial layer 206.

In this embodiment, the dummy gate structure 206 includes: the gate structure comprises a pseudo gate dielectric layer, a pseudo gate layer positioned on the pseudo gate dielectric layer, and side walls (not marked) positioned on the pseudo gate dielectric layer and the side walls of the pseudo gate layer.

In this embodiment, the material of the dummy gate dielectric layer is silicon oxide.

In this embodiment, the material of the dummy gate layer is polysilicon; in other embodiments, the material of the dummy gate layer may also be amorphous silicon.

In this embodiment, the sidewall spacer is made of silicon nitride.

Referring to fig. 6 to 8, fig. 6 isbase:Sub>A top view ofbase:Sub>A semiconductor structure, fig. 7 isbase:Sub>A schematic cross-sectional view taken alongbase:Sub>A linebase:Sub>A-base:Sub>A in fig. 6, fig. 8 isbase:Sub>A schematic cross-sectional view taken alongbase:Sub>A line B-B in fig. 6, and the first channel layer 201, the second channel layer 202, the third channel layer 203, the first sacrificial layer 204, the second sacrificial layer 205, and the third sacrificial layer 206 are respectively etched by using the dummy gate structure 206 asbase:Sub>A mask to formbase:Sub>A source-drain groove 214.

In this embodiment, the source/drain recess 214 functions to provide a space for the source/drain doping layer to be formed subsequently.

Referring to fig. 9 and 10, the directions of the views in fig. 9 and 7 are the same, and the direction of the view in fig. 10 is the same as the direction of the view in fig. 8, and the portions of the first sacrificial layer 204, the second sacrificial layer 205, and the third sacrificial layer 206 exposed by the source-drain grooves 214 are etched back to form a first isolation groove 208, a second isolation groove 209, and a third isolation groove 210.

In the present embodiment, the first isolation recess 208 is located between the substrate 200 and the first channel layer 201, the second isolation recess 209 is located between the first channel layer 201 and the second channel layer 202, and the third isolation recess 210 is located between the second channel layer 202 and the third channel layer 203.

In the present embodiment, the first isolation groove 208, the second isolation groove 209, and the third isolation groove 210 function to provide a space for the first inner sidewall, the second inner sidewall, and the third inner sidewall to be formed later. The first inner side wall, the second inner side wall and the third inner side wall can ensure the electrical isolation between the subsequently formed gate structure and the source drain doping layer.

Referring to fig. 11 and 12, a first inner sidewall 211 is formed in the first isolation groove 208, a second inner sidewall 212 is formed in the second isolation groove 209, and a third inner sidewall 213 is formed in the third isolation groove 210.

In this embodiment, the first inner side wall 211 is located between the first channel layer 201 and the substrate 200, the first inner side wall 211 is located on the substrate 200 and supports two ends of the first channel layer 201, an end surface of the first inner side wall 211 and an end surface of the first channel layer 201 are coplanar, the second inner side wall 212 is located between the first channel layer 201 and the second channel layer 202, the second inner side wall 212 is located on the first channel layer 201 and supports two ends of the second channel layer 202, an end surface of the second inner side wall 212 and an end surface of the second channel layer 202 are coplanar, the third inner side wall 213 is located between the second channel layer 202 and the third channel layer 203, the third inner side wall 213 is located on the second channel layer 202 and supports two ends of the third channel layer 203, and an end surface of the third inner side wall 213 and an end surface of the third channel layer 203 are coplanar.

In this embodiment, the method for forming the first inner sidewall 211, the second inner sidewall 212, and the third inner sidewall 213 includes: forming first initial inner side walls (not shown) in the first, second and

third isolation grooves

208, 209 and 210, the sidewalls and the bottom surfaces of the source and drain grooves 214, and the sidewalls and the top surface of the dummy gate structure 207; etching back the first initial inner side wall until the bottom surface of the source/drain groove 214 and the top surface of the dummy gate structure 207 are exposed, so as to form a second initial inner side wall (not shown); and etching back the second initial inner side wall until the side walls of the pseudo gate structure 207, the first channel layer 201, the second channel layer 202 and the third channel layer 203 are exposed, so as to form the first inner side wall 211, the second inner side wall 212 and the third inner side wall 213.

The process for forming the first initial inner side wall comprises a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the first initial inner sidewall uses an atomic layer deposition process.

In this embodiment, the materials of the first inner side wall 211, the second inner side wall 212, and the third inner side wall 213 are silicon nitride.

Referring to fig. 13 and 14, after the first inner sidewall 211, the second inner sidewall 212, and the third inner sidewall 213 are formed, a source-drain doped layer 215 is formed in the source-drain groove 214, wherein a first source-drain ion is located in the source-drain doped layer 215 on the first region I; and second source-drain ions are arranged in the source-drain doping layer 215 positioned on the second region II, and the electrical types of the first source-drain ions and the second source-drain ions are different.

In this embodiment, the source/drain doping layer 215 is connected to end portions of the first channel layer 201, the second channel layer 202, the third channel layer 203, the first inner sidewall 211, the second inner sidewall 212, and the third inner sidewall 213.

The first source drain ions comprise N-type ions or P-type ions; the second source-drain ions comprise P-type ions or N-type ions. In this embodiment, the first source-drain ions are N-type ions, and the second source-drain ions are P-type ions.

In this embodiment, a CMOS transistor is constituted by the formed PMOS transistor and NMOS transistor.

Referring to fig. 15, after the source-drain doping layer 215 is formed, a dielectric layer 216 is formed on the substrate 200, the dielectric layer 216 covers the dummy gate structure 207, and the dielectric layer 216 exposes the top surface of the dummy gate structure 207.

In this embodiment, the dielectric layer 217 is made of silicon oxide.

Referring to fig. 16, the dummy gate structure 207 is removed, the gate structure 217 is formed in the dielectric layer 216, and the gate structure 217 crosses over the first region I and the second region II.

In this embodiment, the gate structure 217 on the first region I and the gate structure 217 on the second region II are separately formed.

In this embodiment, the method for forming the gate structure 217 includes: forming a first patterning layer (not shown) on the dielectric layer 216, wherein the first patterning layer exposes a part of the dummy gate structure 207; etching the dummy gate structure 207 by using the first patterning layer as a mask, and forming a first gate opening (not shown) in the dielectric layer 216, where the first gate opening is located in the first region I; forming the gate structure 217 in the first gate opening located on the first region I, where the gate structure 217 includes a gate dielectric layer located on a sidewall and a bottom surface of the first gate opening, and a gate layer (not labeled) located on the gate dielectric layer; after forming the gate structure 217 on the first region I, removing the first patterning layer, and forming a second patterning layer (not shown) on the dielectric layer 216, the second patterning layer exposing another portion of the dummy gate structure 207; etching the dummy gate structure 207 by using the second patterning layer as a mask, and forming a second gate opening (not shown) in the dielectric layer 216, where the second gate opening is located in the second region II; and forming the gate structure 217 in the second gate opening on the second region II, where the gate structure 217 includes a gate dielectric layer on the sidewall and the bottom surface of the second gate opening, and a gate layer on the gate dielectric layer.

In this embodiment, after forming the first gate opening, the method further includes: removing the first, second and third

sacrificial layers

204, 205 and 206 on the first region I to form a first gate trench (not shown), the gate structure 217 formed on the first region I also being located in the first gate trench to surround the first, second and third channel layers 201, 202 and 203 on the first region I; after forming the second gate opening, further comprising: the first sacrificial layer 204, the second sacrificial layer 205 and the third sacrificial layer 206 on the second region II are removed to form a second gate trench (not shown), and the gate structure 217 formed on the second region II is also located in the second gate trench to surround the first channel layer 201, the second channel layer 202 and the third channel layer 203 on the second region II.

The material of the gate layer is metal, and the metal material comprises one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum. In this embodiment, the material of the gate layer is tungsten.

In other embodiments, the gate structure on the first region and the gate structure on the second region are formed simultaneously. The specific forming method comprises the steps of removing the pseudo gate structures on the first region and the second region, and the first sacrificial layer, the second sacrificial layer and the third sacrificial layer on the first region and the second region at the same time to form a gate opening and a gate groove; and forming the gate structure in the gate opening and the gate groove.

Referring to fig. 17, after forming the gate structure 217 such that the top surface of the dielectric layer 216 is higher than the top surface of the gate structure 217, a conductive opening 218 is formed in the dielectric layer 216, wherein the conductive opening 218 exposes the top surface of the gate structure 217.

In this embodiment, the gate structure 217 is etched back, such that the top surface of the dielectric layer 216 is higher than the top surface of the gate structure 217, a conductive opening 218 is formed in the dielectric layer 216, and the conductive opening 218 exposes the top surface of the gate structure 217; and subsequently forming a conductive layer within the conductive opening 218, the conductive layer connecting the gate structures 217 located on the first region I and the second region II. The electric connection structure between the gate structures 217 on the first region I and the second region II can be simplified, so that the process steps are simplified, and the process difficulty is reduced.

Referring to fig. 18 and 19, fig. 18 is a perspective view of a semiconductor structure, and fig. 19 is a schematic view of a cross-section taken along line C-C in fig. 18, wherein a conductive layer 219 is formed in the conductive opening 218, and the conductive layer 219 is connected to the gate structure 217 located on the first region I and the second region II.

In this embodiment, the method of forming the conductive layer 219 in the conductive opening 218 includes: forming a layer of conductive material (not shown) within the conductive opening 218 and on a top surface of the dielectric layer 216; the conductive material layer is planarized until the top surface of the dielectric layer 216 is exposed, forming the conductive layer 219.

In this embodiment, the material of the conductive layer 219 includes a metal; the metal is aluminum.

Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, with reference to fig. 19, including: a substrate 200, wherein the substrate 200 comprises a first area I and a second area II which are adjacent to each other, and devices formed on the first area I and the second area II can be the same or different; a first channel layer 201, a second channel layer 202 and a third channel layer 203 respectively located on the first region I and the second region II, wherein the first channel layer 201, the second channel layer 202 and the third channel layer 203 are sequentially stacked along a normal direction of a surface of the substrate 200; the first inner side wall 211 is located between the first channel layer 201 and the substrate 200, the first inner side wall 211 is located on the substrate 200 and supports two ends of the first channel layer 201, and an end surface of the first inner side wall 211 and an end surface of the first channel layer 201 share a vertical surface; a second inner side wall 212 located between the first channel layer 201 and the second channel layer 202, where the second inner side wall 212 is located on the first channel layer 201 and supports two ends of the second channel layer 202, and an end surface of the second inner side wall 212 and an end surface of the second channel layer 202 are coplanar; a third inner side wall 213 located between the second channel layer 202 and the third channel layer 203, where the third inner side wall 213 is located on the second channel layer 202 and supports two ends of the third channel layer 203, and an end surface of the third inner side wall 213 and an end surface of the third channel layer 203 share a vertical surface; the source-drain doping layers 215 are located on two sides of the stacked first channel layer 201, second channel layer 202 and third channel layer 203, and the source-drain doping layers 215 are connected with the ends of the first channel layer 201, the second channel layer 202 and the third channel layer 203, the first inner side wall 211, the second inner side wall 212 and the third inner side wall 213; a gate structure 217 on the substrate 200, the gate structure 217 surrounding the first, second and third channel layers 201, 202 and 203 in a direction perpendicular to an extension direction of the first, second and third channel layers 201, 202 and 203, and the gate structure 217 crossing the first and second regions I and II; a dielectric layer 216 on the substrate 200, wherein the dielectric layer 216 covers sidewalls of the gate structure 217, and a top surface of the dielectric layer 216 is higher than a top surface of the gate structure 217, such that a conductive opening 218 is formed in the dielectric layer 217, and the conductive opening 218 exposes the top surface of the gate structure 217; a conductive layer 219 located within the conductive opening 218, the conductive layer 219 connecting the gate structure 217 located on the first region I and the second region II.

In this embodiment, the semiconductor structure can simplify an electrical connection structure between the gate structure 217 on the first region I and the gate structure 217 on the second region II, thereby simplifying the process steps and reducing the process difficulty.

In other embodiments, further comprising: a fourth channel layer on the third channel layer; and the fourth inner side wall is positioned between the third channel layer and the fourth channel layer, positioned on the third channel layer and supports two ends of the fourth channel layer, and the end surface of the fourth inner side wall is coplanar with the end surface of the fourth channel layer.

In other embodiments, further comprising: a fifth channel layer on the fourth channel layer; and the fifth inner side wall is positioned between the fourth channel layer and the fifth channel layer, the fifth inner side wall is positioned on the fourth channel layer and supports two ends of the fifth channel layer, and the end surface of the fifth inner side wall and the end surface of the fifth channel layer are in a common vertical plane.

In this embodiment, the material of the conductive layer 219 includes metal; the metal is aluminum.

In this embodiment, the gate structure 217 on the first region I and the gate structure 217 on the second region II are separately formed, and a gate dielectric layer is provided between the gate structure 217 on the first region 7 and the gate structure 217 on the second region 77.

In other embodiments, the gate structure on the first region and the gate structure on the second region are formed simultaneously.

In this embodiment, the source-drain doped layer 215 located on the first region I has first source-drain ions therein; and second source-drain ions are arranged in the source-drain doping layer 215 on the second region II, and the electrical types of the first source-drain ions and the second source-drain ions are different.

In the present embodiment, the materials of the first channel layer 201, the second channel layer 202, and the third channel layer 203 include silicon.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising adjacent first and second regions, devices formed on the first and second regions may be the same or different;

the first channel layer, the second channel layer and the third channel layer are respectively positioned on the first area and the second area, and are sequentially stacked along the normal direction of the surface of the substrate;

the first inner side wall is positioned between the first channel layer and the substrate, the first inner side wall is positioned on the substrate and supports two ends of the first channel layer, and the end face of the first inner side wall and the end face of the first channel layer are in a common vertical plane;

the second inner side wall is positioned between the first channel layer and the second channel layer, the second inner side wall is positioned on the first channel layer and supports two ends of the second channel layer, and the end surface of the second inner side wall and the end surface of the second channel layer are in a common vertical plane;

the third inner side wall is positioned between the second channel layer and the third channel layer, the third inner side wall is positioned on the second channel layer and supports two ends of the third channel layer, and the end surface of the third inner side wall and the end surface of the third channel layer are in a coplanar vertical plane;

the source-drain doping layers are positioned on two sides of the stacked first channel layer, the second channel layer and the third channel layer and are connected with the end parts of the first channel layer, the second channel layer, the third channel layer, the first inner side wall, the second inner side wall and the third inner side wall;

a gate structure on the substrate, the gate structure surrounding the first, second and third channel layers in a direction perpendicular to an extension direction of the first, second and third channel layers, and the gate structure crossing the first and second regions;

a dielectric layer located on the substrate, the dielectric layer covering the sidewalls of the gate structure, and the top surface of the dielectric layer being higher than the top surface of the gate structure, such that a conductive opening is formed in the dielectric layer, the conductive opening exposing the top surface of the gate structure;

a conductive layer within the conductive opening, the conductive layer connecting the gate structures on the first and second regions.

2. The semiconductor structure of claim 1, further comprising: a fourth channel layer on the third channel layer; and the fourth inner side wall is positioned between the third channel layer and the fourth channel layer, positioned on the third channel layer and supports two ends of the fourth channel layer, and the end surface of the fourth inner side wall is coplanar with the end surface of the fourth channel layer.

3. The semiconductor structure of claim 2, further comprising: a fifth channel layer on the fourth channel layer; and the fifth inner side wall is positioned between the fourth channel layer and the fifth channel layer, the fifth inner side wall is positioned on the fourth channel layer and supports two ends of the fifth channel layer, and the end surface of the fifth inner side wall is coplanar with the end surface of the fifth channel layer.

4. The semiconductor structure of claim 1, wherein a material of the conductive layer comprises a metal; the metal comprises aluminum.

5. The semiconductor structure of claim 1, wherein the gate structure on the first region and the gate structure on the second region are separately formed with a gate dielectric layer between the gate structure on the first region and the gate structure on the second region.

6. The semiconductor structure of claim 1, wherein the gate structure over the first region and the gate structure over the second region are formed simultaneously.

7. The semiconductor structure of claim 1, further comprising: the source-drain doped layer positioned on the first region is internally provided with first source-drain ions; and second source drain ions are arranged in the source drain doped layer on the second region, and the electrical types of the first source drain ions and the second source drain ions are different.

8. The semiconductor structure of claim 1, wherein a material of the first channel layer, the second channel layer, and the third channel layer comprises silicon.

9. A method of forming a semiconductor structure, comprising:

providing a substrate comprising adjacent first and second regions, the devices formed on the first and second regions being the same or different;

forming a first channel layer, a second channel layer and a third channel layer on the first region and the second region respectively, wherein the first channel layer, the second channel layer and the third channel layer are stacked in sequence along the normal direction of the surface of the substrate;

forming a first inner side wall, a second inner side wall and a third inner side wall, wherein the first inner side wall is located between the first channel layer and the substrate, the first inner side wall is located on the substrate and supports two ends of the first channel layer, the end surface of the first inner side wall is coplanar with the end surface of the first channel layer, the second inner side wall is located between the first channel layer and the second channel layer, the second inner side wall is located on the first channel layer and supports two ends of the second channel layer, the end surface of the second inner side wall is coplanar with the end surface of the second channel layer, the third inner side wall is located between the second channel layer and the third channel layer, the third inner side wall is located on the second channel layer and supports two ends of the third channel layer, and the end surface of the third inner side wall is coplanar with the third end surface;

the source-drain doping layers are arranged on two sides of the stacked first channel layer, the second channel layer and the third channel layer and are connected with the end parts of the first channel layer, the second channel layer, the third channel layer, the first inner side wall, the second inner side wall and the third inner side wall;

forming a dielectric layer and a gate structure on the substrate, wherein the gate structure surrounds the first channel layer, the second channel layer and the third channel layer along an extending direction perpendicular to the first channel layer, the second channel layer and the third channel layer, the gate structure stretches across the first region and the second region, the dielectric layer covers the side wall of the gate structure, and the top surface of the dielectric layer is flush with the top surface of the gate structure;

etching back the grid structure to enable the top surface of the dielectric layer to be higher than the top surface of the grid structure, forming a conductive opening in the dielectric layer, and enabling the conductive opening to be exposed out of the top surface of the grid structure;

and forming a conductive layer in the conductive opening, wherein the conductive layer is connected with the gate structures on the first region and the second region.

10. The method of forming a semiconductor structure of claim 9, further comprising, prior to forming the gate structure and the dielectric layer: forming a dummy gate structure on the substrate, the dummy gate structure crossing the first, second, and third channel layers in a direction perpendicular to an extending direction of the first, second, and third channel layers, and the gate structure crossing the first and second regions; the dielectric layer covers the side wall of the pseudo gate structure.

11. The method of forming a semiconductor structure of claim 10, wherein the gate structure over the first region and the gate structure over the second region are formed separately with a gate dielectric layer between the gate structure over the first region and the gate structure over the second region.

12. The method of forming a semiconductor structure of claim 11, wherein the method of forming a gate structure comprises: forming a first patterning layer on the dielectric layer, wherein part of the pseudo gate structure is exposed out of the first patterning layer; etching the pseudo gate structure by taking the first patterning layer as a mask, and forming a first gate opening in the dielectric layer, wherein the first gate opening is positioned in the first region; forming the gate structure in the first gate opening on the first region, wherein the gate structure comprises a gate dielectric layer on the side wall and the bottom surface of the first gate opening and a gate layer on the gate dielectric layer; after the grid electrode structure is formed on the first area, removing the first patterning layer, and forming a second patterning layer on the dielectric layer, wherein the second patterning layer exposes another part of the pseudo grid electrode structure; etching the pseudo gate structure by taking the second patterning layer as a mask, and forming a second gate opening in the dielectric layer, wherein the second gate opening is positioned in the second region; and forming the grid structure in the second grid opening on the second area, wherein the grid structure comprises a grid dielectric layer positioned on the side wall and the bottom surface of the second grid opening and a grid layer positioned on the grid dielectric layer.

13. The method of forming a semiconductor structure of claim 9, wherein the gate structure over the first region and the gate structure over the second region are formed simultaneously.

14. The method of forming a semiconductor structure of claim 9, wherein forming a conductive layer within the conductive opening comprises: forming a conductive material layer in the conductive opening and on the top surface of the dielectric layer; and carrying out planarization treatment on the conductive material layer until the top surface of the dielectric layer is exposed, so as to form the conductive layer.

15. The method of forming a semiconductor structure of claim 9, wherein a material of the conductive layer comprises a metal; the metal comprises aluminum.

16. The method for forming a semiconductor structure according to claim 9, wherein first source drain ions are provided in the source drain doped layer located on the first region; and second source-drain ions are arranged in the source-drain doped layer on the second region, and the electrical types of the first source-drain ions and the second source-drain ions are different.

17. The method for forming a semiconductor structure according to claim 16, wherein the first source-drain ions include N-type ions or P-type ions; the second source-drain ions comprise P-type ions or N-type ions.

18. The method of forming a semiconductor structure of claim 9, wherein the material of the first, second, and third channel layers comprises silicon.