WO2013088520A1 - Semiconductor device manufacturing method, and semiconductor device - Google Patents

Semiconductor device manufacturing method, and semiconductor device Download PDF

Info

Publication number
WO2013088520A1
WO2013088520A1 PCT/JP2011/078828 JP2011078828W WO2013088520A1 WO 2013088520 A1 WO2013088520 A1 WO 2013088520A1 JP 2011078828 W JP2011078828 W JP 2011078828W WO 2013088520 A1 WO2013088520 A1 WO 2013088520A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon layer
insulating film
type diffusion
sidewall
gate
Prior art date
Application number
PCT/JP2011/078828
Other languages
French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to KR1020137015260A priority Critical patent/KR20130093149A/en
Priority to JP2013527212A priority patent/JP5643900B2/en
Priority to CN2011800599173A priority patent/CN103262234A/en
Priority to PCT/JP2011/078828 priority patent/WO2013088520A1/en
Priority to TW101144278A priority patent/TW201324627A/en
Publication of WO2013088520A1 publication Critical patent/WO2013088520A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • depletion can be suppressed and resistance of the gate electrode can be reduced by using metal instead of polysilicon for the gate electrode.
  • the post-process after forming the metal gate must always be a manufacturing process that takes into account metal contamination by the metal gate.
  • a silicon pillar having a nitride hard mask formed in a columnar shape is formed, a diffusion layer under the silicon pillar is formed, a gate material is deposited, and then the gate material is planarized and etched.
  • the insulating film sidewall is formed on the sidewalls of the silicon pillar and the nitride film hard mask.
  • a resist pattern for gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the silicon pillar (see, for example, Patent Document 4).
  • CMOS Complementary Metal Oxide Semiconductor
  • NMOS Negative Channel Metal Oxide Semiconductor
  • PMOS Platinum Channel Metal Oxide Semiconductor
  • a diffusion layer is formed on the upper and lower parts of the silicon pillar, and a gate material is deposited. Thereafter, the gate material is flattened and etched back to form an insulating film sidewall on the side wall of the silicon pillar, and then the gate material is etched to form a floating gate, and then the insulating film sidewall is removed (for example, see Patent Document 5).
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A JP 2006-310651 A
  • an object of the present invention is to provide a method for manufacturing a semiconductor device (SGT) in which the number of steps is small and the upper part of the silicon pillar is protected during etching of the gate, and a semiconductor device (SGT structure).
  • SGT semiconductor device
  • a method for manufacturing a semiconductor device includes: Forming a planar silicon layer on a silicon substrate, and forming a first columnar silicon layer and a second columnar silicon layer on the planar silicon layer; After the first step, a gate insulating film is formed around the first and second columnar silicon layers, a metal film and polysilicon are deposited around the gate insulating film and planarized, Etching is performed to expose the upper portions of the first and second columnar silicon layers, and a first insulating film sidewall is formed on the upper sidewall of the first columnar silicon layer.
  • a second insulating film side wall on the upper side wall of the silicon layer Forming a first gate electrode and a second gate electrode having a laminated structure of a metal film and polysilicon around the gate insulating film; A second step of forming a gate wiring connected to the first gate electrode and the second gate electrode; After the second step, a first n-type diffusion layer is formed on the first columnar silicon layer, and a second n-type diffusion layer is formed on the lower portion of the first columnar silicon layer and the upper portion of the planar silicon layer.
  • n-type diffusion layer is formed, a first p-type diffusion layer is formed on the second columnar silicon layer, and a second layer is formed on the lower portion of the second columnar silicon layer and the upper portion of the planar silicon layer.
  • a third step of forming a p-type diffusion layer After the third step, a third insulating film sidewall is formed on the first and second insulating film sidewalls, the first and second gate electrodes, and the side walls of the gate wiring. 4 steps, After the fourth step, a fifth step of forming silicide on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and the gate wiring. And having It is characterized by that.
  • a first resist for forming the first and second columnar silicon layers is formed on the silicon substrate, the silicon substrate is etched, and the first and second columnar silicon layers are formed. And removing the first resist, forming a second resist for forming the planar silicon layer, etching the silicon substrate, forming the planar silicon layer, and forming the second resist. Remove, It is preferable.
  • the gate insulating film is formed around the first and second columnar silicon layers, Forming a metal film around the gate insulating film; depositing and planarizing polysilicon; etching the polysilicon; exposing the metal film; etching the polysilicon; and Exposing the top of the columnar silicon layer, Etching the metal film, depositing a second oxide film and a first nitride film, and etching the first nitride film into a sidewall shape to form a nitride film sidewall; The second oxide film and the nitride film sidewall serve as the first and second insulating film sidewalls,
  • a third resist is formed so as to cover upper portions of the first and second columnar
  • a fourth resist for forming the first n-type diffusion layer and the second n-type diffusion layer is formed, arsenic is implanted, and the first and second n-type diffusion layers are formed.
  • a heat treatment is performed, The third oxide film is removed, the second oxide film and the gate insulating film are etched, and the second oxide film is etched to surround the first and second columnar silicon layers.
  • the oxide film sidewall and the nitride film sidewall serve as the first insulating film sidewall, and the oxide film sidewall and the nitride film sidewall serve as the second insulating film sidewall, Forming a fifth resist for forming the first p-type diffusion layer and the second p-type diffusion layer; implanting boron; forming the first and second p-type diffusion layers; Removing the fifth resist, depositing, and performing a heat treatment; It is preferable.
  • a second nitride film is further deposited, and the second nitride film is etched into a sidewall shape to form a nitride film sidewall serving as a third insulating film sidewall. It is preferable.
  • a semiconductor device is A planar silicon layer formed on a silicon substrate; First and second columnar silicon layers formed on the planar silicon layer; A first gate insulating film formed around the first columnar silicon layer; A first gate electrode having a laminated structure of a metal film and polysilicon formed around the first gate insulating film; A second gate insulating film formed around the second columnar silicon layer; A second gate electrode having a laminated structure of a metal film and polysilicon formed around the second gate insulating film; A gate wiring connected to the first and second gate electrodes; A first n-type diffusion layer formed on top of the first columnar silicon layer; A second n-type diffusion layer formed in a lower portion of the first columnar silicon layer and an upper portion of the planar silicon layer; A first p-type diffusion layer formed on top of the second columnar silicon layer; A second p-type diffusion layer formed in a lower portion of the second columnar silicon layer and an upper portion of the planar silicon layer; A first insulating film sidewall formed on
  • a method for manufacturing a semiconductor device (SGT) and a semiconductor device (SGT structure) in which the number of steps is small and the upper part of the silicon pillar is protected during gate etching.
  • the silicon pillar lower diffusion layer and the upper diffusion layer are formed simultaneously, the number of steps can be reduced.
  • a third resist is formed so as to cover the upper part of the first columnar silicon layer and the upper part of the second columnar silicon layer. Since the upper portions of the first and second columnar silicon layers are covered with the third resist, the gate insulating film is etched during the etching and the columnar silicon layer is prevented from being etched.
  • the first gate electrode has an upper portion covered with the first insulating film sidewall and a side wall covered with the third insulating film sidewall.
  • the side wall of the first insulating film side wall is covered with the third insulating film side wall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact can be prevented from being short-circuited.
  • the second gate electrode is covered with the second insulating film side wall at the top and the side wall is covered with the third insulating film side wall.
  • the side wall of the second insulating film sidewall is covered with the third insulating film sidewall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode, when the contact is displaced to the second gate electrode side, The contact is prevented from being short-circuited.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • first resists 102 and 103 for forming a first columnar silicon layer 105 and a second columnar silicon layer 104 are formed on a silicon substrate 101.
  • the silicon substrate 101 is etched to form a first columnar silicon layer 105 and a second columnar silicon layer 104.
  • the first resists 102 and 103 are removed.
  • a second resist 106 for forming the planar silicon layer 107 is formed.
  • the silicon substrate 101 is etched to form a planar silicon layer 107.
  • the second resist 106 is removed.
  • the first oxide film 108 is deposited and the surface thereof is flattened.
  • the first oxide film 108 is etched and left around the planar silicon layer 107.
  • a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104, and around the gate insulating film 109.
  • the metal film 110 and the polysilicon 111 are deposited and the surface thereof is planarized and etched to expose the first columnar silicon layer 105 and the upper portion of the second columnar silicon layer 104.
  • a first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105
  • a second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104, and gate insulation is performed.
  • a first gate electrode 117b and a second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 are formed around the film. Then, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a is shown.
  • a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104.
  • a material of the gate insulating film 109 here, an oxide film, a laminated structure of an oxide film and a nitride film, a nitride film, or a high dielectric film can be used.
  • a metal film 110 is formed around the gate insulating film 109.
  • a metal material that can be used for a gate electrode such as titanium, titanium nitride, tantalum, or tantalum nitride can be used for the metal film 110.
  • polysilicon 111 is deposited and the surface thereof is flattened.
  • the polysilicon 111 is etched.
  • the polysilicon 111 is etched to expose the metal film 110.
  • the polysilicon 111 is etched to expose the upper portions of the first columnar silicon layer 105 and the second columnar silicon layer.
  • the metal film 110 is etched.
  • wet etching it is preferable to use wet etching.
  • a second oxide film 112 and a first nitride film 113 are deposited.
  • the first nitride film 113 is etched to remain on the side walls of the two columnar bodies to form nitride film side walls 114 and 115.
  • the first insulating film sidewall 201 is formed from the first oxide film 112 and the nitride film sidewall 115.
  • a second insulating film sidewall 200 is formed from the first oxide film 112 and the nitride film sidewall 114.
  • the upper part of the first columnar silicon layer 105 and the second gate electrode 117c are formed.
  • a third resist 116 is formed so as to cover the upper part of the columnar silicon layer 104.
  • the second oxide film 112 is etched.
  • the polysilicon 111 is etched, the metal film 110 is etched, and a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed.
  • the third resist 116 is removed.
  • wet etching is performed to remove the residue of the metal film 110. This treatment can be omitted when there is no residue of the metal film 110.
  • the gate insulating film 109 is formed around the second step, that is, the first columnar silicon layer 105 and the second columnar silicon layer 104, and the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. And the surface of the first columnar silicon layer 105 and the second columnar silicon layer 104 are exposed by performing etching. Then, the first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105, and the second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104.
  • a first gate electrode 117 b and a second gate electrode 117 a having a stacked structure of the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. Thereafter, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a was shown.
  • a third step that is, a first n-type diffusion layer 119 is formed on the first columnar silicon layer 105, and a lower portion of the first columnar silicon layer 105 and an upper portion of the planar silicon layer 107 are formed. Then, the second n-type diffusion layer 120 is formed. Then, a first p-type diffusion layer 125 is formed on the second columnar silicon layer 104, and a second p-type diffusion layer is formed on the lower portion of the second columnar silicon layer 104 and the upper portion of the planar silicon layer 107. A third step of forming 126 is shown.
  • a fourth resist 118 for forming the first n-type diffusion layer 119 and the second n-type diffusion layer 120 is formed.
  • arsenic is implanted to form a first n-type diffusion layer 119 and a second n-type diffusion layer 120.
  • phosphorus can be implanted instead of arsenic.
  • the fourth resist 118 is removed, and a third oxide film 121 is deposited.
  • heat treatment is performed.
  • the third oxide film 121 is removed, and the second oxide film 112 and the gate insulating film 109 are etched.
  • the second oxide film 112 is etched and remains around the first columnar silicon layer 105 to form the oxide film sidewall 123, and also remains around the second columnar silicon layer 104, and the oxide film sidewall 122. It becomes. Therefore, the oxide film side wall 123 and the nitride film side wall 115 become the first insulating film side wall 201, and the oxide film side wall 122 and the nitride film side wall 114 become the second insulating film side wall 200. .
  • a fifth resist 124 for forming the first p-type diffusion layer 125 and the second p-type diffusion layer 126 is formed.
  • boron is implanted to form the first p-type diffusion layer 125 and the second p-type diffusion layer 126.
  • the fifth resist 124 is removed.
  • a second nitride film 127 is deposited.
  • heat treatment is performed.
  • the first n-type diffusion layer 119 is formed on the upper portion of the first columnar silicon layer 105, and the lower portion of the first columnar silicon layer 105 and the upper portion of the planar silicon layer 107 are formed.
  • a second n-type diffusion layer 120 is formed.
  • a first p-type diffusion layer 125 is formed above the second columnar silicon layer 104, and a second p-type diffusion layer 126 is formed below the second columnar silicon layer 104 and above the planar silicon layer 107.
  • a third step of forming was shown.
  • the present invention is not limited to this.
  • a sidewall is formed on the sidewall of the columnar silicon layer, and then the first n-type diffusion layer and the second n-type diffusion layer are formed.
  • a first p-type diffusion layer and a second p-type diffusion layer may be formed, and then a gate electrode may be formed.
  • a third insulating film sidewall 201, a second insulating film sidewall 202, a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed on the sidewalls of the third insulating film sidewall 201, the second insulating film sidewall 202, The 4th process of forming the insulating film side wall 202 is shown.
  • the second nitride film 127 is etched and left in a sidewall shape to form nitride film sidewalls 128, 129, and 130.
  • the nitride film sidewall 128 becomes the third insulating film sidewall 202.
  • the upper part of the first gate electrode 117b is covered with the first insulating film sidewall 201, and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact are prevented from being short-circuited.
  • the upper part of the second gate electrode 117 a is covered with the second insulating film sidewall 200 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode side, the second A short circuit between the gate electrode and the contact is prevented.
  • the third insulating film sidewall 201, the second insulating film sidewall 202, the first gate electrode 117b, the second gate electrode 117a, and the side wall of the gate wiring 117c are third insulating.
  • a fourth step of forming the film sidewall 202 has been shown.
  • a metal such as nickel or cobalt is deposited and heat treatment is performed to remove unreacted metal.
  • a metal such as nickel or cobalt is deposited and heat treatment is performed to remove unreacted metal.
  • silicides 133, 134, 135, 136, 132, 131, and 137 are formed.
  • the second n-type diffusion layer 120 and the second p-type diffusion layer 126 are connected by the silicides 134 and 135.
  • the output terminal of the inverter is not formed under the silicon pillar, it is possible to omit connecting the second n-type diffusion layer 120 and the second p-type diffusion layer 126 with silicide.
  • a fifth step of forming silicide on 117c is shown.
  • a third nitride film 138 is deposited, an interlayer insulating film 139 is further deposited, and the surface thereof is flattened.
  • a sixth resist 140 for forming contacts on the first columnar silicon layer 105 and the second columnar silicon layer 104 is formed.
  • the interlayer insulating film 139 is etched to form contact holes 141 and 142.
  • the sixth resist 140 is removed.
  • a seventh resist 143 for forming a contact is formed on the gate wiring 117c and the planar silicon layer 107.
  • the interlayer insulating film 139 is etched to form contact holes 144 and 145.
  • the seventh resist 143 is removed.
  • the third nitride film 138 is etched.
  • metal is deposited to form contacts 146, 147, 148, and 149.
  • a metal 150 for metal wiring is deposited.
  • eighth resists 151, 152, 153, 154 are formed in order to form metal wiring.
  • the metal 150 is etched to form metal wirings 155, 156, 157, 158.
  • the eighth resists 151, 152, 153, 154 are removed.
  • the manufacturing method of SGT in which the number of steps is small and the upper part of the silicon pillar is protected during the etching of the gate is shown.
  • FIG. A structure of a semiconductor device obtained by the manufacturing method is shown in FIG. As shown in FIG. A planar silicon layer 107 formed on the silicon substrate 101; A first columnar silicon layer 105 formed on the planar silicon layer 107; A second columnar silicon layer 104 formed on the planar silicon layer 107; A gate insulating film 109 formed around the first columnar silicon layer 105; A first gate electrode 117b having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109; A gate insulating film 109 formed around the second columnar silicon layer 104; A second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109; A gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a; A first n-type diffusion layer 119 formed on the first columnar silicon layer 105; A second n-type diffusion layer 120 formed below the first columnar silicon layer 105 and above the planar silicon
  • a membrane sidewall 202 Formed on the first n-type diffusion layer 119, the second n-type diffusion layer 120, the first p-type diffusion layer 125, the second p-type diffusion layer 126, and the gate wiring 117c. Silicided 133, 134, 135, 136, 132, 131, 137, Have
  • the upper portion of the first gate electrode 117 b is covered with the first insulating film sidewall 201 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact 140 formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode 117b side, the first gate electrode 117b and the contact 140 are prevented from being short-circuited. . Similarly, the second gate electrode 117 a is covered with the second insulating film sidewall 200 at the top and with the third insulating film sidewall 202 at the sidewall.
  • the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode 117a side, the second It is possible to prevent a short circuit between the gate electrode 117a and the contact.
  • Second nitride film 128. Nitride film sidewall 129. Nitride film sidewall 130. Nitride film sidewall 131.
  • Silicide 132. Silicide 133.
  • Silicide 134. Silicide 135.
  • Silicide 136. Silicide 137.
  • Silicide 138. Third nitride film 139. Interlayer insulating film 140. Sixth resist 141. Contact hole 142. Contact hole 143. Seventh resist 144. Contact hole 145. Contact hole 146. Contact 147. Contact 148. Contact 149. Contact 150. Metal 151. Eighth resist 152. Eighth resist 153. Eighth resist 154. Eighth resist 155. Metal wiring 156. Metal wiring 157. Metal wiring 158. Metal wiring 200. Second insulating film sidewall 201. First insulating film sidewall 202. Third insulating film sidewall

Abstract

This semiconductor device manufacturing method has: a step wherein a planar silicon layer (107) and first and second columnar silicon layers (104, 105) are formed on a silicon substrate (101); a step wherein a gate insulating film (109) is formed, a metal film (110) and polysilicon (111) are deposited and planarized on the periphery of the gate insulating film, and upper portions of the first and second columnar silicon layers are exposed by etching the metal film and the polysilicon, then, first and second insulating film side walls (201, 200) are formed, and first and second gate electrodes (117b, 117a), and gate wiring (117c) are formed; a step wherein n-type diffusion layers are formed above and below the first columnar silicon layer, and p-type diffusion layers are formed above and below the second columnar silicon layer; a step wherein a third insulating film side wall (202) is formed on the first and second insulating film side walls, first and second gate electrodes, and the side walls of the gate wiring; and a step wherein silicide (133) is formed.

Description

半導体装置の製造方法、及び、半導体装置Semiconductor device manufacturing method and semiconductor device
　本発明は半導体装置の製造方法、及び、半導体装置に関する。 The present invention relates to a semiconductor device manufacturing method and a semiconductor device.
　半導体集積回路、特にＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。このようなＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。このような問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲート電極が柱状半導体層を取り囲む構造のSurrounding Gate Transistor（以下、「ＳＧＴ」という。）が提案されている（例えば、特許文献１、特許文献２、特許文献３を参照）。 Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).
　この技術によれば、ゲート電極に、ポリシリコンではなくメタルを用いることにより、空乏化を抑制できるとともに、ゲート電極を低抵抗化することができる。
　しかしながら、メタルゲートを形成した後工程は、常にメタルゲートによるメタル汚染を考慮した製造工程にする必要がある。 According to this technique, depletion can be suppressed and resistance of the gate electrode can be reduced by using metal instead of polysilicon for the gate electrode.
However, the post-process after forming the metal gate must always be a manufacturing process that takes into account metal contamination by the metal gate.
　従来のＳＧＴの製造方法では、窒化膜ハードマスクが柱状に形成されたシリコン柱を形成し、シリコン柱下部の拡散層を形成した後、ゲート材料を堆積し、その後にゲート材料を平坦化、エッチバックをし、シリコン柱と窒化膜ハードマスクの側壁に絶縁膜サイドウォールを形成する。その後、ゲート配線のためのレジストパターンを形成し、ゲート材料をエッチングした後、窒化膜ハードマスクを除去し、シリコン柱上部に拡散層を形成している（例えば、特許文献４を参照）。 In the conventional SGT manufacturing method, a silicon pillar having a nitride hard mask formed in a columnar shape is formed, a diffusion layer under the silicon pillar is formed, a gate material is deposited, and then the gate material is planarized and etched. The insulating film sidewall is formed on the sidewalls of the silicon pillar and the nitride film hard mask. Thereafter, a resist pattern for gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the silicon pillar (see, for example, Patent Document 4).
　このような方法では、シリコン柱下部の拡散層を形成した後、ゲート電極を形成し、シリコン柱上部に拡散層を形成することから、ボロンは拡散速度が速く、砒素は拡散速度が遅いために、いわゆるＣＭＯＳ（Complementary Metal Oxide Semiconductor)　ＳＧＴとしたとき、ＮＭＯＳ(Negative channel Metal Oxide Semiconductor)，ＰＭＯＳ(Positive channel Metal Oxide Semiconductor)それぞれに対して最適な熱処理を行うことが困難となる。
　従って、シリコン柱下部、上部を別々に形成し、窒化膜ハードマスクを除去することになるため、工程数が増加してしまう。 In such a method, after forming the diffusion layer under the silicon pillar, the gate electrode is formed, and the diffusion layer is formed above the silicon pillar. Therefore, boron has a high diffusion rate and arsenic has a low diffusion rate. When a so-called CMOS (Complementary Metal Oxide Semiconductor) SGT is used, it is difficult to perform an optimum heat treatment on each of an NMOS (Negative Channel Metal Oxide Semiconductor) and a PMOS (Positive Channel Metal Oxide Semiconductor).
Therefore, the lower and upper portions of the silicon pillar are separately formed and the nitride film hard mask is removed, which increases the number of steps.
　また、従来のＳＧＴの製造方法では、シリコン柱を形成後、シリコン柱上部、下部に拡散層を形成し、ゲート材料を堆積する。その後、ゲート材料を平坦化、エッチバックをし、シリコン柱の側壁に絶縁膜サイドウォールを形成した後、ゲート材料をエッチングし、フローティングゲートを形成した後、絶縁膜サイドウォールを除去している（例えば、特許文献５を参照）。 In the conventional SGT manufacturing method, after forming the silicon pillar, a diffusion layer is formed on the upper and lower parts of the silicon pillar, and a gate material is deposited. Thereafter, the gate material is flattened and etched back to form an insulating film sidewall on the side wall of the silicon pillar, and then the gate material is etched to form a floating gate, and then the insulating film sidewall is removed ( For example, see Patent Document 5).
　このような方法では、ゲート材料をエッチングし、フローティングゲートを形成する際に、シリコン柱上部にはゲート絶縁膜だけが存在するので、エッチング中にゲート絶縁膜がエッチングされ、シリコン柱がエッチングされる可能性がある。
　また、フローティングゲートを形成後、絶縁膜サイドウォールを除去するため、工程数が増加してしまう。 In such a method, when the gate material is etched to form the floating gate, only the gate insulating film exists on the silicon pillar, so the gate insulating film is etched during the etching, and the silicon pillar is etched. there is a possibility.
Further, since the insulating film sidewall is removed after forming the floating gate, the number of processes increases.
特開平２－７１５５６号公報JP-A-2-71556 特開平２－１８８９６６号公報Japanese Patent Laid-Open No. 2-188966 特開平３－１４５７６１号公報Japanese Patent Laid-Open No. 3-145761 特開２００９－１８２３１７号公報JP 2009-182317 A 特開２００６－３１０６５１号公報JP 2006-310651 A
　そこで、本発明は、工程数が少なく、ゲートのエッチング中にシリコン柱上部が保護される半導体装置（ＳＧＴ）の製造方法、及び、半導体装置（ＳＧＴの構造）を提供することを目的とする。 Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device (SGT) in which the number of steps is small and the upper part of the silicon pillar is protected during etching of the gate, and a semiconductor device (SGT structure).
　本発明の第１の観点に係る半導体装置の製造方法は、
　シリコン基板上に平面状シリコン層を形成し、前記平面状シリコン層上に第１の柱状シリコン層と第２の柱状シリコン層とを形成する第１の工程と、
　前記第１の工程の後、前記第１及び前記第２の柱状シリコン層の周囲にゲート絶縁膜を形成し、前記ゲート絶縁膜の周囲に金属膜及びポリシリコンを堆積するとともに平坦化をし、エッチングを行うことにより前記第１及び前記第２の柱状シリコン層の上部とを露出し、前記第１の柱状シリコン層の上部側壁に第１の絶縁膜サイドウォールを形成し、前記第２の柱状シリコン層の上部側壁に第２の絶縁膜サイドウォールを形成し、前記ゲート絶縁膜の周囲に金属膜とポリシリコンの積層構造からなる第１のゲート電極と第２のゲート電極とを形成し、前記第１のゲート電極と前記第２のゲート電極とに接続されたゲート配線を形成する第２の工程と、
　前記第２の工程の後、前記第１の柱状シリコン層の上部に第１のｎ型拡散層を形成し、前記第１の柱状シリコン層の下部と前記平面状シリコン層の上部に第２のｎ型拡散層を形成し、前記第２の柱状シリコン層の上部に第１のｐ型拡散層を形成し、前記第２の柱状シリコン層の下部と前記平面状シリコン層の上部に第２のｐ型拡散層を形成する第３の工程と、
　前記第３の工程の後、前記第１及び前記第２の絶縁膜サイドウォールと前記第１及び前記第２のゲート電極と前記ゲート配線の側壁とに第３の絶縁膜サイドウォールを形成する第４の工程と、
　前記第４の工程の後、前記第１及び前記第２のｎ型拡散層上と前記第１及び前記第２のｐ型拡散層上と前記ゲート配線上とにシリサイドを形成する第５の工程と、を有する、
　ことを特徴とする。 A method for manufacturing a semiconductor device according to a first aspect of the present invention includes:
Forming a planar silicon layer on a silicon substrate, and forming a first columnar silicon layer and a second columnar silicon layer on the planar silicon layer;
After the first step, a gate insulating film is formed around the first and second columnar silicon layers, a metal film and polysilicon are deposited around the gate insulating film and planarized, Etching is performed to expose the upper portions of the first and second columnar silicon layers, and a first insulating film sidewall is formed on the upper sidewall of the first columnar silicon layer. Forming a second insulating film side wall on the upper side wall of the silicon layer, forming a first gate electrode and a second gate electrode having a laminated structure of a metal film and polysilicon around the gate insulating film; A second step of forming a gate wiring connected to the first gate electrode and the second gate electrode;
After the second step, a first n-type diffusion layer is formed on the first columnar silicon layer, and a second n-type diffusion layer is formed on the lower portion of the first columnar silicon layer and the upper portion of the planar silicon layer. An n-type diffusion layer is formed, a first p-type diffusion layer is formed on the second columnar silicon layer, and a second layer is formed on the lower portion of the second columnar silicon layer and the upper portion of the planar silicon layer. a third step of forming a p-type diffusion layer;
After the third step, a third insulating film sidewall is formed on the first and second insulating film sidewalls, the first and second gate electrodes, and the side walls of the gate wiring. 4 steps,
After the fourth step, a fifth step of forming silicide on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and the gate wiring. And having
It is characterized by that.
　前記シリコン基板上に前記第１及び前記第２の柱状シリコン層を形成するための第１のレジストを形成し、前記シリコン基板をエッチングし、前記第１及び前記第２の柱状シリコン層とを形成し、前記第１のレジストを除去し、前記平面状シリコン層を形成するための第２のレジストを形成し、前記シリコン基板をエッチングし、前記平面状シリコン層を形成し、前記第２のレジストを除去する、
　ことが好ましい。 A first resist for forming the first and second columnar silicon layers is formed on the silicon substrate, the silicon substrate is etched, and the first and second columnar silicon layers are formed. And removing the first resist, forming a second resist for forming the planar silicon layer, etching the silicon substrate, forming the planar silicon layer, and forming the second resist. Remove,
It is preferable.
　前記シリコン基板上に形成された前記平面状シリコン層と、前記平面状シリコン層上に形成された前記第１の柱状シリコン層と、前記平面状シリコン層上に形成された第２の柱状シリコン層と、前記平面状シリコン層の周囲に第１の絶縁膜が形成された構造において、前記第１及び前記第２の柱状シリコン層の周囲に前記ゲート絶縁膜が形成され、
　前記ゲート絶縁膜の周囲に金属膜を形成し、ポリシリコンを堆積するとともに平坦化し、前記ポリシリコンをエッチングし、前記金属膜を露出させ、前記ポリシリコンをエッチングし、前記第１及び前記第２の柱状シリコン層の上部とを露出し、
　前記金属膜をエッチングし、第２の酸化膜と第１の窒化膜とを堆積し、前記第１の窒化膜をサイドウォール状にエッチングすることで、窒化膜サイドウォールを形成し、
　前記第２の酸化膜と前記窒化膜サイドウォールとが前記第１及び前記第２の絶縁膜サイドウォールとなり、
　前記第１及び前記第２のゲート電極と前記ゲート配線とを形成するために、前記第１及び前記第２の柱状シリコン層の上部を覆うように第３のレジストを形成し、
　前記第２の酸化膜をエッチングし、前記ポリシリコンをエッチングし、前記金属膜をエッチングし、前記第１及び前記第２のゲート電極と前記ゲート配線とを形成した後、前記第３のレジストを除去する、
　ことが好ましい。 The planar silicon layer formed on the silicon substrate, the first columnar silicon layer formed on the planar silicon layer, and the second columnar silicon layer formed on the planar silicon layer And in the structure in which the first insulating film is formed around the planar silicon layer, the gate insulating film is formed around the first and second columnar silicon layers,
Forming a metal film around the gate insulating film; depositing and planarizing polysilicon; etching the polysilicon; exposing the metal film; etching the polysilicon; and Exposing the top of the columnar silicon layer,
Etching the metal film, depositing a second oxide film and a first nitride film, and etching the first nitride film into a sidewall shape to form a nitride film sidewall;
The second oxide film and the nitride film sidewall serve as the first and second insulating film sidewalls,
In order to form the first and second gate electrodes and the gate wiring, a third resist is formed so as to cover upper portions of the first and second columnar silicon layers,
The second oxide film is etched, the polysilicon is etched, the metal film is etched, the first and second gate electrodes and the gate wiring are formed, and then the third resist is formed. Remove,
It is preferable.
　第１のｎ型拡散層と第２のｎ型拡散層とを形成するための第４のレジストを形成し、砒素を注入し、前記第１及び前記第２のｎ型拡散層とを形成し、前記第４のレジストを除去し、第３の酸化膜を堆積した後、熱処理を行い、
　前記第３の酸化膜を除去し、前記第２の酸化膜と前記ゲート絶縁膜とをエッチングし、前記第２の酸化膜は、エッチングされ、前記第１及び前記第２の柱状シリコン層の周囲に残存し酸化膜サイドウォールとなり、
　前記酸化膜サイドウォールと前記窒化膜サイドウォールとが前記第１の絶縁膜サイドウォールとなるとともに、前記酸化膜サイドウォールと前記窒化膜サイドウォールとが前記第２の絶縁膜サイドウォールとなり、
　第１のｐ型拡散層と第２のｐ型拡散層とを形成するための第５のレジストを形成し、ボロンを注入し、前記第１及び前記第２のｐ型拡散層を形成し、前記第５のレジストを除去し、を堆積した後、熱処理を行う、
　ことが好ましい。 A fourth resist for forming the first n-type diffusion layer and the second n-type diffusion layer is formed, arsenic is implanted, and the first and second n-type diffusion layers are formed. , After removing the fourth resist and depositing a third oxide film, a heat treatment is performed,
The third oxide film is removed, the second oxide film and the gate insulating film are etched, and the second oxide film is etched to surround the first and second columnar silicon layers. Remain in the oxide film sidewall,
The oxide film sidewall and the nitride film sidewall serve as the first insulating film sidewall, and the oxide film sidewall and the nitride film sidewall serve as the second insulating film sidewall,
Forming a fifth resist for forming the first p-type diffusion layer and the second p-type diffusion layer; implanting boron; forming the first and second p-type diffusion layers; Removing the fifth resist, depositing, and performing a heat treatment;
It is preferable.
　第２の窒化膜をさらに堆積し、前記第２の窒化膜をサイドウォール状にエッチングすることで、第３の絶縁膜サイドウォールとなる窒化膜サイドウォールを形成する、
　ことが好ましい。 A second nitride film is further deposited, and the second nitride film is etched into a sidewall shape to form a nitride film sidewall serving as a third insulating film sidewall.
It is preferable.
　また、本発明の第２の観点に係る半導体装置は、
　シリコン基板上に形成された平面状シリコン層と、
　前記平面状シリコン層上に形成された第１及び第２の柱状シリコン層と、
　前記第１の柱状シリコン層の周囲に形成された第１のゲート絶縁膜と、
　前記第１のゲート絶縁膜の周囲に形成された金属膜及びポリシリコンの積層構造からなる第１のゲート電極と、
　前記第２の柱状シリコン層の周囲に形成された第２のゲート絶縁膜と、
　前記第２のゲート絶縁膜の周囲に形成された金属膜及びポリシリコンの積層構造からなる第２のゲート電極と、
　前記第１及び前記第２のゲート電極に接続されたゲート配線と、
　前記第１の柱状シリコン層の上部に形成された第１のｎ型拡散層と、
　前記第１の柱状シリコン層の下部と前記平面状シリコン層の上部とに形成された第２のｎ型拡散層と、
　前記第２の柱状シリコン層の上部に形成された第１のｐ型拡散層と、
　前記第２の柱状シリコン層の下部と前記平面状シリコン層の上部とに形成された第２のｐ型拡散層と、
　前記第１の柱状シリコン層の上部側壁と前記第１のゲート電極上部とに形成された第１の絶縁膜サイドウォールと、
　前記第２の柱状シリコン層の上部側壁と前記第２のゲート電極上部とに形成された第２の絶縁膜サイドウォールと、
　前記第１及び前記第２の絶縁膜サイドウォールと前記第１及び前記第２のゲート電極と前記ゲート配線の側壁とに形成された第３の絶縁膜サイドウォールと、
　前記第１及び前記第２のｎ型拡散層上と前記第１及び前記第２のｐ型拡散層上と、ゲート配線上に形成されたシリサイドと、を有する、
　ことを特徴とする。 A semiconductor device according to the second aspect of the present invention is
A planar silicon layer formed on a silicon substrate;
First and second columnar silicon layers formed on the planar silicon layer;
A first gate insulating film formed around the first columnar silicon layer;
A first gate electrode having a laminated structure of a metal film and polysilicon formed around the first gate insulating film;
A second gate insulating film formed around the second columnar silicon layer;
A second gate electrode having a laminated structure of a metal film and polysilicon formed around the second gate insulating film;
A gate wiring connected to the first and second gate electrodes;
A first n-type diffusion layer formed on top of the first columnar silicon layer;
A second n-type diffusion layer formed in a lower portion of the first columnar silicon layer and an upper portion of the planar silicon layer;
A first p-type diffusion layer formed on top of the second columnar silicon layer;
A second p-type diffusion layer formed in a lower portion of the second columnar silicon layer and an upper portion of the planar silicon layer;
A first insulating film sidewall formed on an upper sidewall of the first columnar silicon layer and an upper portion of the first gate electrode;
A second insulating film sidewall formed on an upper sidewall of the second columnar silicon layer and an upper portion of the second gate electrode;
A third insulating film sidewall formed on the first and second insulating film sidewalls, the first and second gate electrodes, and a sidewall of the gate wiring;
A silicide formed on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and a gate wiring;
It is characterized by that.
　本発明によれば、工程数が少なく、ゲートのエッチング中にシリコン柱上部が保護される半導体装置（ＳＧＴ）の製造方法、及び、半導体装置（ＳＧＴの構造）を提供することができる。
　また、シリコン柱下部拡散層、上部拡散層を同時に形成するため、工程数を低減することができる。
　また、第１及び第２のゲート電極とゲート配線とを形成するために、第１の柱状シリコン層の上部と第２の柱状シリコン層の上部とを覆うように第３のレジストを形成するため、第１及び第２の柱状シリコン層の上部とが第３のレジストで覆われるので、エッチング中にゲート絶縁膜がエッチングされ、柱状シリコン層がエッチングされることが防止される。 According to the present invention, it is possible to provide a method for manufacturing a semiconductor device (SGT) and a semiconductor device (SGT structure) in which the number of steps is small and the upper part of the silicon pillar is protected during gate etching.
In addition, since the silicon pillar lower diffusion layer and the upper diffusion layer are formed simultaneously, the number of steps can be reduced.
Further, in order to form the first and second gate electrodes and the gate wiring, a third resist is formed so as to cover the upper part of the first columnar silicon layer and the upper part of the second columnar silicon layer. Since the upper portions of the first and second columnar silicon layers are covered with the third resist, the gate insulating film is etched during the etching and the columnar silicon layer is prevented from being etched.
　また、第１のゲート電極は、上部が第１の絶縁膜サイドウォールに覆われ、側壁が第３の絶縁膜サイドウォールに覆われている。第１の絶縁膜サイドウォールの側壁は第３の絶縁膜サイドウォールに覆われている。従って、平面状シリコン層上部の拡散層上に形成するコンタクトが、第１のゲート電極側に位置ずれしたとき、第１のゲート電極とコンタクトが短絡することを防止できる。
　これと同様に、第２のゲート電極は、上部が第２の絶縁膜サイドウォールで覆われ、側壁が第３の絶縁膜サイドウォールで覆われる。また、第２の絶縁膜サイドウォールの側壁は第３の絶縁膜サイドウォールで覆われる。従って、平面状シリコン層上部の拡散層上に形成するコンタクトが第２のゲート電極の近傍に形成されたとき、そのコンタクトが第２のゲート電極側に位置ずれしたとき、第２のゲート電極とコンタクトが短絡することが防止される。 The first gate electrode has an upper portion covered with the first insulating film sidewall and a side wall covered with the third insulating film sidewall. The side wall of the first insulating film side wall is covered with the third insulating film side wall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact can be prevented from being short-circuited.
Similarly, the second gate electrode is covered with the second insulating film side wall at the top and the side wall is covered with the third insulating film side wall. The side wall of the second insulating film sidewall is covered with the third insulating film sidewall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode, when the contact is displaced to the second gate electrode side, The contact is prevented from being short-circuited.
（ａ）は本発明の実施形態に係る半導体装置の平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view of the semiconductor device concerning the embodiment of the present invention. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. （ａ）は本実施形態に係る半導体装置の製造方法を示す平面図である。（ｂ）は（ａ）のＸ－Ｘ’線での断面図である。（ｃ）は（ａ）のＹ－Ｙ’線での断面図である。(A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
　以下、本発明の実施形態に係る、ＳＧＴの構造を有する半導体装置の製造工程を、図２～図４８を参照しながら説明する。 Hereinafter, a manufacturing process of a semiconductor device having an SGT structure according to an embodiment of the present invention will be described with reference to FIGS.
（第１の工程）
　以下に、シリコン基板１０１上に平面状シリコン層１０７と、平面状シリコン層１０７上とに、第１の柱状シリコン層１０５と第２の柱状シリコン層１０４と、を形成する第１の工程を示す。 (First step)
Hereinafter, a first step of forming the planar silicon layer 107 on the silicon substrate 101 and the first columnar silicon layer 105 and the second columnar silicon layer 104 on the planar silicon layer 107 is shown. .
　まず、図２に示すように、シリコン基板１０１上に第１の柱状シリコン層１０５と第２の柱状シリコン層１０４とを形成するための第１のレジスト１０２、１０３を形成する。 First, as shown in FIG. 2, first resists 102 and 103 for forming a first columnar silicon layer 105 and a second columnar silicon layer 104 are formed on a silicon substrate 101.
　次に、図３に示すように、シリコン基板１０１をエッチングし、第１の柱状シリコン層１０５と第２の柱状シリコン層１０４とを形成する。 Next, as shown in FIG. 3, the silicon substrate 101 is etched to form a first columnar silicon layer 105 and a second columnar silicon layer 104.
　続いて、図４に示すように、第１のレジスト１０２、１０３を除去する。 Subsequently, as shown in FIG. 4, the first resists 102 and 103 are removed.
　続いて、図５に示すように、平面状シリコン層１０７を形成するための第２のレジスト１０６を形成する。 Subsequently, as shown in FIG. 5, a second resist 106 for forming the planar silicon layer 107 is formed.
　続いて、図６に示すように、シリコン基板１０１をエッチングし、平面状シリコン層１０７を形成する。 Subsequently, as shown in FIG. 6, the silicon substrate 101 is etched to form a planar silicon layer 107.
　続いて、図７に示すように、第２のレジスト１０６を除去する。 Subsequently, as shown in FIG. 7, the second resist 106 is removed.
　以上により、シリコン基板１０１上に平面状シリコン層１０７と、平面状シリコン層１０７上とに、第１の柱状シリコン層１０５と第２の柱状シリコン層１０４とを形成する第１の工程が示された。 Thus, the first step of forming the planar silicon layer 107 on the silicon substrate 101 and the first columnar silicon layer 105 and the second columnar silicon layer 104 on the planar silicon layer 107 is shown. It was.
　次に、図８に示すように、第１の酸化膜１０８を堆積するとともにその表面を平坦化する。 Next, as shown in FIG. 8, the first oxide film 108 is deposited and the surface thereof is flattened.
　そして、図９に示すように、第１の酸化膜１０８をエッチングし、平面状シリコン層１０７の周囲に残存させる。 Then, as shown in FIG. 9, the first oxide film 108 is etched and left around the planar silicon layer 107.
（第２の工程）
　次に、第２の工程、即ち、図９に示すように、第１の柱状シリコン層１０５及び第２の柱状シリコン層１０４の周囲にゲート絶縁膜１０９を形成し、ゲート絶縁膜１０９の周囲に金属膜１１０とポリシリコン１１１とを堆積するとともにその表面を平坦化し、エッチングすることにより第１の柱状シリコン層１０５と第２の柱状シリコン層１０４の上部とを露出させる。そして、第１の柱状シリコン層１０５の上部側壁に第１の絶縁膜サイドウォール２０１を形成し、第２の柱状シリコン層１０４の上部側壁に第２の絶縁膜サイドウォール２００を形成し、ゲート絶縁膜の周囲に金属膜１１０及びポリシリコン１１１の積層構造からなる第１のゲート電極１１７ｂと第２のゲート電極１１７ａとを形成する。そして、第１のゲート電極１１７ｂと第２のゲート電極１１７ａとに接続されたゲート配線１１７ｃを形成する第２の工程を示す。 (Second step)
Next, in the second step, that is, as shown in FIG. 9, a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104, and around the gate insulating film 109. The metal film 110 and the polysilicon 111 are deposited and the surface thereof is planarized and etched to expose the first columnar silicon layer 105 and the upper portion of the second columnar silicon layer 104. Then, a first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105, a second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104, and gate insulation is performed. A first gate electrode 117b and a second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 are formed around the film. Then, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a is shown.
　まず、図１０に示すように、第１の柱状シリコン層１０５及び第２の柱状シリコン層１０４の周囲にゲート絶縁膜１０９を形成する。ここでのゲート絶縁膜１０９の材質としては、酸化膜、酸化膜及び窒化膜の積層構造、窒化膜、または、高誘電体膜が使用できる。 First, as shown in FIG. 10, a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104. As a material of the gate insulating film 109 here, an oxide film, a laminated structure of an oxide film and a nitride film, a nitride film, or a high dielectric film can be used.
　次に、図１１に示すように、ゲート絶縁膜１０９の周囲に金属膜１１０を形成する。
ここでの金属膜１１０には、チタン、窒化チタン、タンタル、窒化タンタルなどのゲート電極に使用しうる金属材料が使用できる。 Next, as illustrated in FIG. 11, a metal film 110 is formed around the gate insulating film 109.
Here, a metal material that can be used for a gate electrode such as titanium, titanium nitride, tantalum, or tantalum nitride can be used for the metal film 110.
　続いて、図１２に示すように、ポリシリコン１１１を堆積するとともにその表面を平坦化する。 Subsequently, as shown in FIG. 12, polysilicon 111 is deposited and the surface thereof is flattened.
　続いて、図１３に示すように、ポリシリコン１１１をエッチングする。 Subsequently, as shown in FIG. 13, the polysilicon 111 is etched.
　続いて、図１４に示すように、ポリシリコン１１１をエッチングし、金属膜１１０を露出させる。 Subsequently, as shown in FIG. 14, the polysilicon 111 is etched to expose the metal film 110.
　続いて、図１５に示すように、ポリシリコン１１１をエッチングし、第１の柱状シリコン層１０５及び第２の柱状シリコン層の上部を露出させる。 Subsequently, as shown in FIG. 15, the polysilicon 111 is etched to expose the upper portions of the first columnar silicon layer 105 and the second columnar silicon layer.
　続いて、図１６に示すように、金属膜１１０をエッチングする。ここでは、ウエットエッチングを用いることが好ましい。 Subsequently, as shown in FIG. 16, the metal film 110 is etched. Here, it is preferable to use wet etching.
　続いて、図１７に示すように、第２の酸化膜１１２と第１の窒化膜１１３とを堆積する。 Subsequently, as shown in FIG. 17, a second oxide film 112 and a first nitride film 113 are deposited.
　続いて、図１８に示すように、第１の窒化膜１１３をエッチングすることで２つの柱状体の側壁にサイドウォール状に残存させ、窒化膜サイドウォール１１４、１１５を形成する。ここでは、第１の酸化膜１１２と窒化膜サイドウォール１１５とから第１の絶縁膜サイドウォール２０１が形成される。また、第１の酸化膜１１２と窒化膜サイドウォール１１４とから第２の絶縁膜サイドウォール２００が形成される。 Subsequently, as shown in FIG. 18, the first nitride film 113 is etched to remain on the side walls of the two columnar bodies to form nitride film side walls 114 and 115. Here, the first insulating film sidewall 201 is formed from the first oxide film 112 and the nitride film sidewall 115. A second insulating film sidewall 200 is formed from the first oxide film 112 and the nitride film sidewall 114.
　続いて、図１９に示すように、第１のゲート電極１１７ｂと、第２のゲート電極１１７ａと、ゲート配線１１７ｃと、を形成するために、第１の柱状シリコン層１０５の上部と第２の柱状シリコン層１０４の上部とを覆うように第３のレジスト１１６を形成する。
　このとき、第１の柱状シリコン層１０５の上部と第２の柱状シリコン層１０４の上部とが第３のレジストで覆われるので、エッチング中にゲート絶縁膜１０９がエッチングされてしまい、柱状シリコン層がエッチングされることが防止される。 Subsequently, as shown in FIG. 19, in order to form the first gate electrode 117b, the second gate electrode 117a, and the gate wiring 117c, the upper part of the first columnar silicon layer 105 and the second gate electrode 117c are formed. A third resist 116 is formed so as to cover the upper part of the columnar silicon layer 104.
At this time, since the upper portion of the first columnar silicon layer 105 and the upper portion of the second columnar silicon layer 104 are covered with the third resist, the gate insulating film 109 is etched during the etching, and the columnar silicon layer is Etching is prevented.
　続いて、図２０に示すように、第２の酸化膜１１２をエッチングする。 Subsequently, as shown in FIG. 20, the second oxide film 112 is etched.
　続いて、図２１に示すように、ポリシリコン１１１をエッチングし、金属膜１１０をエッチングし、第１のゲート電極１１７ｂと、第２のゲート電極１１７ａと、ゲート配線１１７ｃと、を形成する。 Subsequently, as shown in FIG. 21, the polysilicon 111 is etched, the metal film 110 is etched, and a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed.
　続いて、図２２に示すように、第３のレジスト１１６を除去する。 Subsequently, as shown in FIG. 22, the third resist 116 is removed.
　続いて、図２３に示すように、金属膜１１０の残渣を除去するためにウエットエッチングを行う。この処理は、金属膜１１０の残渣が存在しない場合には省略できる。 Subsequently, as shown in FIG. 23, wet etching is performed to remove the residue of the metal film 110. This treatment can be omitted when there is no residue of the metal film 110.
　以上により、第２の工程、即ち、第１の柱状シリコン層１０５及び第２の柱状シリコン層１０４の周囲にゲート絶縁膜１０９を形成し、ゲート絶縁膜１０９の周囲に金属膜１１０とポリシリコン１１１とを堆積するとともにその表面を平坦化し、さらにエッチングを行うことによって第１の柱状シリコン層１０５及び第２の柱状シリコン層１０４の上部を露出させる。そして、第１の柱状シリコン層１０５の上部側壁に第１の絶縁膜サイドウォール２０１を形成し、第２の柱状シリコン層１０４の上部側壁に第２の絶縁膜サイドウォール２００を形成する。そして、ゲート絶縁膜１０９の周囲に金属膜１１０とポリシリコン１１１の積層構造からなる第１のゲート電極１１７ｂと第２のゲート電極１１７ａを形成する。その後、第１のゲート電極１１７ｂと第２のゲート電極１１７ａとに接続されたゲート配線１１７ｃを形成する第２の工程が示された。 As described above, the gate insulating film 109 is formed around the second step, that is, the first columnar silicon layer 105 and the second columnar silicon layer 104, and the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. And the surface of the first columnar silicon layer 105 and the second columnar silicon layer 104 are exposed by performing etching. Then, the first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105, and the second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104. Then, a first gate electrode 117 b and a second gate electrode 117 a having a stacked structure of the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. Thereafter, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a was shown.
（第３の工程）
　次に、第３の工程、即ち、第１の柱状シリコン層１０５の上部に第１のｎ型拡散層１１９を形成し、第１の柱状シリコン層１０５の下部と平面状シリコン層１０７の上部とに第２のｎ型拡散層１２０を形成する。そして、第２の柱状シリコン層１０４の上部に第１のｐ型拡散層１２５を形成し、第２の柱状シリコン層１０４の下部と平面状シリコン層１０７の上部とに第２のｐ型拡散層１２６を形成する第３の工程を示す。 (Third step)
Next, in a third step, that is, a first n-type diffusion layer 119 is formed on the first columnar silicon layer 105, and a lower portion of the first columnar silicon layer 105 and an upper portion of the planar silicon layer 107 are formed. Then, the second n-type diffusion layer 120 is formed. Then, a first p-type diffusion layer 125 is formed on the second columnar silicon layer 104, and a second p-type diffusion layer is formed on the lower portion of the second columnar silicon layer 104 and the upper portion of the planar silicon layer 107. A third step of forming 126 is shown.
　まず、図２４に示すように、第１のｎ型拡散層１１９と第２のｎ型拡散層１２０とを形成するための第４のレジスト１１８を形成する。 First, as shown in FIG. 24, a fourth resist 118 for forming the first n-type diffusion layer 119 and the second n-type diffusion layer 120 is formed.
　次に、図２５に示すように、砒素を注入し、第１のｎ型拡散層１１９と第２のｎ型拡散層１２０とを形成する。ここでは、砒素の代わりにリンを注入することもできる。 Next, as shown in FIG. 25, arsenic is implanted to form a first n-type diffusion layer 119 and a second n-type diffusion layer 120. Here, phosphorus can be implanted instead of arsenic.
　続いて、図２６に示すように、第４のレジスト１１８を除去し、第３の酸化膜１２１を堆積する。 Subsequently, as shown in FIG. 26, the fourth resist 118 is removed, and a third oxide film 121 is deposited.
　続いて、図２７を参照して、熱処理を行う。ここでは、ＮＭＯＳ　ＳＧＴに対して最適化された熱処理を行うことが好ましい。 Subsequently, referring to FIG. 27, heat treatment is performed. Here, it is preferable to perform heat treatment optimized for the NMOS SGT.
　続いて、図２８に示すように、第３の酸化膜１２１を除去し、第２の酸化膜１１２とゲート絶縁膜１０９とをエッチングする。第２の酸化膜１１２はエッチングされ、第１の柱状シリコン層１０５の周囲に残存し、酸化膜サイドウォール１２３となるとともに、第２の柱状シリコン層１０４の周囲に残存し、酸化膜サイドウォール１２２となる。従って、酸化膜サイドウォール１２３と窒化膜サイドウォール１１５とが第１の絶縁膜サイドウォール２０１となるとともに、酸化膜サイドウォール１２２と窒化膜サイドウォール１１４とが第２の絶縁膜サイドウォール２００となる。 Subsequently, as shown in FIG. 28, the third oxide film 121 is removed, and the second oxide film 112 and the gate insulating film 109 are etched. The second oxide film 112 is etched and remains around the first columnar silicon layer 105 to form the oxide film sidewall 123, and also remains around the second columnar silicon layer 104, and the oxide film sidewall 122. It becomes. Therefore, the oxide film side wall 123 and the nitride film side wall 115 become the first insulating film side wall 201, and the oxide film side wall 122 and the nitride film side wall 114 become the second insulating film side wall 200. .
　続いて、図２９に示すように、第１のｐ型拡散層１２５と第２のｐ型拡散層１２６とを形成するための第５のレジスト１２４を形成する。 Subsequently, as shown in FIG. 29, a fifth resist 124 for forming the first p-type diffusion layer 125 and the second p-type diffusion layer 126 is formed.
　続いて、図３０に示すように、ボロンを注入し、第１のｐ型拡散層１２５と第２のｐ型拡散層１２６とを形成する。 Subsequently, as shown in FIG. 30, boron is implanted to form the first p-type diffusion layer 125 and the second p-type diffusion layer 126.
　続いて、　図３１に示すように、第５のレジスト１２４を除去する。 Subsequently, as shown in FIG. 31, the fifth resist 124 is removed.
　続いて、図３２に示すように、第２の窒化膜１２７を堆積する。 Subsequently, as shown in FIG. 32, a second nitride film 127 is deposited.
　続いて、図３３を参照して、熱処理を行う。ここでは、ＰＭＯＳ　ＳＧＴに対して最適化された熱処理を行うことが好ましい。 Subsequently, referring to FIG. 33, heat treatment is performed. Here, it is preferable to perform heat treatment optimized for PMOS SGT.
　以上により、第３の工程、即ち、第１の柱状シリコン層１０５の上部に第１のｎ型拡散層１１９を形成し、第１の柱状シリコン層１０５の下部と平面状シリコン層１０７の上部に第２のｎ型拡散層１２０を形成する。そして、第２の柱状シリコン層１０４の上部に第１のｐ型拡散層１２５を形成し、第２の柱状シリコン層１０４の下部と平面状シリコン層１０７の上部に第２のｐ型拡散層１２６を形成する第３の工程が示された。 As described above, in the third step, that is, the first n-type diffusion layer 119 is formed on the upper portion of the first columnar silicon layer 105, and the lower portion of the first columnar silicon layer 105 and the upper portion of the planar silicon layer 107 are formed. A second n-type diffusion layer 120 is formed. Then, a first p-type diffusion layer 125 is formed above the second columnar silicon layer 104, and a second p-type diffusion layer 126 is formed below the second columnar silicon layer 104 and above the planar silicon layer 107. A third step of forming was shown.
　上記実施例においては、ゲート電極を形成した後に第１のｎ型拡散層と第２のｎ型拡散層と第１のｐ型拡散層と第２のｐ型拡散層を形成した。しかしこれに限られず、柱状シリコン層と平面状シリコン層とを形成した後に、柱状シリコン層の側壁にサイドウォールを形成し、その後に第１のｎ型拡散層及び第２のｎ型拡散層を形成し、さらにその後に、第１のｐ型拡散層及び第２のｐ型拡散層を形成し、しかる後にゲート電極を形成してもよい。 In the above embodiment, after forming the gate electrode, the first n-type diffusion layer, the second n-type diffusion layer, the first p-type diffusion layer, and the second p-type diffusion layer were formed. However, the present invention is not limited to this. After the columnar silicon layer and the planar silicon layer are formed, a sidewall is formed on the sidewall of the columnar silicon layer, and then the first n-type diffusion layer and the second n-type diffusion layer are formed. Then, after that, a first p-type diffusion layer and a second p-type diffusion layer may be formed, and then a gate electrode may be formed.
（第４の工程）
　次に、第１の絶縁膜サイドウォール２０１と、第２の絶縁膜サイドウォール２０２と、第１のゲート電極１１７ｂと、第２のゲート電極１１７ａと、ゲート配線１１７ｃとの側壁に、第３の絶縁膜サイドウォール２０２を形成する第４の工程を示す。 (Fourth process)
Next, a third insulating film sidewall 201, a second insulating film sidewall 202, a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed on the sidewalls of the third insulating film sidewall 201, the second insulating film sidewall 202, The 4th process of forming the insulating film side wall 202 is shown.
　まず、図３４に示すように、第２の窒化膜１２７をエッチングし、サイドウォール状に残存させ、窒化膜サイドウォール１２８、１２９、１３０を形成する。
　ここで、窒化膜サイドウォール１２８は、第３の絶縁膜サイドウォール２０２となる。 First, as shown in FIG. 34, the second nitride film 127 is etched and left in a sidewall shape to form nitride film sidewalls 128, 129, and 130.
Here, the nitride film sidewall 128 becomes the third insulating film sidewall 202.
　このとき、第１のゲート電極１１７ｂは、上部が第１の絶縁膜サイドウォール２０１で覆われ、側壁が第３の絶縁膜サイドウォール２０２で覆われる。また、第１の絶縁膜サイドウォール２０１の側壁は第３の絶縁膜サイドウォール２０２で覆われる。従って、平面状シリコン層上部の拡散層上に形成するコンタクトが、第１のゲート電極側に位置ずれしたとき、第１のゲート電極とコンタクトが短絡することが防止される。 At this time, the upper part of the first gate electrode 117b is covered with the first insulating film sidewall 201, and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact are prevented from being short-circuited.
　同様に、第２のゲート電極１１７ａは、上部が第２の絶縁膜サイドウォール２００で覆われ、側壁が第３の絶縁膜サイドウォール２０２で覆われる。また、第２の絶縁膜サイドウォール２００の側壁は第３の絶縁膜サイドウォール２０２で覆われる。従って、平面状シリコン層上部の拡散層上に形成するコンタクトが第２のゲート電極１１７ａの近傍に形成された場合において、そのコンタクトが第２のゲート電極側に位置ずれしたときに、第２のゲート電極とコンタクトとが短絡することが防止される。 Similarly, the upper part of the second gate electrode 117 a is covered with the second insulating film sidewall 200 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode side, the second A short circuit between the gate electrode and the contact is prevented.
　以上により、第１の絶縁膜サイドウォール２０１と、第２の絶縁膜サイドウォール２０２と、第１のゲート電極１１７ｂと、第２のゲート電極１１７ａと、ゲート配線１１７ｃの側壁とに第３の絶縁膜サイドウォール２０２を形成する第４の工程が示された。 As described above, the third insulating film sidewall 201, the second insulating film sidewall 202, the first gate electrode 117b, the second gate electrode 117a, and the side wall of the gate wiring 117c are third insulating. A fourth step of forming the film sidewall 202 has been shown.
（第５の工程）
　次に、第１のｎ型拡散層１１９上と、第２のｎ型拡散層１２０上と、第１のｐ型拡散層１２５と、第２のｐ型拡散層１２６上と、ゲート配線１１７ｃ上と、にシリサイドを形成する第５の工程を示す。 (Fifth step)
Next, on the first n-type diffusion layer 119, on the second n-type diffusion layer 120, on the first p-type diffusion layer 125, on the second p-type diffusion layer 126, and on the gate wiring 117c. 5 shows a fifth step of forming silicide.
　まず、図３５に示すように、ニッケルやコバルトといった金属を堆積するとともに熱処理を行い、未反応の金属を除去する。これにより、第１のｎ型拡散層１１９上と、第２のｎ型拡散層１２０上と、第１のｐ型拡散層１２５と、第２のｐ型拡散層１２６上と、ゲート配線１１７ｃ上とに、シリサイド１３３、１３４、１３５、１３６、１３２、１３１、１３７を形成する。このとき、第２のｎ型拡散層１２０と第２のｐ型拡散層１２６とがシリサイド１３４、１３５によって接続される。インバータの出力端子をシリコン柱下部に形成しないときは、第２のｎ型拡散層１２０と第２のｐ型拡散層１２６とをシリサイドにより接続することを省略できる。 First, as shown in FIG. 35, a metal such as nickel or cobalt is deposited and heat treatment is performed to remove unreacted metal. Thereby, on the first n-type diffusion layer 119, the second n-type diffusion layer 120, the first p-type diffusion layer 125, the second p-type diffusion layer 126, and the gate wiring 117c. Then, silicides 133, 134, 135, 136, 132, 131, and 137 are formed. At this time, the second n-type diffusion layer 120 and the second p-type diffusion layer 126 are connected by the silicides 134 and 135. When the output terminal of the inverter is not formed under the silicon pillar, it is possible to omit connecting the second n-type diffusion layer 120 and the second p-type diffusion layer 126 with silicide.
　以上により、前記第１のｎ型拡散層１１９上と、前記第２のｎ型拡散層１２０上と、第１のｐ型拡散層１２５と、第２のｐ型拡散層１２６上と、ゲート配線１１７ｃ上とにシリサイドを形成する第５の工程が示された。 As described above, the first n-type diffusion layer 119, the second n-type diffusion layer 120, the first p-type diffusion layer 125, the second p-type diffusion layer 126, and the gate wiring. A fifth step of forming silicide on 117c is shown.
　次に、図３６に示すように、第３の窒化膜１３８を堆積し、さらに、層間絶縁膜１３９を堆積するとともにその表面を平坦化する。 Next, as shown in FIG. 36, a third nitride film 138 is deposited, an interlayer insulating film 139 is further deposited, and the surface thereof is flattened.
　続いて、図３７に示すように、第１の柱状シリコン層１０５上と第２の柱状シリコン層１０４上とにコンタクトを形成するための第６のレジスト１４０を形成する。 Subsequently, as shown in FIG. 37, a sixth resist 140 for forming contacts on the first columnar silicon layer 105 and the second columnar silicon layer 104 is formed.
　続いて、図３８に示すように、層間絶縁膜１３９をエッチングし、コンタクト孔１４１、１４２を形成する。 Subsequently, as shown in FIG. 38, the interlayer insulating film 139 is etched to form contact holes 141 and 142.
　続いて、図３９に示すように、第６のレジスト１４０を除去する。 Subsequently, as shown in FIG. 39, the sixth resist 140 is removed.
　続いて、図４０に示すように、ゲート配線１１７ｃ上と、平面状シリコン層１０７上と、にコンタクトを形成するための第７のレジスト１４３を形成する。 Subsequently, as shown in FIG. 40, a seventh resist 143 for forming a contact is formed on the gate wiring 117c and the planar silicon layer 107.
　続いて、図４１に示すように、層間絶縁膜１３９をエッチングし、コンタクト孔１４４、１４５を形成する。 Subsequently, as shown in FIG. 41, the interlayer insulating film 139 is etched to form contact holes 144 and 145.
　続いて、図４２に示すように、第７のレジスト１４３を除去する。 Subsequently, as shown in FIG. 42, the seventh resist 143 is removed.
　続いて、図４３に示すように、第３の窒化膜１３８をエッチングする。 Subsequently, as shown in FIG. 43, the third nitride film 138 is etched.
　続いて、図４４に示すように、金属を堆積し、コンタクト１４６、１４７、１４８、１４９を形成する。 Subsequently, as shown in FIG. 44, metal is deposited to form contacts 146, 147, 148, and 149.
　続いて、図４５に示すように、金属配線のための金属１５０を堆積する。 Subsequently, as shown in FIG. 45, a metal 150 for metal wiring is deposited.
　続いて、図４６に示すように、金属配線を形成するために第８のレジスト１５１、１５２、１５３、１５４を形成する。 Subsequently, as shown in FIG. 46, eighth resists 151, 152, 153, 154 are formed in order to form metal wiring.
　続いて、図４７に示すように、金属１５０をエッチングし、金属配線１５５、１５６、１５７、１５８を形成する。 Subsequently, as shown in FIG. 47, the metal 150 is etched to form metal wirings 155, 156, 157, 158.
　続いて、図４８に示すように、第８のレジスト１５１、１５２、１５３、１５４を除去する。
　以上により、工程数が少なく、ゲートのエッチング中にシリコン柱上部が保護されるＳＧＴの製造方法が示された。 Subsequently, as shown in FIG. 48, the eighth resists 151, 152, 153, 154 are removed.
As described above, the manufacturing method of SGT in which the number of steps is small and the upper part of the silicon pillar is protected during the etching of the gate is shown.
　上記製造方法によって得られる半導体装置の構造を図１に示す。
　図１に示すように、半導体装置は、
　シリコン基板１０１上に形成された平面状シリコン層１０７と、
　前記平面状シリコン層１０７上に形成された第１の柱状シリコン層１０５と、
　前記平面状シリコン層１０７上に形成された第２の柱状シリコン層１０４と、
　前記第１の柱状シリコン層１０５の周囲に形成されたゲート絶縁膜１０９と、
　前記ゲート絶縁膜１０９の周囲に形成された金属膜１１０とポリシリコン１１１の積層構造からなる第１のゲート電極１１７ｂと、
　前記第２の柱状シリコン層１０４の周囲に形成されたゲート絶縁膜１０９と、
前記ゲート絶縁膜１０９の周囲に形成された金属膜１１０とポリシリコン１１１の積層構造からなる第２のゲート電極１１７ａと、
　前記第１のゲート電極１１７ｂと前記第２のゲート電極１１７ａに接続されたゲート配線１１７ｃと、
　前記第１の柱状シリコン層１０５の上部に形成された第１のｎ型拡散層１１９と、
　前記第１の柱状シリコン層１０５の下部と前記平面状シリコン層１０７の上部に形成された第２のｎ型拡散層１２０と、
　前記第２の柱状シリコン層１０４の上部に形成された第１のｐ型拡散層１２５と、
　前記第２の柱状シリコン層１０４の下部と前記平面状シリコン層１０７の上部に形成された第２のｐ型拡散層１２６と、
　前記第１の柱状シリコン層１０５の上部側壁と前記第１のゲート電極１１７ｂ上部に形成された第１の絶縁膜サイドウォール２０１と、
　前記第２の柱状シリコン層１０４の上部側壁と前記第２のゲート電極１１７ａ上部に形成された第２の絶縁膜サイドウォール２００と、
　前記第１の絶縁膜サイドウォール２０１と前記第２の絶縁膜サイドウォール２００と前記第１のゲート電極１１７ｂと前記第２のゲート電極１１７ａと前記ゲート配線１１７ｃの側壁に形成された第３の絶縁膜サイドウォール２０２と、
　前記第１のｎ型拡散層１１９上と前記第２のｎ型拡散層１２０上と前記第１のｐ型拡散層１２５と前記第２のｐ型拡散層１２６上と、ゲート配線１１７ｃ上に形成されたシリサイド１３３、１３４、１３５、１３６、１３２、１３１、１３７と、
　を有する。 A structure of a semiconductor device obtained by the manufacturing method is shown in FIG.
As shown in FIG.
A planar silicon layer 107 formed on the silicon substrate 101;
A first columnar silicon layer 105 formed on the planar silicon layer 107;
A second columnar silicon layer 104 formed on the planar silicon layer 107;
A gate insulating film 109 formed around the first columnar silicon layer 105;
A first gate electrode 117b having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109;
A gate insulating film 109 formed around the second columnar silicon layer 104;
A second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109;
A gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a;
A first n-type diffusion layer 119 formed on the first columnar silicon layer 105;
A second n-type diffusion layer 120 formed below the first columnar silicon layer 105 and above the planar silicon layer 107;
A first p-type diffusion layer 125 formed on the second columnar silicon layer 104;
A second p-type diffusion layer 126 formed below the second columnar silicon layer 104 and above the planar silicon layer 107;
An upper sidewall of the first columnar silicon layer 105 and a first insulating film sidewall 201 formed on the first gate electrode 117b;
A second insulating film sidewall 200 formed on the upper sidewall of the second columnar silicon layer 104 and the second gate electrode 117a;
Third insulation formed on the side walls of the first insulating film sidewall 201, the second insulating film sidewall 200, the first gate electrode 117b, the second gate electrode 117a, and the gate wiring 117c. A membrane sidewall 202;
Formed on the first n-type diffusion layer 119, the second n-type diffusion layer 120, the first p-type diffusion layer 125, the second p-type diffusion layer 126, and the gate wiring 117c. Silicided 133, 134, 135, 136, 132, 131, 137,
Have
　このとき、第１のゲート電極１１７ｂは、上部が第１の絶縁膜サイドウォール２０１で覆われ、側壁が第３の絶縁膜サイドウォール２０２で覆われる。また、第１の絶縁膜サイドウォール２０１の側壁は第３の絶縁膜サイドウォール２０２で覆われる。従って、平面状シリコン層上部の拡散層上に形成するコンタクト１４０が、第１のゲート電極１１７ｂ側に位置ずれしたときに、第１のゲート電極１１７ｂとコンタクト１４０とが短絡することが防止される。
　また、同様に、第２のゲート電極１１７ａは、上部が第２の絶縁膜サイドウォール２００で覆われ、側壁が第３の絶縁膜サイドウォール２０２で覆われる。また、第２の絶縁膜サイドウォール２００の側壁は第３の絶縁膜サイドウォール２０２で覆われる。従って、平面状シリコン層上部の拡散層上に形成するコンタクトが第２のゲート電極１１７ａの近傍に形成された場合において、そのコンタクトが第２のゲート電極１１７ａ側に位置ずれしたときに、第２のゲート電極１１７ａとコンタクトとが短絡することを防止できる。 At this time, the upper portion of the first gate electrode 117 b is covered with the first insulating film sidewall 201 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact 140 formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode 117b side, the first gate electrode 117b and the contact 140 are prevented from being short-circuited. .
Similarly, the second gate electrode 117 a is covered with the second insulating film sidewall 200 at the top and with the third insulating film sidewall 202 at the sidewall. Further, the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode 117a side, the second It is possible to prevent a short circuit between the gate electrode 117a and the contact.
　なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。 The present invention is capable of various embodiments and modifications without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for describing an example of the present invention, and does not limit the scope of the present invention.
　例えば、上記実施例において、ｐ型（ｐ＋型を含む。）とｎ型（ｎ＋型を含む。）とをそれぞれ反対の導電型とした半導体装置の製造方法、及び、それにより得られる半導体装置も当然に本発明の技術的範囲に含まれる。 For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p + -type) and n-type (including n + -type) are opposite in conductivity type, and semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.
１０１．シリコン基板
１０２．第１のレジスト
１０３．第１のレジスト
１０４．第２の柱状シリコン層
１０５．第１の柱状シリコン層
１０６．第２のレジスト
１０７．平面状シリコン層
１０８．第１の酸化膜
１０９．ゲート絶縁膜
１１０．金属膜
１１１．ポリシリコン
１１２．第２の酸化膜
１１３．第１の窒化膜
１１４．窒化膜サイドウォール
１１５．窒化膜サイドウォール
１１６．第３のレジスト
１１７ａ．第２のゲート電極
１１７ｂ．第１のゲート電極
１１７ｃ．ゲート配線
１１８．第４のレジスト
１１９．第１のｎ型拡散層
１２０．第２のｎ型拡散層
１２１．第３の酸化膜
１２２．酸化膜サイドウォール
１２３．酸化膜サイドウォール
１２４．第５のレジスト
１２５．第１のｐ型拡散層
１２６．第２のｐ型拡散層
１２７．第２の窒化膜
１２８．窒化膜サイドウォール
１２９．窒化膜サイドウォール
１３０．窒化膜サイドウォール
１３１．シリサイド
１３２．シリサイド
１３３．シリサイド
１３４．シリサイド
１３５．シリサイド
１３６．シリサイド
１３７．シリサイド
１３８．第３の窒化膜
１３９．層間絶縁膜
１４０．第６のレジスト
１４１．コンタクト孔
１４２．コンタクト孔
１４３．第７のレジスト
１４４．コンタクト孔
１４５．コンタクト孔
１４６．コンタクト
１４７．コンタクト
１４８．コンタクト
１４９．コンタクト
１５０．金属
１５１．第８のレジスト
１５２．第８のレジスト
１５３．第８のレジスト
１５４．第８のレジスト
１５５．金属配線
１５６．金属配線
１５７．金属配線
１５８．金属配線
２００．第２の絶縁膜サイドウォール
２０１．第１の絶縁膜サイドウォール
２０２．第３の絶縁膜サイドウォール 101. Silicon substrate 102. First resist 103. First resist 104. Second columnar silicon layer 105. First columnar silicon layer 106. Second resist 107. Planar silicon layer 108. First oxide film 109. Gate insulating film 110. Metal film 111. Polysilicon 112. Second oxide film 113. First nitride film 114. Nitride film sidewall 115. Nitride film sidewall 116. Third resist 117a. Second gate electrode 117b. First gate electrode 117c. Gate wiring 118. Fourth resist 119. First n-type diffusion layer 120. Second n-type diffusion layer 121. Third oxide film 122. Oxide film side wall 123. Oxide film side wall 124. Fifth resist 125. First p-type diffusion layer 126. Second p-type diffusion layer 127. Second nitride film 128. Nitride film sidewall 129. Nitride film sidewall 130. Nitride film sidewall 131. Silicide 132. Silicide 133. Silicide 134. Silicide 135. Silicide 136. Silicide 137. Silicide 138. Third nitride film 139. Interlayer insulating film 140. Sixth resist 141. Contact hole 142. Contact hole 143. Seventh resist 144. Contact hole 145. Contact hole 146. Contact 147. Contact 148. Contact 149. Contact 150. Metal 151. Eighth resist 152. Eighth resist 153. Eighth resist 154. Eighth resist 155. Metal wiring 156. Metal wiring 157. Metal wiring 158. Metal wiring 200. Second insulating film sidewall 201. First insulating film sidewall 202. Third insulating film sidewall

Claims (6)

  1. 　シリコン基板上に平面状シリコン層を形成し、前記平面状シリコン層上に第１の柱状シリコン層と第２の柱状シリコン層とを形成する第１の工程と、
    　前記第１の工程の後、前記第１及び前記第２の柱状シリコン層の周囲にゲート絶縁膜を形成し、前記ゲート絶縁膜の周囲に金属膜及びポリシリコンを堆積するとともに平坦化をし、エッチングを行うことにより前記第１及び前記第２の柱状シリコン層の上部とを露出し、前記第１の柱状シリコン層の上部側壁に第１の絶縁膜サイドウォールを形成し、前記第２の柱状シリコン層の上部側壁に第２の絶縁膜サイドウォールを形成し、前記ゲート絶縁膜の周囲に金属膜とポリシリコンの積層構造からなる第１のゲート電極と第２のゲート電極とを形成し、前記第１のゲート電極と前記第２のゲート電極とに接続されたゲート配線を形成する第２の工程と、
    　前記第２の工程の後、前記第１の柱状シリコン層の上部に第１のｎ型拡散層を形成し、前記第１の柱状シリコン層の下部と前記平面状シリコン層の上部に第２のｎ型拡散層を形成し、前記第２の柱状シリコン層の上部に第１のｐ型拡散層を形成し、前記第２の柱状シリコン層の下部と前記平面状シリコン層の上部に第２のｐ型拡散層を形成する第３の工程と、
    　前記第３の工程の後、前記第１及び前記第２の絶縁膜サイドウォールと前記第１及び前記第２のゲート電極と前記ゲート配線の側壁とに第３の絶縁膜サイドウォールを形成する第４の工程と、
    　前記第４の工程の後、前記第１及び前記第２のｎ型拡散層上と前記第１及び前記第２のｐ型拡散層上と前記ゲート配線上とにシリサイドを形成する第５の工程と、を有する、
    　ことを特徴とする半導体装置の製造方法。     Forming a planar silicon layer on a silicon substrate, and forming a first columnar silicon layer and a second columnar silicon layer on the planar silicon layer;
    After the first step, a gate insulating film is formed around the first and second columnar silicon layers, a metal film and polysilicon are deposited around the gate insulating film and planarized, Etching is performed to expose the upper portions of the first and second columnar silicon layers, and a first insulating film sidewall is formed on the upper sidewall of the first columnar silicon layer. Forming a second insulating film side wall on the upper side wall of the silicon layer, forming a first gate electrode and a second gate electrode having a laminated structure of a metal film and polysilicon around the gate insulating film; A second step of forming a gate wiring connected to the first gate electrode and the second gate electrode;
    After the second step, a first n-type diffusion layer is formed on the first columnar silicon layer, and a second n-type diffusion layer is formed on the lower portion of the first columnar silicon layer and the upper portion of the planar silicon layer. An n-type diffusion layer is formed, a first p-type diffusion layer is formed on the second columnar silicon layer, and a second layer is formed on the lower portion of the second columnar silicon layer and the upper portion of the planar silicon layer. a third step of forming a p-type diffusion layer;
    After the third step, a third insulating film sidewall is formed on the first and second insulating film sidewalls, the first and second gate electrodes, and the side walls of the gate wiring. 4 steps,
    After the fourth step, a fifth step of forming silicide on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and the gate wiring. And having
    A method for manufacturing a semiconductor device.
  2. 　前記シリコン基板上に前記第１及び前記第２の柱状シリコン層を形成するための第１のレジストを形成し、前記シリコン基板をエッチングし、前記第１及び前記第２の柱状シリコン層とを形成し、前記第１のレジストを除去し、前記平面状シリコン層を形成するための第２のレジストを形成し、前記シリコン基板をエッチングし、前記平面状シリコン層を形成し、前記第２のレジストを除去する、
    　ことを特徴とする請求項１に記載の半導体装置の製造方法。     A first resist for forming the first and second columnar silicon layers is formed on the silicon substrate, the silicon substrate is etched, and the first and second columnar silicon layers are formed. And removing the first resist, forming a second resist for forming the planar silicon layer, etching the silicon substrate, forming the planar silicon layer, and forming the second resist. Remove,
    The method of manufacturing a semiconductor device according to claim 1.
  3. 　前記シリコン基板上に形成された前記平面状シリコン層と、前記平面状シリコン層上に形成された前記第１の柱状シリコン層と、前記平面状シリコン層上に形成された第２の柱状シリコン層と、前記平面状シリコン層の周囲に第１の絶縁膜が形成された構造において、前記第１及び前記第２の柱状シリコン層の周囲に前記ゲート絶縁膜が形成され、
    　前記ゲート絶縁膜の周囲に金属膜を形成し、ポリシリコンを堆積するとともに平坦化し、前記ポリシリコンをエッチングし、前記金属膜を露出させ、前記ポリシリコンをエッチングし、前記第１及び前記第２の柱状シリコン層の上部とを露出し、
    　前記金属膜をエッチングし、第２の酸化膜と第１の窒化膜とを堆積し、前記第１の窒化膜をサイドウォール状にエッチングすることで、窒化膜サイドウォールを形成し、
    　前記第２の酸化膜と前記窒化膜サイドウォールとが前記第１及び前記第２の絶縁膜サイドウォールとなり、
    　前記第１及び前記第２のゲート電極と前記ゲート配線とを形成するために、前記第１及び前記第２の柱状シリコン層の上部を覆うように第３のレジストを形成し、
    　前記第２の酸化膜をエッチングし、前記ポリシリコンをエッチングし、前記金属膜をエッチングし、前記第１及び前記第２のゲート電極と前記ゲート配線とを形成した後、前記第３のレジストを除去することを特徴とする請求項１に記載の半導体装置の製造方法。     The planar silicon layer formed on the silicon substrate, the first columnar silicon layer formed on the planar silicon layer, and the second columnar silicon layer formed on the planar silicon layer And in the structure in which the first insulating film is formed around the planar silicon layer, the gate insulating film is formed around the first and second columnar silicon layers,
    Forming a metal film around the gate insulating film; depositing and planarizing polysilicon; etching the polysilicon; exposing the metal film; etching the polysilicon; and Exposing the top of the columnar silicon layer,
    Etching the metal film, depositing a second oxide film and a first nitride film, and etching the first nitride film into a sidewall shape to form a nitride film sidewall;
    The second oxide film and the nitride film sidewall serve as the first and second insulating film sidewalls,
    In order to form the first and second gate electrodes and the gate wiring, a third resist is formed so as to cover upper portions of the first and second columnar silicon layers,
    The second oxide film is etched, the polysilicon is etched, the metal film is etched, the first and second gate electrodes and the gate wiring are formed, and then the third resist is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed.
  4. 　第１のｎ型拡散層と第２のｎ型拡散層とを形成するための第４のレジストを形成し、砒素を注入し、前記第１及び前記第２のｎ型拡散層とを形成し、前記第４のレジストを除去し、第３の酸化膜を堆積した後、熱処理を行い、
    　前記第３の酸化膜を除去し、前記第２の酸化膜と前記ゲート絶縁膜とをエッチングし、前記第２の酸化膜は、エッチングされ、前記第１及び前記第２の柱状シリコン層の周囲に残存し酸化膜サイドウォールとなり、
    　前記酸化膜サイドウォールと前記窒化膜サイドウォールとが前記第１の絶縁膜サイドウォールとなるとともに、前記酸化膜サイドウォールと前記窒化膜サイドウォールとが前記第２の絶縁膜サイドウォールとなり、
    　第１のｐ型拡散層と第２のｐ型拡散層とを形成するための第５のレジストを形成し、ボロンを注入し、前記第１及び前記第２のｐ型拡散層を形成し、前記第５のレジストを除去し、を堆積した後、熱処理を行う、
    　ことを特徴とする請求項３に記載の半導体装置の製造方法。     A fourth resist for forming the first n-type diffusion layer and the second n-type diffusion layer is formed, arsenic is implanted, and the first and second n-type diffusion layers are formed. , After removing the fourth resist and depositing a third oxide film, a heat treatment is performed,
    The third oxide film is removed, the second oxide film and the gate insulating film are etched, and the second oxide film is etched to surround the first and second columnar silicon layers. Remain in the oxide film sidewall,
    The oxide film sidewall and the nitride film sidewall serve as the first insulating film sidewall, and the oxide film sidewall and the nitride film sidewall serve as the second insulating film sidewall,
    Forming a fifth resist for forming the first p-type diffusion layer and the second p-type diffusion layer; implanting boron; forming the first and second p-type diffusion layers; Removing the fifth resist, depositing, and performing a heat treatment;
    The method of manufacturing a semiconductor device according to claim 3.
  5. 　第２の窒化膜をさらに堆積し、前記第２の窒化膜をサイドウォール状にエッチングすることで、第３の絶縁膜サイドウォールとなる窒化膜サイドウォールを形成する、
    　ことを特徴とする請求項４に記載の半導体装置の製造方法。     A second nitride film is further deposited, and the second nitride film is etched into a sidewall shape to form a nitride film sidewall serving as a third insulating film sidewall.
    The method of manufacturing a semiconductor device according to claim 4.
  6. 　シリコン基板上に形成された平面状シリコン層と、
    　前記平面状シリコン層上に形成された第１及び第２の柱状シリコン層と、
    　前記第１の柱状シリコン層の周囲に形成された第１のゲート絶縁膜と、
    　前記第１のゲート絶縁膜の周囲に形成された金属膜及びポリシリコンの積層構造からなる第１のゲート電極と、
    　前記第２の柱状シリコン層の周囲に形成された第２のゲート絶縁膜と、
    　前記第２のゲート絶縁膜の周囲に形成された金属膜及びポリシリコンの積層構造からなる第２のゲート電極と、
    　前記第１及び前記第２のゲート電極に接続されたゲート配線と、
    　前記第１の柱状シリコン層の上部に形成された第１のｎ型拡散層と、
    　前記第１の柱状シリコン層の下部と前記平面状シリコン層の上部とに形成された第２のｎ型拡散層と、
    　前記第２の柱状シリコン層の上部に形成された第１のｐ型拡散層と、
    　前記第２の柱状シリコン層の下部と前記平面状シリコン層の上部とに形成された第２のｐ型拡散層と、
    　前記第１の柱状シリコン層の上部側壁と前記第１のゲート電極上部とに形成された第１の絶縁膜サイドウォールと、
    　前記第２の柱状シリコン層の上部側壁と前記第２のゲート電極上部とに形成された第２の絶縁膜サイドウォールと、
    　前記第１及び前記第２の絶縁膜サイドウォールと前記第１及び前記第２のゲート電極と前記ゲート配線の側壁とに形成された第３の絶縁膜サイドウォールと、
    　前記第１及び前記第２のｎ型拡散層上と前記第１及び前記第２のｐ型拡散層上と、ゲート配線上に形成されたシリサイドと、を有する、
    　ことを特徴とする半導体装置。     A planar silicon layer formed on a silicon substrate;
    First and second columnar silicon layers formed on the planar silicon layer;
    A first gate insulating film formed around the first columnar silicon layer;
    A first gate electrode having a laminated structure of a metal film and polysilicon formed around the first gate insulating film;
    A second gate insulating film formed around the second columnar silicon layer;
    A second gate electrode having a laminated structure of a metal film and polysilicon formed around the second gate insulating film;
    A gate wiring connected to the first and second gate electrodes;
    A first n-type diffusion layer formed on top of the first columnar silicon layer;
    A second n-type diffusion layer formed in a lower portion of the first columnar silicon layer and an upper portion of the planar silicon layer;
    A first p-type diffusion layer formed on top of the second columnar silicon layer;
    A second p-type diffusion layer formed in a lower portion of the second columnar silicon layer and an upper portion of the planar silicon layer;
    A first insulating film sidewall formed on an upper sidewall of the first columnar silicon layer and an upper portion of the first gate electrode;
    A second insulating film sidewall formed on an upper sidewall of the second columnar silicon layer and an upper portion of the second gate electrode;
    A third insulating film sidewall formed on the first and second insulating film sidewalls, the first and second gate electrodes, and a sidewall of the gate wiring;
    A silicide formed on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and a gate wiring;
    A semiconductor device.
PCT/JP2011/078828 2011-12-13 2011-12-13 Semiconductor device manufacturing method, and semiconductor device WO2013088520A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020137015260A KR20130093149A (en) 2011-12-13 2011-12-13 Production method of semiconductor device and semiconductor device
JP2013527212A JP5643900B2 (en) 2011-12-13 2011-12-13 Semiconductor device manufacturing method and semiconductor device
CN2011800599173A CN103262234A (en) 2011-12-13 2011-12-13 Semiconductor device manufacturing method, and semiconductor device
PCT/JP2011/078828 WO2013088520A1 (en) 2011-12-13 2011-12-13 Semiconductor device manufacturing method, and semiconductor device
TW101144278A TW201324627A (en) 2011-12-13 2012-11-27 Method for manufacturing semiconductor device, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/078828 WO2013088520A1 (en) 2011-12-13 2011-12-13 Semiconductor device manufacturing method, and semiconductor device

Publications (1)

Publication Number Publication Date
WO2013088520A1 true WO2013088520A1 (en) 2013-06-20

Family

ID=48612007

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/078828 WO2013088520A1 (en) 2011-12-13 2011-12-13 Semiconductor device manufacturing method, and semiconductor device

Country Status (5)

Country Link
JP (1) JP5643900B2 (en)
KR (1) KR20130093149A (en)
CN (1) CN103262234A (en)
TW (1) TW201324627A (en)
WO (1) WO2013088520A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5639317B1 (en) * 2013-11-06 2014-12-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device having SGT and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096468A1 (en) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor storage device, semiconductor device having memory mounted therein, and methods for fabricating the devices
JP2010251678A (en) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd Method of manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5323610B2 (en) * 2009-08-18 2013-10-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device and manufacturing method thereof
JP4987926B2 (en) * 2009-09-16 2012-08-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device
JP5031809B2 (en) * 2009-11-13 2012-09-26 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device
JP2011216657A (en) * 2010-03-31 2011-10-27 Unisantis Electronics Japan Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096468A1 (en) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor storage device, semiconductor device having memory mounted therein, and methods for fabricating the devices
JP2010251678A (en) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd Method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5639317B1 (en) * 2013-11-06 2014-12-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device having SGT and manufacturing method thereof
WO2015068226A1 (en) * 2013-11-06 2015-05-14 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device with sgt and method for manufacturing said semiconductor device
US9613827B2 (en) 2013-11-06 2017-04-04 Unisantis Electronics Singapore Pte. Ltd. SGT-including semiconductor device and method for manufacturing the same
US10312110B2 (en) 2013-11-06 2019-06-04 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing an SGT-including semiconductor device

Also Published As

Publication number Publication date
TW201324627A (en) 2013-06-16
CN103262234A (en) 2013-08-21
JPWO2013088520A1 (en) 2015-04-27
KR20130093149A (en) 2013-08-21
JP5643900B2 (en) 2014-12-17

Similar Documents

Publication Publication Date Title
US8877578B2 (en) Method for producing semiconductor device and semiconductor device
JP2011061181A (en) Semiconductor device and method of manufacturing the same
WO2013080378A1 (en) Semiconductor device manufacturing method and semiconductor device
JP5990843B2 (en) Semiconductor device manufacturing method and semiconductor device
US20110062521A1 (en) Semiconductor device
JP5731073B1 (en) Semiconductor device manufacturing method and semiconductor device
WO2013171908A1 (en) Method for producing semiconductor device, and semiconductor device
WO2016031014A1 (en) Semiconductor device, and method for manufacturing semiconductor device
JP5928658B1 (en) Semiconductor device manufacturing method and semiconductor device
JP5654184B1 (en) Semiconductor device manufacturing method and semiconductor device
JP5596245B1 (en) Semiconductor device manufacturing method and semiconductor device
US8664063B2 (en) Method of producing a semiconductor device and semiconductor device
JP5643900B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6230648B2 (en) Semiconductor device
JP5926354B2 (en) Semiconductor device
JP5833214B2 (en) Semiconductor device manufacturing method and semiconductor device
JP5974066B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6159777B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6235662B2 (en) Semiconductor device
JP5936653B2 (en) Semiconductor device
JP5869166B2 (en) Semiconductor device manufacturing method and semiconductor device
JP5986618B2 (en) Semiconductor device
JP2010177688A (en) Semiconductor device
JP2016195274A (en) Semiconductor device manufacturing method and semiconductor device
JP2015079988A (en) Semiconductor device manufacturing method and semiconductor device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2013527212

Country of ref document: JP

Kind code of ref document: A

Ref document number: 20137015260

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11877444

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11877444

Country of ref document: EP

Kind code of ref document: A1