JP2005093458A - Semiconductor device and its fabricating process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form the drain offset of a high breakdown voltage MOS transistor with high precision and to realize high speed operation. <P>SOLUTION: The drain of an MOS transistor formed on a first conductivity type semiconductor substrate 1 comprises a second conductivity type first lightly doped diffusion layer 14, a second conductivity type first heavily doped diffusion layer 19, a second conductivity type first lightly doped diffusion layer 21, and second conductivity type second heavily doped diffusion layer 18 formed sequentially from the side close to a gate electrode 12. A contact 25 for connecting the drain of the MOS transistor with the outside is formed on the second heavily doped diffusion layer 18. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device made of a high voltage MOS transistor and a method for manufacturing the same.

  In recent years, EEPROM and flash EEPROM have attracted attention as nonvolatile memories that can be electrically written and erased. In these memory devices, it is necessary to apply a high voltage of 10 V or more to the memory cell at the time of data writing or erasing. This high voltage is supplied from an external power source or generated by an internal booster circuit. To be supplied.

  At that time, a high breakdown voltage MOS transistor is used for the booster circuit and the high voltage transmission circuit. This high breakdown voltage MOS transistor not only requires a drain junction breakdown voltage higher than the high voltage to be used, but also a drain / gate. Even with respect to the bipolar action that occurs when a high voltage is applied simultaneously, a withstand voltage higher than the high voltage used is required. Usually, such a high voltage MOS transistor as shown in FIG. 14 is known (for example, Patent Document 1).

  The structure of this high voltage MOS transistor is as follows. That is, the STI element isolation films 105 and 106 are formed in the P-type silicon substrate 101, and the gate oxide film 111 and the gate electrode 112 thereon are disposed on the surface of the P-type silicon substrate 101. Further, sidewalls 130 made of an insulating film are formed on the side surfaces of the gate electrode 112 and the gate oxide film 111, and an N-type is formed in the P-type silicon substrate 101 on one side (left side in the drawing) of the gate electrode 112. A source region composed of the low impurity concentration region 115 and the N-type high impurity concentration region 120 is formed. Also, a drain region composed of an N-type low impurity concentration region 114 and an N-type high impurity concentration region 118 is formed in the P-type silicon substrate 101 opposite to the source region across the gate electrode 112. Has been. However, in the drain region, the N-type high impurity concentration region 118 is disposed away from the gate electrode 112 by the length of the offset 121. Reference numerals 113 and 116 denote N-type low impurity concentration regions. Part of the surfaces of the high impurity concentration regions 118 and 120 and part of the upper surface of the gate electrode 112 are silicided as a Ti silicide film 123. By this silicidation, the source and drain contact resistances and the gate electrode wiring resistance and contact resistance are reduced, and the high voltage MOS transistor can operate at high speed. Then, the surface of the P-type silicon substrate 101 is covered with a silicon oxide film 124 as an interlayer insulating film, a contact hole is opened in the silicon oxide film 124, and an N-type is used as a contact electrode for the source and drain in the contact hole. AL wirings 125 and 126 are arranged on the Ti silicide film 123 formed on the surfaces of the high impurity concentration regions 118 and 120. Note that a contact hole and a contact electrode are also provided for the gate electrode 112, but illustration thereof is omitted in FIG.

  By adopting the above configuration, when a high voltage is applied to the drain, a large depletion layer is generated in the low impurity region 114 in the offset 121 portion at the drain junction near the gate electrode 112, and therefore, in the vicinity of the gate oxide film 111. The electric field concentration at the drain junction can be weakened. As a result, bipolar action between the source and drain can be prevented, and a high voltage MOS transistor with excellent voltage resistance can be obtained.

Next, a method for manufacturing the above-described high voltage MOS transistor will be described with reference to FIGS.
First, as shown in FIG. 9, STI element isolation films 105 and 106 made of a silicon oxide film are formed on the surface of a P-type silicon substrate 101. Next, after the surface of the P-type silicon substrate 101 is thermally oxidized to form a silicon oxide film 109, a polysilicon film 110 is deposited by a CVD method. Thereafter, P + ions are implanted into the polysilicon film 110 to reduce the electrical resistance of the polysilicon film 110.

  As long as the electrical resistance of the polysilicon film 110 is reduced, the same effect can be obtained by using a phosphorus-doped polysilicon film instead of implanting P + ions. However, normally, for the purpose of high-speed operation, the polysilicon gate electrode of the N-channel MOS transistor is doped N-type, and the polysilicon gate electrode of the P-channel MOS transistor is doped P-type. Therefore, in the CMOS process in which an N-type MOS transistor and a P-type MOS transistor are formed on the same substrate at the same time, the gate electrode has a low electrical resistance by an ion doping method that can make the polysilicon gate electrode separately N-type and P-type. Is most effective.

  In the present specification, an N-channel high voltage MOS transistor will be described hereinafter. However, a P-channel high voltage MOS transistor is also premised on a CMOS process that is simultaneously formed on a P-type silicon substrate 101.

  Next, the silicon oxide film 109 and the polysilicon film 110 are patterned using a lithography method and an anisotropic dry etching technique to form a gate oxide film 111 and a gate electrode 112 as shown in FIG. Further, P + ions are implanted into the P-type silicon substrate 101 using the gate electrode 112 and the gate oxide film 111 as a mask to form N-type low impurity concentration regions 113, 114, 115, and 116.

  Next, as shown in FIG. 11, a silicon oxide film is deposited on the surface of a P-type silicon substrate 101 using a CVD method, and then the deposited silicon oxide film is removed by etching using an anisotropic dry etching technique. Thus, sidewalls 130 made of a silicon oxide film are formed on the side surfaces of the gate electrode 112 and the gate oxide film 111.

  Next, a photoresist 117 is patterned on the P-type silicon substrate 101, and As + ions are implanted to form N-type high impurity concentration regions 118 and 120. At this time, in order to form the offset 121, patterning is performed so that a part of the photoresist 117 overlaps with the gate electrode 112 and the remaining part overlaps with the low impurity concentration region 114 as shown in the center of the figure. As + ions are implanted. As a result, the low impurity concentration region 114 is arranged on the surface of the P-type silicon substrate 101 between one end of the gate electrode 112 and the high impurity concentration region 118.

  Next, as shown in FIG. 12, a silicon oxide film 122 is entirely deposited on the surface of the P-type silicon substrate 101 by a CVD method, and then high impurity concentration regions 118 and 120 in the silicon oxide film 122 are formed. The portion on the surface of the gate electrode 112 is selectively removed by etching to obtain the state shown in the figure. The remaining silicon oxide film 122 serves as a mask for silicidation.

  Next, as shown in FIG. 13, ions for promoting silicide, for example, As + ions, are implanted with low energy using the silicon oxide film 122 as a mask, and the high impurity concentration regions 118 and 120 not covered with the silicon oxide film 122 are formed. And a part of the surface of the gate electrode 112 are made amorphous. This amorphization facilitates the formation of silicide. Next, after depositing a refractory metal, for example, Ti, heat treatment is performed at a high temperature above the eutectic point, so that single crystal silicon constituting the high impurity concentration regions 118 and 120 and polysilicon constituting the gate electrode 112 and Ti are made. By reacting, a Ti silicide film 123 is formed.

Next, as shown in FIG. 14, after removing unreacted Ti and silicon oxide film 122, a silicon oxide film 124 is deposited as an interlayer insulating film by a CVD method, and contact holes are formed on the high impurity concentration regions 118 and 120. Are formed, and AL wirings 125 and 126 are formed to form contact electrodes to the source and drain. Note that a contact electrode is also formed on the gate electrode 112.
JP-A-9-266255

  However, the conventional high voltage MOS transistor and the manufacturing method thereof as described above have a problem that the length of the offset 121 is likely to vary, and as a result, the characteristics of the high voltage MOS transistor vary.

  This is because the length of the offset 121 is affected by an error in patterning the photoresist 117. That is, dimensional errors and patterning alignment errors can be considered as errors during patterning of the photoresist 117. The length of the offset 121 is determined by the distance from the end of the gate electrode 112 to the end of the photoresist 117 opposite to the gate electrode 112. For example, even if the alignment error of the photoresist 117 is zero, When the dimension is patterned to be smaller than the design value, the length of the offset 121 is shortened. Conversely, even if the dimensional error of the photoresist 117 is zero, if the alignment error occurs and the center position of the photoresist 117 is shifted to the gate electrode 112 side, the length of the offset 121 is also shortened. .

  In patterning a photoresist, a dimensional error and an alignment error always occur. In manufacturing a semiconductor device, these two errors are taken into consideration, and the length of each part is determined so that the semiconductor device operates even if an error occurs within a certain range.

  In the case of a high breakdown voltage MOS transistor, it is necessary to secure an offset 121 having a certain length or more in order to ensure a breakdown voltage. However, if the offset 121 is made longer than necessary, the drain current becomes small. This is because the offset portion is made of a low-concentration diffusion layer and thus becomes electrically high resistance. Therefore, it is necessary to increase the gate width in order to ensure a predetermined drain current, but this will hinder the miniaturization of the element.

  From this point of view, it is desirable that the length of the offset 121 is a minimum length that can ensure a breakdown voltage. However, as described above, in the conventional high breakdown voltage MOS transistor and its manufacturing method, Considering two error components at the time of patterning, it is unavoidable to set a longer setting with a margin. In order to compensate for the drain current that is reduced by this, it is necessary to set the width of the gate electrode 112 longer than necessary, and as a result, miniaturization is sacrificed.

Another problem is that the number of processes increases because of the low electrical resistance of the gate electrode 112 made of polysilicon.
When polysilicon is used as the gate electrode, the electrical resistance is usually high as it is, and this hinders the operation of the circuit. Therefore, N-type or P-type impurities are doped into the polysilicon to reduce the electrical resistance. Impurity doping means for reducing electrical resistance include the use of phosphorus-doped polysilicon in which phosphorus is simultaneously doped when depositing polysilicon by CVD, and the doping of impurities by ion implantation after polysilicon deposition. It is common to use any one of the methods. As described in the description in the background section above, doping by ion implantation makes it easy to control the implantation amount, and N-type and P-type doping can be applied to the gates of the N-channel MOS transistor and the P-channel MOS transistor. Since it can be divided into gates, it is an indispensable technique for manufacturing CMOS semiconductor devices. Further, the number of processes can be reduced by implanting the gate simultaneously with the source and drain.

  However, according to the above-described conventional method for manufacturing a high voltage MOS transistor, the gate electrode 112 made of polysilicon is exposed to photo at the time of As + ion implantation for forming the high impurity concentration regions 120 and 118 for the source and drain shown in FIG. Since it is partially covered by the resist 117, As + ions are only implanted into a part of the gate electrode 112. For this reason, the As + ion implantation of FIG. 11 does not sufficiently dope the gate electrode 112, so that, for example, P + ions are implanted immediately after the polysilicon film 110 is deposited as shown in FIG. This has led to an increase in the number of processes.

  Further, the conventional high voltage MOS transistor and its manufacturing method have a problem that it is difficult to increase the speed by silicidation. In order to increase the speed by silicidation, it is desirable that the entire upper surface of the gate electrode 112 be silicided in order to further reduce the electrical resistance of the gate electrode 112. However, if the surface of the low impurity concentration region 114 in the offset 121 region is silicided, it is electrically short-circuited with the high impurity concentration region 118, and the meaning of providing the offset 121 is lost.

  Therefore, as shown in FIG. 13, it is necessary to cover the portion of the offset 121 with the silicon oxide film 122 for silicidation to avoid silicidation. However, for that purpose, the silicon oxide film 122 must be formed so as to partially overlap the gate electrode 112 in consideration of the alignment margin at the time of lithography. There is a problem that it is difficult to realize a high voltage MOS transistor capable of high-speed operation because only the portion is not silicided and the electric resistance is not sufficiently reduced.

  The present invention has been made to solve the above-described problems, and can form a drain offset of a high-breakdown-voltage MOS transistor with high accuracy, and can sufficiently minimize a decrease in drain current while ensuring a sufficient breakdown voltage. Furthermore, impurity doping for reducing the electrical resistance of the gate electrode made of polysilicon can be performed without increasing the number of steps, and further, the entire surface of the gate electrode can be silicided during silicidation, resulting in higher speed operation. The present invention provides a high-breakdown-voltage MOS transistor and a method for manufacturing the same.

  In order to solve the above problems, according to the semiconductor device of the present invention, in the MOS transistor formed on the first conductivity type semiconductor substrate, the drain of the MOS transistor is close to the gate electrode of the MOS transistor. In order from the side, the MOS transistor includes a first conductivity type first high concentration diffusion layer, a second conductivity type first low concentration diffusion layer, and a second conductivity type second high concentration diffusion layer, The contact connecting the drain of the type transistor and the outside is formed on the second high-concentration diffusion layer.

  According to the present invention, in the semiconductor device, the drain of the MOS transistor is further connected between the gate electrode of the MOS transistor and the first high-concentration diffusion layer of the second conductivity type. It can be set as the structure provided with 2 low concentration diffusion layers.

According to the present invention, in the semiconductor device, it is preferable that at least one of the first or second high-concentration diffusion layers is partially silicided or entirely silicided.
According to the present invention, in the semiconductor device, the entire upper surface of the gate electrode of the MOS transistor is preferably silicided.

  According to the present invention, in the semiconductor device, the source of the MOS transistor preferably has a symmetrical structure with the drain of the MOS transistor across the gate electrode of the MOS transistor.

  According to a first method of manufacturing a semiconductor device of the present invention, a method of manufacturing a semiconductor device in which a MOS transistor is formed on a first conductivity type semiconductor substrate forms a gate insulating film on the surface of the first conductivity type semiconductor substrate. A step of forming a gate electrode on the gate insulating film, and implanting a first conductivity type second impurity into the semiconductor substrate using the gate electrode as a mask, thereby reducing the concentration in the semiconductor substrate. A step of forming a diffusion layer; a step of forming a mask at a position spaced from the gate electrode on the surface of the semiconductor substrate; and a second impurity of a second conductivity type on the semiconductor substrate on which the mask is formed. The first high-concentration diffusion layer, the first low-concentration diffusion layer, and the second high-concentration diffusion are implanted into the surface of the semiconductor substrate adjacent to the gate electrode in order from the side close to the gate electrode. Layer and Example was, and forming a drain, characterized in that it comprises a step of forming a contact for connecting the drain and the outside to the second high-concentration diffusion layer.

  According to a second method of manufacturing a semiconductor device of the present invention, a method of manufacturing a semiconductor device in which a MOS transistor is formed on a first conductivity type semiconductor substrate forms a gate insulating film on the surface of the first conductivity type semiconductor substrate. A step of forming a gate electrode on the gate insulating film, and implanting a first conductivity type second impurity into the semiconductor substrate using the gate electrode as a mask, thereby reducing the concentration in the semiconductor substrate. A step of forming a diffusion layer, a step of forming sidewalls made of an insulating film on both sides of the gate electrode, a step of forming a mask at a position apart from the sidewalls on the surface of the semiconductor substrate, and the mask A second impurity of a second conductivity type is implanted into the semiconductor substrate on which the gate electrode is formed, and the surface of the semiconductor substrate adjacent to the gate electrode is introduced from the side close to the gate electrode. Forming a drain comprising a second low-concentration diffusion layer, a first high-concentration diffusion layer, a first low-concentration diffusion layer, and a second high-concentration diffusion layer; Forming a contact for connecting to the outside on the second high-concentration diffusion layer.

  According to the present invention, in the first or second method of manufacturing a semiconductor device, a part or the entire surface of at least one of the first or second high-concentration diffusion layers is formed before the contact forming step. Is preferably silicided.

  According to the present invention, in the semiconductor device manufacturing method, it is preferable that the entire upper surface of the gate electrode is silicided before the step of forming the contact.

  According to the semiconductor device and the manufacturing method thereof of the present invention, since the alignment error can be eliminated among the two errors of the dimensional error and the alignment error that are generated when the implantation mask is formed by lithography, a more accurate dimension can be obtained. Thus, an offset can be formed, and as a result, a high voltage MOS transistor having stable characteristics can be realized. In addition, since there is no need to cover the gate electrode made of polysilicon with an implantation mask at the time of source / drain implantation, a sufficient amount of impurities can be introduced into the gate electrode simultaneously with the source / drain implantation. It is possible to realize resistance and reduce the number of processes at the same time. Furthermore, when siliciding the high voltage MOS transistor, the gate electrode surface can be silicidized over the entire surface, so that a high voltage MOS transistor capable of higher speed operation can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 7 are sectional views in order of steps showing a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.

  The manufacturing method will be described. First, as shown in FIG. 1, after forming STI element isolation films 5 and 6 made of silicon oxide in a P-type silicon substrate 1, the surface of the P-type silicon substrate 1 is thermally oxidized. A silicon oxide film 9 having a thickness of about 20 nm is formed, and a polysilicon film 10 is further deposited by a CVD method to a thickness of about 200 nm.

Next, the silicon oxide film 9 and the polysilicon film 10 are patterned by using a photolithography technique and a dry etching technique. Then, as shown in FIG. 2, a part of the patterned silicon oxide film 9 becomes the gate oxide film 11 of the high voltage MOS transistor, and a part of the polysilicon film 10 becomes the gate electrode 12. Next, using the gate electrode 12 and the gate oxide film 11 as a mask, for example, P + ions are implanted from the surface of the P-type silicon substrate 1 under the conditions of 70 keV and 1 × 10 ¹³ cm ⁻² . The implanted P + ions form N-type low impurity concentration regions 13, 14, 15, and 16.

Next, as shown in FIG. 3, a silicon oxide film having a thickness of about 100 nm is deposited on the surface of the P-type silicon substrate 1 using the CVD method, and then etched away using an anisotropic dry etching technique. Thus, sidewalls 30 made of a silicon oxide film are formed on the side surfaces of the gate electrode 12 and the gate oxide film 11. The sidewalls 30 are formed so as to cover portions of the N-type low impurity concentration regions 14 and 15 that are close to the gate electrode 12. Next, a photoresist 17 is patterned on the surface of the P-type silicon substrate 1. At this time, as shown in the figure, the photoresist 17 is patterned at a position spaced from the sidewall 20 on the drain side. Further, the patterning dimension is set equal to the offset 21. Thereafter, As + ions are implanted under conditions of, for example, 40 keV and 1 × 10 ¹⁵ cm ⁻² to form N-type high impurity concentration regions 18, 19, and 20. The high impurity concentration regions 19 and 20 are formed at positions separated from the gate electrode 12 by the portions of the N-type low impurity concentration regions 14 and 15 corresponding to the thickness of the sidewall 30. The N-type high impurity concentration region 20 and the N-type low impurity concentration region 15 collectively function as the source of the high breakdown voltage MOS transistor, and the N-type high impurity concentration regions 18 and 19 and the N-type low impurity concentration region. Together with the region 14, it functions as the drain of the high voltage MOS transistor.

  Also, As + ions are implanted into the gate electrode 12 simultaneously with the surface of the P-type silicon substrate 1, and the electrical resistance of the gate electrode 12 is simultaneously reduced. Therefore, unlike the conventional example described with reference to FIGS. 8 to 13, it is not necessary to perform impurity doping to the gate electrode in a separate process, and the number of processes can be reduced.

Thereafter, as shown in FIG. 4, the photoresist 17 is removed.
Here, the feature of the present invention is that the photoresist 17 is patterned at a position separated from the sidewall 30 on the drain side as described above. Since As + ions are not implanted into the portion of the surface of the P-type silicon substrate 1 below the photoresist 17 patterned at a position away from the sidewall 30, the low impurity concentration region 14 remains as it is, and this region is offset. 21. In the present invention, the area of the offset 21 is determined only by the size of the photoresist 17.

  As described above, in the conventional high voltage MOS transistor, when forming an offset consisting of a low impurity concentration region on the drain side, the photoresist is overlapped with the gate electrode and patterned, so the length of the offset is It is affected by two error factors, resist dimensional error and alignment error.

  However, according to the present invention, the offset 21 is only affected by the dimensional error of the photoresist 17. Therefore, the length of the offset 21 can be formed with higher accuracy than in the conventional example, and therefore, a high voltage MOS transistor having stable characteristics can be manufactured.

  At this time, since the photoresist 17 is patterned at a position separated from the sidewall 30, there is a concern that the size of the high voltage MOS transistor in the channel length direction is longer than that in the conventional example, but the offset 21 can be formed with high accuracy. Therefore, since the margin of the length to be added to the offset 21 can be reduced, the increase in the size of the gate electrode 12 in the channel length direction can be made small.

  Furthermore, since the length of the offset 21 can be set shorter than that of the conventional example, the high electrical resistance component due to the low impurity concentration region 14 corresponding to the offset 21 is reduced, and it becomes easier to secure the drain current. In comparison, the size of the gate electrode 12 in the width direction can be reduced.

  Furthermore, since the high impurity concentration region 19 formed on the surface of the P-type silicon substrate 1 in the vicinity of the sidewall 30 based on forming the offset 21 at a position separated from the sidewall 30 has an extremely small electrical resistance component, Even if the structure shown in the figure is adopted, the drain current is hardly reduced, and a high voltage MOS transistor having excellent characteristics can be realized.

  Next, the silicidation process of the high voltage MOS transistor will be described with reference to FIGS. By siliciding, a high voltage MOS transistor capable of operating at higher speed can be realized.

  First, as shown in FIG. 5, after a silicon oxide film 22 is deposited on the entire surface of the P-type silicon substrate 1 to a thickness of about 80 nm by a CVD method, the high impurity concentration region 18, The silicon oxide film 22 is patterned so that a part or the whole of the upper surfaces of 19 and 20 and the surfaces of the gate electrode 12 and the sidewalls 30 are opened. The patterned silicon oxide film 22 becomes a mask for silicidation.

Next, As + ions for promoting silicidation are implanted under the conditions of, for example, 25 keV and 1 × 10 ¹⁴ cm ^{−2 using} the silicon oxide film 22 as a mask. As a result, the regions near the surface of the gate electrode 12 and the high impurity concentration regions 18, 19 and 20 are made amorphous and silicide is easily formed. Next, after depositing a refractory metal, for example, Ti with a thickness of about 50 nm, heat treatment is performed at 650 ° C. for 30 minutes, and polysilicon and high impurity concentration regions 18, 19, 20 constituting the gate electrode 12 are formed. The single crystal silicon to be formed is reacted with Ti. As a result, as shown in FIG. 6, the surface of the gate electrode 12 and part of the surface of the high impurity concentration regions 18, 19, 20 are silicided to form a Ti silicide film 23.

  By performing such silicidation, the gate electrode 12 and the high impurity concentration regions 18 and 20 can be reduced in electrical resistance, and a high voltage MOS transistor operating at higher speed can be realized.

  When the conventional high voltage MOS transistor as shown in FIG. 13 is silicided, if the surface of the low impurity concentration region 114 in the region corresponding to the offset 121 is silicided, the surface is electrically short-circuited with the high impurity concentration region 118. Since the meaning of providing the offset 121 is lost, the surface of the low impurity concentration region 114 cannot be silicided. Therefore, when siliciding a conventional high voltage MOS transistor, it is necessary to completely cover the surface of the low impurity concentration region 114 forming the offset 121 with a silicon oxide film 122 which is a silicide mask. The film 122 has to be patterned so as to overlap part or all of the surface of the gate electrode 112. As a result, a part of the surface of the gate electrode 112 is not silicided at all, and further reduction in electric resistance is insufficient, and it is difficult to increase the speed of the high voltage MOS transistor.

  However, according to the method shown in the present embodiment, since the entire surface of the gate electrode 12 can be silicided, a high voltage MOS transistor that can operate at higher speed can be realized. Furthermore, since a part of the surface of the high impurity concentration region 19 can be silicided, the high impurity concentration region 19 has a lower electrical resistance and allows a larger drain current to flow.

  Next, as shown in FIG. 7, after the unreacted Ti and the silicon oxide film 22 are removed, a silicon oxide film 24 is deposited on the surface of the P-type silicon substrate 1 to a thickness of about 800 nm. Further, contact holes are opened on the high impurity concentration regions 18 and 19, and AL wirings 25 and 26 are formed. The contact hole to the gate electrode 12 and the AL wiring are not shown in FIG.

  In the present embodiment, the structure and manufacturing method of only the N-channel type high breakdown voltage MOS transistor have been described. However, the P channel type high breakdown voltage MOS having the same structure and manufacturing method is applied to other regions on the P type silicon substrate 1. When transistors are arranged to have a CMOS structure, a wider variety of semiconductor devices can be realized.

  If a memory element such as an EEPROM or a low-voltage MOS transistor is formed on the P-type silicon substrate 1 at the same time, an efficient semiconductor device capable of operating the EEPROM or the like on a single chip can be realized.

  Further, in the present embodiment, the high voltage MOS transistor having the offset structure only in the drain region and the manufacturing method thereof have been described, but the source region may have an offset structure as well as the drain region. In this case, since the source and drain can be used interchangeably, a semiconductor device that can be used more flexibly can be realized.

  Further, in the present embodiment, an offset made of the low impurity concentration region 14 is also provided on the surface near the STI element isolation films 5 and 6, but this offset need not be provided if the element isolation characteristics are sufficiently good. In this case, the high voltage MOS transistor can be further miniaturized.

  As shown in FIG. 8, the semiconductor device having the structure in which the sidewall 30 is not formed as compared with the semiconductor device shown in FIG. 7 has the same effect as that described above. That is, in FIG. 7, the low impurity region formed below the sidewall 30 does not exist in this case, and the high concentration impurity regions 19 and 20 are adjacent to the gate electrode 12.

Regarding the manufacturing method, the semiconductor device shown in FIG. 8 can be obtained by omitting the step of forming the sidewalls 30 from the manufacturing method of the semiconductor device of FIG.
According to the configuration shown in FIG. 8, since there is no side wall forming step, a high voltage MOS transistor capable of high-precision and high-speed operation can be obtained with a smaller number of steps than the semiconductor device shown in FIG.

  The semiconductor device and the manufacturing method thereof of the present invention can form the drain offset of the MOS transistor with high accuracy and enable high-speed operation, and are effective as a high breakdown voltage MOS transistor and a manufacturing method thereof.

Sectional drawing which shows the manufacturing method of the semiconductor memory device based on embodiment of this invention Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the structure of the semiconductor memory device based on the next process of FIG. 6, and embodiment of this invention Sectional drawing which shows the structure of the semiconductor memory device based on other embodiment of this invention. Sectional drawing which shows the manufacturing method of the conventional high voltage MOS transistor Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the next process of FIG. Sectional drawing which shows the structure of the next process of FIG. 13 and the conventional high voltage MOS transistor

Explanation of symbols

1 P-type silicon substrate 11 Gate oxide film 12 Gate electrode 14 Low impurity concentration region 15 Low impurity concentration region 17 Photoresist 18 High impurity concentration region 19 High impurity concentration region 20 High impurity concentration region 21 Offset 23 Ti silicide film 25 AL wiring 26 AL wiring 30 Side wall

Claims (9)

In a MOS transistor formed on a first conductivity type semiconductor substrate,
In order from the side closer to the gate electrode of the MOS transistor, the drain of the MOS transistor has a second conductivity type first high concentration diffusion layer, a second conductivity type first low concentration diffusion layer, A second conductivity type second high-concentration diffusion layer,
A contact for connecting the drain of the MOS transistor and the outside is formed on the second high-concentration diffusion layer.   The drain of the MOS transistor further includes a second low concentration diffusion layer of the second conductivity type between the gate electrode of the MOS transistor and the first high concentration diffusion layer of the second conductivity type. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein a part or the entire surface of at least one of the first or second high-concentration diffusion layers is silicided.   4. The semiconductor device according to claim 1, wherein the entire upper surface of the gate electrode of the MOS transistor is silicided.   5. The semiconductor device according to claim 1, wherein a source of the MOS transistor has a symmetric structure with a drain of the MOS transistor across the gate electrode of the MOS transistor. A method of manufacturing a semiconductor device in which a MOS transistor is formed on a semiconductor substrate of a first conductivity type,
Forming a gate insulating film on the surface of the first conductivity type semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a low-concentration diffusion layer in the semiconductor substrate by implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask;
Forming a mask at a position separated from the gate electrode on the semiconductor substrate surface;
A second impurity of a second conductivity type is implanted into the semiconductor substrate on which the mask is formed, and a first high level is sequentially formed on the surface of the semiconductor substrate adjacent to the gate electrode from the side close to the gate electrode. Forming a drain comprising a concentration diffusion layer, a first low concentration diffusion layer, and a second high concentration diffusion layer;
Forming a contact connecting the drain and the outside on the second high-concentration diffusion layer. A method of manufacturing a semiconductor device in which a MOS transistor is formed on a semiconductor substrate of a first conductivity type,
Forming a gate insulating film on the surface of the first conductivity type semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a low-concentration diffusion layer in the semiconductor substrate by implanting a first impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask;
Forming sidewalls made of an insulating film on both sides of the gate electrode;
Forming a mask at a position separated from the sidewall on the semiconductor substrate surface;
A second impurity of a second conductivity type is implanted into the semiconductor substrate on which the mask is formed, and a second low-concentration layer is formed on the surface of the semiconductor substrate adjacent to the gate electrode in order from the side close to the gate electrode. Forming a drain comprising a concentration diffusion layer, a first high concentration diffusion layer, a first low concentration diffusion layer, and a second high concentration diffusion layer;
Forming a contact connecting the drain and the outside on the second high-concentration diffusion layer.   8. The semiconductor device according to claim 6, wherein a part or the entire surface of at least one of the first or second high-concentration diffusion layers is silicided before the step of forming a contact. Production method.   9. The method of manufacturing a semiconductor device according to claim 6, wherein the entire upper surface of the gate electrode is silicided before the step of forming the contact.

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