JP3050188B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a semiconductor device using a technique of siliciding a diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art The miniaturization and higher density of the structure of semiconductor devices are still being vigorously pursued. For miniaturization, a semiconductor element formed with a size of 0.15 μm is currently used, and a semiconductor device such as a memory device or a logic device using this size as a design standard has been put to practical use.

[0003] Such miniaturization is the most effective method for achieving high performance or multifunctionality due to high integration, high speed, etc. of a semiconductor device, and is indispensable for the manufacture of semiconductor devices in the future. With the miniaturization of such semiconductor elements, it has become necessary to make the impurity diffusion layers for forming source and drain regions extremely shallow. However, making the diffusion layer shallow leads to an increase in resistance of the source and drain regions, significantly lowering the current driving capability of an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor), and hindering the speeding up of the semiconductor device. .
In order to solve such a problem, a MOS transistor having a so-called silicide structure in which a silicide layer is selectively formed on a diffusion layer forming a source / drain and the resistance of the source / drain is extremely reduced has been used. I have.

However, in this silicide structure MOS transistor, since a diffusion layer (source / drain) resistance is small, a large current easily flows, and the semiconductor device is ESD (E)
There is a drawback that the device is susceptible to electrostatic breakdown due to electro-static discharge or the like. Therefore,
Various measures have been studied for this purpose. Among them, as shown in, for example, JP-A-7-106567, it is necessary to provide a region where a silicide layer is not formed in a diffusion layer of a source / drain region of an input / output unit MOS transistor of a semiconductor integrated circuit. . A method of manufacturing such a conventional semiconductor device will be described with reference to FIG.
Here, FIG. 6 is a sectional view in the order of the manufacturing process of the MOS transistor.

[0005] As shown in FIG.
Element isolation insulating film 102 is selectively formed on 1. Next, the polysilicon gate 1 is interposed via the gate insulating film 103.
04, a sidewall insulating film 105 made of an insulating film such as a silicon oxide film, and an LDD (Lightly Dop).
(drain) structure of the drain region 106 with a diffusion layer.
And source region 107 are formed. Then, a titanium film 108 is deposited on the entire surface of the semiconductor substrate 101.

Next, a resist film 109 is applied and patterned on the entire surface by photolithography. Then, the titanium film 108 is dry-etched using the patterned resist film as a mask. By this dry etching, as shown in FIG.
On the source region 107 and the polysilicon gate 10
Titanium films 110, 111 and 112 are formed by patterning on the drain and source regions adjacent to the fourth and polycrystalline silicon gates 104.

Next, the resist film 109 is removed. Then, a silicidation reaction between the titanium films 110, 111, and 112 and the underlying silicon is performed by the heat treatment.
As shown in (c), the titanium silicide films 113, 11
4, 115, 116 and 117 are formed. Hereinafter, although not shown, an interlayer insulating film is formed on the entire surface, and a metal wiring connected to the titanium silicide film 116 or 117 through the contact hole is provided.

In this manner, as shown in FIG. 6C, a diffusion resistance layer 118 is formed between the titanium silicide films 116 and 114. Similarly, the titanium silicide film 11
The diffusion resistance layer 119 is also formed between 7 and 115. Then, even if a high voltage such as a surge is applied to the titanium silicide film 116 or 117 through the metal wiring, the MOS transistor is protected from the electrostatic breakdown by the diffusion resistance layers 118 and 119.

[0009]

In the above conventional technique, the resist film 1 formed in the photolithography process is used.
09 is used as a mask for dry etching and the titanium film 1
08 is patterned. Then, the patterned titanium films 110, 111, 112 and the like are silicided and separated from each other by titanium silicide films 114 and 116.
Is formed in the drain region 106. The diffusion resistance layer 1 is provided between the titanium silicide films 114 and 116.
18 are formed. Alternatively, similarly, the titanium silicide films 115 and 117 which are separated from each other are formed in the source region 107.
These titanium silicide films 115 and 1
17, a diffusion resistance layer 119 is formed.

However, with the miniaturization of the MOS transistor, the dimensions between the titanium silicide films 114 and 116 are miniaturized. For this reason, a photolithography process that requires the formation of a fine pattern is newly required, which complicates the manufacturing process and increases the manufacturing cost of the semiconductor device.

Further, when the titanium silicide film in the source / drain region is separated through the photolithography process as in the prior art, variations are inevitable due to alignment in the photolithography process. That is,
The width of the titanium silicide film 114 or 115 varies. Then, the driving capability of the MOS transistor varies. Such variation is M
As OS transistors become smaller, a more serious problem arises.

Therefore, it is difficult for this conventional method to cope with miniaturization of a semiconductor element such as a MOS transistor.

It is an object of the present invention to provide a semiconductor device which solves all of the above-mentioned problems, has a source and a drain which are silicidized, has excellent electrostatic breakdown resistance, and can cope with miniaturization by a simple method, and a method of manufacturing the same. Is to do.

[0014]

For this purpose, in a semiconductor device according to the present invention, in a MOS transistor in which a silicide layer is formed on a partial surface of a diffusion layer constituting a source / drain, a side wall of a gate electrode of the MOS transistor A first sidewall insulating film and a second sidewall insulating film are laminated, and a silicide layer is formed on the diffusion layer located below the first and second sidewall insulating films. Not formed. Here, the above
2 is located below the sidewall insulating film and has a drain
The impurity concentration of only the formed diffusion layer is lower than that of the silicide layer.
Lower than the impurity concentration of the diffusion layer in the
Is set.

Alternatively, in a semiconductor integrated circuit composed of MOS transistors, a MOS
A first sidewall insulating film is formed on a sidewall of a gate electrode of the transistor, and a first sidewall insulating film and a second sidewall made of different materials are formed on sidewalls of a gate electrode of a MOS transistor forming an input / output circuit. And a sidewall insulating film.

Here, the MOS constituting the internal circuit described above
The width of the first side wall insulating film formed on the side wall of the gate electrode of the transistor is larger than the width of the first side wall insulating film formed on the side wall of the gate electrode of the MOS transistor constituting the input / output circuit. It is getting smaller.

Further, a silicide layer is formed on the surface of the diffusion layer constituting the source / drain of the MOS transistor. The impurity concentration of the diffusion layer located below the second sidewall insulating film is set to be lower than the impurity concentration of the diffusion layer in the region where the silicide layer is formed. Alternatively, the impurity concentration of only the diffusion layer located below the second sidewall insulating film and constituting the drain is set to be lower than the impurity concentration of the diffusion layer in the region where the silicide layer is formed. .

[0018]

[0019] Then, a method of manufacturing a semiconductor device of the present invention includes the steps of forming on a semiconductor substrate a gate electrode of the MOS transistor through the gate insulating film, a first one conductivity type impurity of the gate electrode of the above mask Forming a first diffusion layer of one conductivity type serving as a source / drain by performing ion implantation, and forming a first sidewall insulating film on a side wall of the gate electrode after forming the first diffusion layer. Forming a diffusion resistance layer of the same conductivity type by adding a third ion implantation of an impurity of the opposite conductivity type using the gate electrode and the first sidewall insulating film as a mask. Forming a second sidewall insulating film on the first sidewall insulating film after forming the diffusion resistance layer; and forming a gate electrode, a first sidewall insulating film, and a second sidewall insulating film on the first sidewall insulating film. Forming a second diffusion layer and a second ion implantation of the same conductivity type impurity film as a mask of the same conductivity type as the source and drain, a silicide layer is formed on the second diffusion layer surface And a process.

Here, the first side wall insulating film is formed of a silicon oxynitride film, and the second side wall insulating film is formed of a silicon oxide film.

The first sidewall insulating film and the second sidewall insulating film are formed by anisotropic dry etching of the entire surface after the formation of the insulating film. For this,
The second sidewall insulating film is formed without passing through the photolithography process. Then, the diffusion resistance layer provided in the region located below the second sidewall insulating film is formed in a self-aligned (self-aligned) manner. For this reason, the source and the drain are silicided, and the miniaturization of the MOS transistor excellent in the electrostatic breakdown resistance becomes easy.

[0022]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a MOS transistor formed in an input / output circuit portion for describing an embodiment of the present invention. FIG. 2 is a cross-sectional view of a MOS transistor formed in an internal circuit portion for describing an embodiment of the present invention.

The MOS transistors in the input / output circuit are shown in FIG.
It has a structure as shown in FIG. That is, as shown in FIG. 1, a field oxide film 2 is selectively formed on a silicon substrate 1 having a P-type conductivity. The gate electrode 4 and the upper insulating film 5 are formed on the silicon substrate 1 with the gate insulating film 3 interposed therebetween.

A first sidewall insulating film 6 made of an insulating film such as a silicon oxide film is formed on the side walls of the gate electrode 4 and the upper insulating film 5. An N-type low-concentration diffusion layer 7 is formed on the surface of the silicon substrate 1 located below the first sidewall insulating film 6.

Then, a second side wall insulating film 8 is formed so as to overlap the side wall of the first side wall insulating film 6. Here, the material of the second sidewall insulating film 8 is different from that of the first sidewall insulating film 6. For example, it is composed of a silicon oxynitride (SiON) film.

Then, as shown in FIG. 1, an N-type high-concentration diffusion layer 9 is formed.
A diffusion layer having a D structure is formed. Furthermore, the second
A silicide layer 10 is formed on the surface of the N-type high-concentration diffusion layer 9 except for the N-type high-concentration diffusion layer 9 located below the sidewall insulating film 8. Here, this silicide layer 1
0 is made of, for example, titanium silicide.

Thus, the diffusion resistance layer 11 is formed in a self-aligned manner on the N-type high-concentration diffusion layer 9 located below the second sidewall insulating film 8.

Then, a silicon oxide film is deposited on the entire surface to form an interlayer insulating film 12, and an electrode 13 connected to the silicide layer 10 through a contact hole provided in the interlayer insulating film 12 is formed. MO of input / output circuit
The S transistor has the above structure.

On the other hand, the MOS transistor in the internal circuit has a structure as shown in FIG. That is, as shown in FIG.
A field oxide film 2 is formed thereon. On the silicon substrate 1, a gate insulating film 3, a gate electrode 4, and an upper insulating film 5 are formed by lamination.

Then, similarly to the input / output circuit section, a first sidewall insulating film 6a made of an insulating film such as a silicon oxide film is formed on the side walls of the gate electrode 4 and the upper insulating film 5. Here, the first sidewall insulating film 6a
Is smaller than the width of the first sidewall insulating film 6 of the MOS transistor in the input / output circuit section described with reference to FIG. An N-type low-concentration diffusion layer 7a is formed on the surface of the silicon substrate 1 located below such a first sidewall insulating film 6a. Similarly, the N-type low concentration diffusion layer 7a
Is narrower than the width of the N-type low-concentration diffusion layer 7 of the MOS transistor in the input / output circuit section described with reference to FIG.

Then, as shown in FIG. 2, an N-type high-concentration diffusion layer 9 is formed.
A diffusion layer having a DD structure is formed. Furthermore, N
Silicide layer 10 is formed on the surface of high-concentration diffusion layer 9. Here, the silicide layer 10 is made of, for example, titanium silicide.

A silicon oxide film is deposited on the entire surface to form an interlayer insulating film 12, and an electrode 13 connected to the silicide layer 10 through a contact hole provided in the interlayer insulating film 12 is formed. The MOS transistor in the internal circuit has the above structure.

In the embodiment of the present invention, the first
The SiON film is used for the sidewall insulating film of
A silicon oxide film may be used as the sidewall insulating film.

Next, a method of manufacturing the above MOS transistor will be described with reference to FIGS. FIG. 3 is a sectional view of a MOS transistor constituting an input / output circuit of a semiconductor device in the order of manufacturing steps. FIG. 4 is a sectional view of a MOS transistor which forms an internal circuit in the same manufacturing process in the order of steps. Hereinafter, the same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.

In the input / output circuit portion, first, as shown in FIG. 3A, a field oxide film 2 is selectively formed on the surface of a silicon substrate 1 in the same manner as in the prior art. Then, a gate insulating film 3 of a 10 nm-thickness silicon oxide film is formed on the silicon substrate 1. And a film thickness of 300
about 200 nm thick tungsten polycide film
The silicon oxide film is patterned to a degree, and the gate electrode 4 and the upper insulating film 5 are formed by lamination.

Next, ion implantation of phosphorus impurities or arsenic impurities is performed on the entire surface, and heat treatment is performed. Here, the implantation energy is 50 keV and the dose is set to about 10 ¹³ ions / cm ² . Then, an N-type low concentration diffusion layer 7 is formed on the field oxide film 2, the gate electrode 4 and the upper insulating film 5 in a self-aligned manner. here,
The depth of the N-type low concentration diffusion layer 7 is set to be 0.1 μm or less.

Next, a first insulating film 14 is deposited on the entire surface with silicon oxynitride having a thickness of about 150 nm. Then, ion implantation of arsenic impurities is performed on the entire surface, and heat treatment is performed. Here, the implantation energy is 300 ke
V and the dose is set to about 10 ¹⁵ ions / cm ² . Then, an N-type high concentration diffusion layer 9 is formed.

Further, as shown in FIG. 3B, a second insulating film 15 is formed on the first insulating film 14 by lamination. The second insulating film 15 is an insulating material different from that of the first insulating film 14, and is formed of a silicon oxide film having a thickness of about 150 nm. Then, a resist mask 16 is formed on the second insulating film 15. This resist mask 16
Is an MO that constitutes an input / output circuit of a semiconductor device.
It is formed so as to cover the entire S transistor. For this reason, the pattern of the resist mask 16 is very large, and high alignment accuracy in the photolithography process is not required.

The resist mask 16 is used as an etching mask, and as described later, the second insulating film 15 on the MOS transistor of the internal circuit is removed by etching.

Next, the resist mask 16 is removed by a known method. Thus, a state as shown in FIG. 3C is obtained.

Next, reactive ion etching (RIE)
Thereby, the second insulating film 15 is anisotropically etched.
That is, etch back is performed. Here, a mixed gas of C ₄ F ₈ and CO is used as a reaction gas for the etch back. The reaction gas first etches back the second insulating film 15 to form a second sidewall insulating film 8a as shown in FIG. Continue, CHF
Anisotropic dry etching is performed again with a mixed gas of ₃ and CO, and the first insulating film 14 is etched back this time.
Then, as shown in FIG. 3D, a first sidewall insulating film 6b is formed on the side walls of the gate electrode 4 and the upper insulating film 5.

Next, a titanium film having a thickness of about 30 nm is deposited on the entire surface by sputtering, and a heat treatment is performed at about 800 ° C. to cause a thermal reaction between the titanium film and the silicon substrate to form an N-type high concentration diffusion layer. 9, a silicide layer 10 is formed on the surface.
Here, the unreacted titanium film on the insulating film is removed with a chemical solution. This chemical solution is a mixed solution of aqueous ammonia, aqueous hydrogen peroxide and pure water.

On the other hand, in the internal circuit portion, the resist mask 16 is removed in the step described with reference to FIG. 3B in the input / output circuit portion, and does not exist in this region. That is, FIG.
After the step (a), a second insulating film 15 is formed on the first insulating film 14 as shown in FIG.

Next, the input / output circuit portion is used as an etching mask with the resist mask 16 so that the second insulating film 15 on the MOS transistor of the internal circuit is removed by etching. In this way, as shown in FIG. 4B, the first insulating film 14 is exposed.

Next, as described above, the second insulating film 15 shown in FIG. 3C is anisotropically etched. Here, a mixed gas of C ₄ F ₈ and CO is used as a reaction gas for the etch back. For this reason, the first insulating film 14 exposed in FIG. 4B is hardly etched.
Then, the exposed first insulating film 14 is etched back by the above-described anisotropic dry etching using the mixed gas of CHF ₃ and CO. Thus, as shown in FIG. 4C, the first sidewall insulating film 6a is formed on the side walls of the gate electrode 4 and the upper insulating film 5.

Thereafter, a silicide layer 10 is formed on the surface of the N-type high concentration diffusion layer 9 in the same manner as described with reference to FIG.

Thereafter, a silicon oxide film is deposited on the entire surface by a chemical vapor deposition (CVD) method, the interlayer insulating film described with reference to FIGS. 1 and 2 is formed, and electrodes are formed. Thus, a MOS transistor having the same structure as that described above is formed.

That is, M of the input / output circuit portion of the semiconductor device
A first sidewall insulating film 6b and a second sidewall insulating film 8a are formed by stacking on the side wall of the gate electrode of the OS transistor. Then, only the first sidewall insulating film 6a is formed on the side wall of the gate electrode of the MOS transistor in the internal circuit portion of the semiconductor device. Moreover, the width of the first sidewall insulating film 6a is smaller than the width of the first sidewall insulating film 6b.

As described above, in the MOS transistor of the input / output circuit portion of the semiconductor device, the silicide layer 10 is not formed in the N-type high concentration diffusion layer 9 located below the second sidewall insulating film 8. This region becomes a diffusion resistance layer. For this reason, the MO of the input / output circuit section of the semiconductor device is
The S transistor is resistant to ESD caused by the above-described surge or the like.

In the MOS transistor in the internal circuit portion of the semiconductor device, only the narrow first sidewall insulating film 6a is formed on the side wall of the gate electrode. And N
A silicide layer is formed on high concentration diffusion layer 9. For this reason, the operation speed of the MOS transistor in the internal circuit portion of the semiconductor device is greatly improved.

As described above, according to the present invention, a semiconductor device which is strong against ESD and has a high operation speed can be easily obtained.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a cross-sectional view of a MOS transistor formed in an input / output circuit unit for describing an embodiment of the present invention. The second embodiment differs from the first embodiment in that another diffusion resistance layer is formed on the surface of the silicon substrate located below the second sidewall insulating film. Hereinafter, the same components are denoted by the same reference numerals.

As shown in FIG. 5, a field oxide film 2 is formed on a P-type silicon substrate 1 as in the first embodiment. The gate electrode 4 and the upper insulating film 5 are formed on the silicon substrate 1 with the gate insulating film 3 interposed therebetween. Then, a first sidewall insulating film 6 is formed on the side walls of the gate electrode 4 and the upper insulating film 5. An N-type low-concentration diffusion layer 7 is formed on the surface of the silicon substrate 1 located below the first sidewall insulating film 6.

Then, the second sidewall insulating film 8 is overlapped with the side wall of the first sidewall insulating film 6.
Are formed. Further, the N-type high-concentration diffusion layer 9 is formed, and the N-type low-concentration diffusion layer 7 forms a diffusion layer having an LDD structure.

Then, a diffusion resistance layer 11 a is formed on the surface of the silicon substrate 1 located below the second sidewall insulating film 8.
Are formed. Here, the impurity concentration of the diffusion resistance layer 11a is lower than that of the N-type high concentration diffusion layer 9.
For this reason, the resistance value of the diffusion resistance layer 11a becomes higher than in the case of the first embodiment.

Thus, a silicide layer 10 is further formed on the surface of N-type high concentration diffusion layer 9. Then, an interlayer insulating film 12 is formed, and an electrode 13 connected to the silicide layer 10 is formed through a contact hole provided in the interlayer insulating film 12.

In the second embodiment, the diffusion resistance layer 11a
Is formed by forming the first insulating film 14 in the process described with reference to FIG.
Ion implantation of boron impurities of the type. And FIG.
After the second insulating film is formed in the process described in FIG. 2B, high-concentration arsenic impurities are ion-implanted. here,
The concentration of the boron impurity by ion implantation is set to be smaller than the impurity amount of the N-type low concentration diffusion layer 7, and the conductivity type of the diffusion resistance layer 11a is N-type.

In the second embodiment, the impurity concentration of the diffusion resistance layer 11a formed in the region located below the second sidewall insulating film 8 is different from the impurity concentration of the N-type high concentration diffusion layer 9. Can be controlled independently. For this reason, the resistance value of the diffusion resistance layer 11a can be set high, and the ESD
The resistance will be further improved.

In the above embodiment, the N-channel type M
The case of the OS transistor has been described. It should be noted that the present invention can be similarly formed with a P-channel type MOS transistor. In this case, the N-type may be replaced with the P-type.

Further, the first sidewall insulating film and the second
May be formed of the same kind of material.

In the embodiment of the present invention, the case where the second side wall insulating film is formed on both side walls of the gate electrode of the MOS transistor has been described.
This second sidewall insulating film may be formed on one side of the gate electrode. However, in this case, the diffusion layer located below the second sidewall insulating film becomes the drain region of the MOS transistor.

Although the silicide layer is composed of titanium silicide, the present invention is not limited to titanium silicide. It should be noted that the method of the present invention can be similarly formed with a silicide layer of a refractory metal such as cobalt or tungsten.

[0063]

As described above, according to the present invention, in a MOS transistor in which a silicide layer is formed on a partial surface of a diffusion layer forming a source / drain,
A first sidewall insulating film and a second sidewall insulating film are formed on a sidewall of a gate electrode of a transistor by lamination, and are formed on the diffusion layer located below the second sidewall insulating film. A diffusion resistance layer is formed in a self-aligned manner on the second sidewall insulating film.

Alternatively, in a semiconductor integrated circuit composed of MOS transistors, a MOS
A first sidewall insulating film is formed on a sidewall of a gate electrode of the transistor, and a first sidewall insulating film and a second sidewall made of different materials are formed on sidewalls of a gate electrode of a MOS transistor forming an input / output circuit. Is formed by laminating the sidewall insulating films.

As described above, in the present invention, a diffusion resistance layer is formed in a part of the source and drain diffusion layers of the MOS transistor in a self-aligned manner on the second sidewall insulating film.

For this reason, there is no variation due to alignment in the photolithography process, which occurs in the conventional technology. Then, there is no variation in the driving capability of the MOS transistor.

The method of the present invention facilitates miniaturization of a MOS transistor, simplifies the manufacturing process, and reduces the manufacturing cost of a semiconductor device.

According to the present invention, a low-resistance silicide layer can be formed in a diffusion layer of a MOS transistor in an internal circuit portion of a semiconductor integrated circuit, and a width of a sidewall insulating film formed on a side wall of a gate electrode is small. Become. For this reason, it is possible to easily achieve higher performance of the semiconductor device.

As described above, the fine and source
The electrostatic breakdown resistance of a semiconductor device including a MOS transistor whose drain is silicided is improved,
Such a semiconductor device can be easily formed with a high reliability and a simple method.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a MOS transistor in an input / output circuit unit for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a MOS transistor in an internal circuit section for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view of the MOS transistor of the input / output circuit section in the order of manufacturing steps.

FIG. 4 is a sectional view of a MOS transistor in the internal circuit section in the order of manufacturing steps.

FIG. 5 is a cross-sectional view of a MOS transistor in an input / output circuit unit for explaining a second embodiment of the present invention.

FIG. 6 is a sectional view illustrating a conventional technique in the order of manufacturing steps of a MOS transistor.

[Explanation of symbols]

Reference Signs List 1,101 Silicon substrate 2 Field oxide film 3,103 Gate insulating film 4 Gate electrode 5 Upper insulating film 6,6a, 6b First sidewall insulating film 7,7a N-type low concentration diffusion layer 8,8a Second side Wall insulating film 9 N-type high concentration diffusion layer 10 Silicide layer 11, 11a, 118, 119 Diffusion resistance layer 12 Interlayer insulating film 13 Electrode 14 First insulating film 15 Second insulating film 16 Resist mask 102 Element isolation insulating film 104 Polycrystalline silicon gate 105 Side wall insulating film 106 Source region 107 Drain region 108, 110, 111, 112 Titanium film 109 Resist film 113, 114, 115, 116, 117 Titanium silicide film

Claims (10)

(57) [Claims] In a semiconductor integrated circuit comprising an insulated gate field effect transistor, a first sidewall insulating film is formed on a side wall of a gate electrode of the insulated gate field effect transistor constituting an internal circuit, and an input / output circuit is provided. A first sidewall insulating film and a second sidewall insulating film made of different materials are laminated on the side wall of the gate electrode of the insulated gate field effect transistor. Semiconductor device. 2. A first electrode formed on a side wall of a gate electrode of an insulated gate field effect transistor constituting the internal circuit.
Wherein the width of the side wall insulating film is smaller than the width of the first side wall insulating film formed on the side wall of the gate electrode of the insulated gate field effect transistor constituting the input / output circuit. Item 2. The semiconductor device according to item 1 . Wherein said insulated gate field effect transistor semiconductor device according to claim 1 or claim 2, wherein the silicide layer on the portion of the surface of the diffusion layer constituting the source and drain are formed of. 4. The semiconductor device according to claim 1, wherein an impurity concentration of the diffusion layer located below the second sidewall insulating film is set to be lower than an impurity concentration of the diffusion layer in a region where the silicide layer is formed. 4. The semiconductor device according to claim 3 , wherein: 5. An impurity concentration of only a diffusion layer located under the second sidewall insulating film and constituting a drain is set to be lower than an impurity concentration of a diffusion layer in a region where the silicide layer is formed. The semiconductor device according to claim 3 , wherein: 6. A diffusion layer forming a source / drain.
Gate field effect with silicide layer formed on the surface of the part
In the transistor, the insulated gate field effect transistor
A first sidewall insulation is provided on the side wall of the gate electrode of the transistor.
The edge film and the second sidewall insulating film are formed by lamination.
Under the first and second sidewall insulating films.
No silicide layer is formed on the diffusion layer located at
In, is set such that the impurity concentration of the pure diffusion layer constituting the position to drain at the bottom of the second side wall insulating film is lower than the impurity concentration of the diffusion layer region formed of the silicide layer semi conductor arrangement you wherein a. 7. The semiconductor device according to claim 1, wherein the first sidewall insulating film is formed of a silicon oxynitride film, and the second sidewall insulating film is formed of a silicon oxide film. The semiconductor device according to claim 6. 8. A diffusion layer forming a source / drain.
Gate field effect with silicide layer formed on the surface of the part
In the transistor, the insulated gate field effect transistor
A first sidewall insulation is provided on the side wall of the gate electrode of the transistor.
The edge film and the second sidewall insulating film are formed by lamination.
Under the first and second sidewall insulating films.
No silicide layer is formed on the diffusion layer located at
In the first sidewall insulating film is made of silicon oxynitride film, the second sidewall insulating film semi-conductor device you <br/> characterized in that is composed of a silicon oxide film . 9. A step of forming a gate electrode of an insulated gate field effect transistor on a semiconductor substrate via a gate insulating film; and performing a first ion implantation of one conductivity type impurity using the gate electrode as a mask. One conductivity type to be drain
Forming a first diffusion layer of the after forming the first diffusion layer, forming a first sidewall insulation film on a sidewall of the gate electrode, the gate electrode and the first sidewall Third impurity of reverse conductivity type using insulating film as a mask
Forming a diffusion resistance layer of the same conductivity type by adding a second ion implantation, and forming a second sidewall insulation film on the first sidewall insulation film after forming the diffusion resistance layer. A second ion implantation of impurities of the same conductivity type is performed using the gate electrode, the first sidewall insulating film and the second sidewall insulating film as a mask,
A method for manufacturing a semiconductor device, comprising: a step of forming a second diffusion layer of the same conductivity type serving as a drain; and a step of forming a silicide layer on a surface of the second diffusion layer. Wherein said first sidewall insulation film is made of silicon oxynitride film, the second sidewall insulating film 請 Motomeko 9 you, characterized in that is composed of a silicon oxide film The manufacturing method of the semiconductor device described in the above.