JPH0730104A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and its manufacturing method which can reduce the dimensions of an element as well as parasitic resistances such as gate resistance, source resistance, drain resistance, and the like. CONSTITUTION:In a minute concave MOSFET, a groove opening becomes extremely narrow. This groove is normally formed by etching. After it is subjected to gate oxidation, polysilicon is deposited to fill the groove. Further, even when the entire surface of the substrate is treated with etchback, if etching conditions are to be selected, only the inside of the groove can be left with polysilicon as the electrode, and, if etching time is properly selected, the upper side of polysilicon can be made lower than the upper end of the periphery of the groove. By making the structure in this way, it is possible to form a sidewall insulating film 9 inside the groove, and with this sidewall insulating film, silicide 12 on the gate electrode 8 can be physically and electrically isolated from silicide 10 and 11 on a source electrode 3 and a drain electrode 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microminiaturized semiconductor device, and more particularly to a MOS field effect transistor (hereinafter referred to as MOS
(Referred to as FET).

[0002]

2. Description of the Related Art Miniaturization of Si MOS integrated circuits is
It is necessary to achieve both high driving force of FET and suppression of channel effect. Among these, shortening the channel length is extremely effective for increasing the driving force. However, when the channel length is close to 0.1 μm, there is a physical limit in increasing the concentration of substrate impurities, thinning the gate oxide film, and shortening the junction depth, which are used in the conventional device scaling law. Therefore, it becomes difficult to suppress the short channel effect. In particular, it is indispensable to attach a metal such as silicide to the source region and the drain region in order to reduce the parasitic resistance, which makes it extremely difficult to reduce the junction depth.

In order to overcome this difficulty, the inside of the bottom of the groove formed by etching the substrate is used as a channel region, and this channel region is formed at a position lower than the source region and the drain region. , Making the effective junction length seen from the channel shallow, so-called CONC
AVE MOSFETs have been proposed.

FIG. 5 is a vertical sectional view of a MOSFET of this type. In the same figure, the central portion of the region surrounded by the element isolation insulating film 2 on the substrate semiconductor 1 is dug down, and the source region 5 is formed on one side and the other side is formed by using the inside of the bottom as a channel region. The drain regions 6 are formed in the respective regions. The source electrode 3 is formed on the upper surface of the source region 5.
However, the drain electrode 4 is formed on the upper surface of the drain region 6 so as to ride on the element isolation insulating film 2.
A gate electrode 8 is formed inside the groove via a gate insulating film 7. Further, the interlayer insulating film 13 is laminated on the source electrode 3, the drain electrode 4 and the gate electrode 8, and
A source metal electrode 14, a drain metal electrode 15 and a gate metal electrode are provided through contact holes formed in the interlayer insulating film 13.
16 have been derived.

[0005]

The conventional M shown in FIG.
The OSFET is effective in suppressing the short channel effect because the channel region is formed at a position lower than the source region and the drain region by digging the substrate.

However, in this conventional MOSFET, since the gate electrode is formed by the lithography technique after the channel region of the groove (recess) is formed, the gate electrode region is formed as a channel by the margin for mask alignment. There is a problem that the area becomes larger than the area and the element area becomes large.

In addition, even if an attempt is made to form a silicide on the source electrode 3 and the drain electrode 4 in order to reduce the parasitic resistance, the source electrode 3 and the drain electrode 4 corresponding to the mask alignment margin are formed. There is also a problem that silicide cannot be formed because the gate electrode 8 is placed.

The present invention has been made in order to solve the above problems, and it is possible to reduce the element size and to reduce the parasitic resistance such as the gate resistance, the source resistance, and the drain resistance. An object is to provide an apparatus and a manufacturing method thereof.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device having a source region and a drain region spaced apart from each other on a surface portion, and a substrate semiconductor having a channel region in the middle of these regions, and a source region. A source electrode and a drain electrode stacked on the drain region, each side surface of the source electrode and the drain electrode facing each other across the channel region, and a gate insulating film formed continuously on the surface of the channel region, A gate electrode formed on the gate insulating film between the source electrode and the drain electrode so that the surface thereof is lower than the surface of either the source electrode or the drain electrode;
The silicide film formed on each surface of the source electrode, the drain electrode, and the gate electrode, and the silicide film formed on each side surface of the source electrode and the drain electrode facing each other, the silicide film on the drain electrode and the gate electrode And a sidewall insulating film separated from the silicide film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a first silicon film containing impurities on a surface of a substrate semiconductor and at least a first silicon film and a substrate semiconductor are selected. By partially etching the silicon film of No. 1, the substrate semiconductor is exposed on the bottom surface,
In addition, a step of forming a groove having a channel region inside the bottom, a step of forming a first insulating film on the inner surface of the groove and a surface of the first silicon film, and impurities in the first silicon film are used as a substrate semiconductor. Forming a source region and a drain region by diffusing into the second region, and forming a second region on the first insulating film so that the region corresponding to the trench is higher than the first silicon film on the side of the trench. The step of depositing a silicon film, and the second silicon film remains only inside the groove as a gate electrode, and the height of the surface is lower than the surface of the first silicon film on the side of the groove. The step of etching back the second silicon film, the step of forming the second insulating film on each surface of the second silicon film and the first insulating film, and the step of forming the second insulating film as a sidewall insulating film Etching back so that only the side wall remains, and the first silicon And a step of depositing a metal for forming a silicide on each surface of the second silicon film, and a step of causing a silicide reaction between the metal and the first silicon and between the metal and the second silicon, respectively. And removing the unreacted metal formed on the second insulating film.

[0011]

[Operation] Ultra-fine CON with a channel length of around 0.1 μm
In the CAVE MOSFET, the opening of the groove (recess) is extremely narrow. This groove is generally formed by etching. However, if the inventor chooses etching conditions even if polysilicon is deposited to fill the groove after gate oxidation and the entire surface of the substrate is etched back, It was confirmed that polysilicon can be left only inside the groove as an electrode, and the upper surface of the polysilicon can be made lower than the upper end of the edge of the groove if the etching time is appropriately selected.

With such a structure, the sidewall insulating film can be formed inside the groove. This sidewall insulating film plays a role of physically and electrically separating the silicide on the gate electrode from the respective silicides on the source electrode and the drain electrode in the next self-aligned silicide process (silicide process).

In this structure, when the substrate wafer is viewed from above, the source electrode, the gate electrode, and the drain electrode do not overlap each other, and the margin for mask alignment required when using the lithography technique is unnecessary. Becomes
The element area can be reduced.

Further, according to this structure, since the silicide is formed on the source electrode and the drain electrode to the edge of the gate electrode, the parasitic resistance can be sufficiently reduced.

[0015]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 shows a configuration of an embodiment of the present invention, (b) is a plan view of a main part, and (a) is a sectional view taken along line XX. In the figure, the same reference numerals as those in FIG. 5 denote the same elements.

This MOSFET is a P-type substrate semiconductor 1
The element isolation insulating film 2 is formed thereon. An intermediate channel region sandwiched between the element isolation insulating films 2 is dug down, and a polycrystalline silicon film is formed as a source electrode 3 on the upper surface of one side and a drain electrode 4 on the upper surface of the other side. Deposited on the element isolation insulating film 2,
A heavily doped n-type source region 5 and a drain region 6 are formed on the substrate side. Further, a polycrystalline silicon layer is formed inside the groove via a gate insulating film 7, and this serves as a gate electrode 8 of the MOSFET. The upper surface of the gate electrode 8 is lower than the upper surfaces of the source electrode 3 and the drain electrode 4 adjacent to the groove, and the side wall insulating film 9 is formed on the side wall of the groove formed on the upper surface of the gate electrode 8. Further, a source silicide layer 10 is formed on the source electrode 3, a drain silicide layer 11 is formed on the drain electrode 4, and a gate silicide layer 12 is formed on the gate electrode 8 so as to sandwich the sidewall insulating film 9. These silicide films are made of, for example, TiSi ₂ , NiSi ₂ ,
It is made of CoSi ₂ . Further, an interlayer insulating film 13 is deposited on these silicide films, a source electrode contact hole 17, a drain electrode contact hole 18 and a gate electrode contact hole 19 are formed in the interlayer insulating film 13, and further, these contact holes are penetrated. A source metal electrode 14, a drain metal electrode 15 and a gate metal electrode 16 are provided on the. As a result, an n-channel MOSFET in which the element region 22 shown in FIG. 1B is reduced and the parasitic resistance such as the gate resistance, the source resistance and the drain resistance is reduced can be obtained.

A method of manufacturing this n-channel MOSFET will be described with reference to FIGS. First, as in the case of a normal MOS type integrated circuit, as shown in FIG. 2A, the element isolation insulating film 2 is formed on the substrate semiconductor 1 to perform element isolation.

Next, as shown in FIG. 2 (b), the first polycrystalline silicon layer 20 is deposited on the entire surface of the substrate by LPCVD (low pressure vapor deposition) to a thickness of about 0.1 μm. Then, arsenic ions are ion-implanted under the conditions of ²⁰ keV and 5 × 10 ¹⁵ / cm ² for doping polycrystalline silicon.

Next, as shown in FIG. 2 (c), the polycrystalline silicon layer 20 in the portion to be the channel region is patterned by the lithography technique and etched by the RIE method (reactive ion etching method) to form the groove 20a. To form. At this time, the substrate semiconductor 1 is also etched until it becomes the same as the final bond depth, that is, about 50 to 100 nm. As a result, the polycrystalline silicon layer on one side becomes the source electrode 3, and the polycrystalline silicon layer on the other side becomes the drain electrode 4.

Next, as shown in FIG. 2 (d), a gate insulating film 7 having a thickness of about 5 nm is formed by thermal oxidation, and then a second polycrystalline silicon layer 21 is formed on the entire surface of the substrate by LPCVD. Deposit about 0.3 to 0.5 μm. Further, at the time of thermal oxidation, arsenic is diffused from the source electrode 3 and the drain electrode 4 in which arsenic ions are implanted to the substrate side to form the source region 5 and the drain region 6 having a high impurity concentration. The gate insulating film 7 is formed by CVD (Chemica) instead of thermal oxidation.
In addition to SiO ₂ , a high dielectric constant film such as Si ₃ N ₄ , Ta ₂ O ₅ , TiSrO ₃ or PZT may be used as the gate insulating film 7.

Next, as shown in FIG. 3 (a), the second polycrystalline silicon layer 21 is etched back to leave it only in the groove. That is, the gate electrode 8 is embedded in the groove. Here, by appropriately selecting the etching time, the upper surface of the second polycrystalline silicon layer 21 is etched so as to be below the upper surfaces of the source electrode 3 and the drain electrode 4 adjacent to the groove by about 20 to 40 nm. .

Next, a silicon nitride film is deposited on the entire surface by the LPCVD method and then etched back to form the structure shown in FIG.
As shown in (b), the sidewall insulating film 9 is formed while leaving the silicon nitride film only on the sidewall of the groove.

Next, as shown in FIG. 3C, the gate insulating film 7 on the source electrode 3 and the drain electrode 4 is removed by wet etching, and subsequently, Ti is deposited to 20 nm by a sputtering method. Then, rapid heating to about 800 ° C. is performed to form TiSi ₂ as silicide. Then, the titanium film on the silicon nitride film is removed by wet etching.

Next, as shown in FIG. 1B, an interlayer insulating film is deposited to form the source electrode contact hole 17, the drain electrode contact hole 18 and the gate electrode contact hole 19, and then the source metal electrode is made of aluminum. By forming 14, the drain metal electrode 15 and the gate metal electrode 16, the n-channel MOSFET shown in FIG. 1 (a) is obtained.

Although the gate electrode contact hole 19 is formed in the interlayer insulating film 13 on the gate electrode 8 having a uniform width in the above-mentioned embodiment, it is shown in FIG. 4 when patterning the first polycrystalline silicon layer 20. As shown in the drawing, if the portion deviating from the element region 22 is expanded, the opening for the gate electrode, that is, the gate electrode contact hole 19 can be expanded.

In the above embodiment, the n-channel MOS is used.
Although the FET has been described, the p-channel MOSFET can be manufactured in the same manner as described above.

Furthermore, in the above embodiment, a silicon wafer is usually used as the substrate semiconductor, but instead of this, S
Uses an OI (Silicon On Insulator) substrate and MOS
The channel region of the FET may be formed in the thin film silicon layer on the insulating film.

Further, single crystal silicon may be used as the first silicon film. In this case, amorphous silicon may be deposited from the substrate semiconductor 1 to the element isolation insulating film 2 and the amorphous silicon film may be monocrystallized by solid phase growth.

Similarly, single crystal silicon may be used as the second silicon film.

Furthermore, in the above-described embodiment, the CONCAVE MOSFET is described in which the substrate semiconductor 1 is also etched until the final bond depth becomes the same. However, the original surface of the substrate semiconductor 1 and the bottom surface of the groove coincide with each other. It goes without saying that the present invention can be applied to the CONCAVE MOSFET having the configuration.

[0031]

As is apparent from the above description, according to the present invention, it is possible to reduce the element size and to reduce the parasitic resistance such as the gate resistance, the source resistance and the drain resistance. A device and a manufacturing method thereof can be provided.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a configuration of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process drawing for explaining the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process drawing for explaining the manufacturing method of the semiconductor device according to the invention.

FIG. 4 is a plan view showing the configuration of another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing the structure of a conventional CONCAVE MOSFET.

[Explanation of symbols]

 1 substrate semiconductor 2 element isolation insulating film 3 source electrode 4 drain electrode 5 source region 6 drain region 7 gate insulating film 8 gate electrode 9 sidewall insulating film 10 source silicide layer 11 drain silicide layer 12 gate silicide layer 13 interlayer insulating film 14 source metal Electrode 15 Drain metal electrode 16 Gate metal electrode 17 Source electrode contact hole 18 Drain electrode contact hole 19 Gate electrode contact hole 22 Device area

Claims (2)

[Claims] 1. A substrate semiconductor having a source region and a drain region spaced apart from each other on a surface portion and having a channel region in the middle of these regions, and a source electrode and a drain region laminated on the source region. A drain electrode, side surfaces of the source electrode and drain electrode facing each other with the channel region sandwiched therebetween, and a gate insulating film formed continuously on the surface of the channel region, and the surface of the source electrode and drain electrode A gate electrode formed on the gate insulating film between the source electrode and the drain electrode so as to be lower than any surface; and a silicide film formed on each surface of the source electrode, the drain electrode, and the gate electrode. , A silicide film formed on each side surface of the source electrode and the drain electrode facing each other and on the gate electrode, A semiconductor device having a sidewall insulating films separated from each silicide films on the drain electrode and the gate electrode. 2. A step of forming a first silicon film containing an impurity on a surface of a substrate semiconductor, and at least the first silicon film of the first silicon film and the substrate semiconductor is partially formed. A step of exposing the substrate semiconductor to the bottom surface by etching and forming a groove having a channel region inside the bottom; and forming a first insulating film on the inner surface of the groove and the surface of the first silicon film. A step of forming a source region and a drain region by diffusing impurities in the first silicon film into the substrate semiconductor, and a portion corresponding to the groove is the first side portion of the groove. A second silicon film is deposited on the first insulating film so as to be higher than the first silicon film, and the second silicon film remains only inside the groove as a gate electrode, and High Etching back the second silicon film so that it is lower than the surface of the first silicon film on the side of the groove, and each of the second silicon film and the first insulating film. A step of forming a second insulating film on the surface; a step of etching back the second insulating film as a sidewall insulating film so as to remain only on the sidewalls of the trench; the first silicon film; and the second silicon film. Depositing a metal for forming a silicide on each surface of the silicon film, causing a silicide reaction between the metal and the first silicon, and between the metal and the second silicon, respectively. And a step of removing unreacted metal formed on the second insulating film.