JP2007214495A - Semiconductor device and method for fabrication thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing substrate floating effects, without threshold voltage variations in each position in the gate width direction, and to provide a method for manufacturing the same. <P>SOLUTION: This semiconductor device comprises an SOI (silicon-on-insulator) substrate 11 with a support substrate 11a, a BOX layer 11b and an SOI layer 11c, a gate insulating film 13 formed on the SOI layer 11c, a gate electrode 14 formed on the gate insulating film 13, a first conductive low-density area 15b formed in a region below the gate electrode 14 on the SOI layer 11c, a first conductive high-density region 15a formed in a region below the gate electrode 14 and between the lightly-doped regions 15b on the SOI layer 11c with impurity density higher than that of the low-density region 15b, and second conductive source and drain regions 16s and 16d formed in a pair of regions pinching the high-density region 15a and low-density region 15b on the SIO layer 11c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device using an SOI (Silicon On Insulator) substrate as a semiconductor substrate and a method for manufacturing the semiconductor device.

  2. Description of the Related Art Conventionally, there are semiconductor devices manufactured using an SOI (Silicon On Insulator) substrate. The SOI substrate is a semiconductor substrate having a support substrate such as a silicon substrate, an insulating film formed on the support substrate, and a silicon film formed on the insulating film. Hereinafter, the insulating film on the supporting substrate is referred to as a buried oxide film or a BOX (Buried Oxide) layer, and the silicon film on the BOX layer is referred to as a silicon thin film or an SOI layer.

  As a semiconductor device created using an SOI substrate, there is a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), for example. Hereinafter, this is referred to as SOI-MOSFET. Further, in order to distinguish from the SOI-MOSFET, a MOSFET formed using a bulk semiconductor substrate is hereinafter referred to as a bulk-MOSFET.

  The SOI-MOSFET can operate at a lower voltage and eliminate crosstalk noise from peripheral elements. For this reason, it has attracted particular attention in fields that require low power consumption, high integration, multiple functions, and high speed. Also, by using a thinner SOI substrate for the SOI layer, a so-called full depletion (hereinafter referred to as FD) type SOI-MOSFET in which the entire body region under the gate electrode is depleted when conducting is realized. Is possible. Such an FD-type SOI-MOSFET can suppress a substrate floating effect (also referred to as a kink effect) due to hot carriers generated near the junction surface between the SOI layer and the BOX layer.

  Note that hot carriers are most likely to occur in the junction region between the source or drain and the body region. This is because the electric field tends to concentrate near the junction interface between the source / drain and the body region. In order to solve such a problem, conventionally, a diffusion region having a lower impurity concentration than the source / drain, that is, a so-called LDD (Lightly Doped Drain) is provided in a region sandwiching under the gate, or a body region near the edge of the gate. A so-called Halo ion implantation method has been used in which a region having a low channel concentration is formed under the gate edge by locally implanting (counter-doping) an impurity having a conductivity type opposite to the above-described conductivity type. According to these structures and methods, since the electric field formed in the vicinity of the junction interface between the source / drain and the body region can be relaxed, generation of hot carriers can be suppressed.

  Further, the substrate floating effect in the SOI-MOSFET is a region having a particularly short gate length, in other words, a region in which a channel between a source and a drain (hereinafter referred to as a channel formation region) is short (this is referred to as a short channel region). ) Appears prominently. This is because in the short channel region, the electric field formed between the source and the drain becomes strong, and as a result, many hot carriers are generated. Such a phenomenon is called a short channel effect. When many hot carriers are generated due to the short channel effect, the substrate floating effect in the SOI-MOSFET cannot be suppressed, and as a result, there arises a problem that the threshold voltage of the SOI-MOSFET is lowered.

  As a reference, for example, Patent Document 1 shown below discloses a method for suppressing a change in threshold voltage from position to position due to variations in gate length in a short channel region. In this prior art, a so-called blank pattern insulating film (hereinafter referred to as a dummy gate) is formed on a bulk semiconductor substrate having a first conductivity type well region by inverting the pattern of the gate electrode. In other words, a dummy gate having an opening on the first conductivity type channel formation region is formed on the semiconductor substrate. Next, a channel is formed near the edge of the gate by implanting a second conductivity type impurity having a polarity opposite to that of the first conductivity type from a certain oblique direction with respect to the semiconductor substrate surface while using the dummy gate as a mask. An impurity having a conductivity type opposite to that of the region is locally counter-doped. Thereby, a counter-doped region having a low channel concentration is formed at the end of the channel formation region. At this time, the ion implantation angle is set so that the source-side region and the drain-side region into which the reverse polarity (second conductivity type) impurity is implanted do not overlap.

  According to this prior art, a counter-doped region is formed widely in a portion having a large opening length (width in the gate length direction) in the dummy gate, that is, a portion having a long gate length. On the other hand, in the portion where the gate length is short, the counter-doped region is formed narrowly. Therefore, the distance between the counter-doped region formed on the source side and the counter-doped region formed on the drain side becomes narrow in a portion with a long gate length that is a high threshold voltage portion. As a result, the threshold voltage in this portion is corrected so as to be low. Further, in a portion with a short gate length, which is a portion having a low threshold voltage, the distance between the counter-doped region formed on the source side and the counter-doped region formed on the drain side becomes wide. As a result, the threshold voltage in this portion is corrected so as to increase.

As described above, in this prior art, the distance between the counter-doping regions is adjusted in a self-aligned manner according to the length of the gate length, so that the threshold voltage varies depending on the position in the gate width direction due to the variation in the gate length. It is possible to suppress this.
JP 2000-77661 A

  As described above, in order to suppress the substrate floating effect in the SOI-MOSFET, it is necessary to suppress the generation of hot carriers, and a method for realizing this is to have an impurity concentration higher than that of the source / drain in the region sandwiched under the gate. There are a method of providing a low LDD, a Halo ion implantation method in which an impurity having a conductivity type opposite to that of the body region is locally counter-doped near the edge of the gate.

  However, the method of counter-doping the conductivity type (second conductivity type) opposite to the conductivity type (first conductivity type) of the channel formation region (body region) has poor channel concentration controllability in the counter-doped region. It is difficult to accurately and uniformly control the channel concentration in the counter-doped region. For this reason, there arises a problem that the threshold voltage after counter doping varies depending on the position in the gate width direction.

  Such a problem is also a problem that occurs when the counter-doped region in Patent Document 1 described above is formed. For this reason, it is difficult to accurately control the variation of the threshold voltage for each position using the technique disclosed in Patent Document 1 described above.

  Therefore, the present invention has been made in view of the above problems, and a semiconductor device and a semiconductor device manufacturing capable of suppressing the substrate floating effect without varying the threshold voltage at each position in the gate width direction. It aims to provide a method.

  In order to achieve such an object, a semiconductor device according to the present invention includes an SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer, and a semiconductor layer. A formed gate insulating film; a gate electrode formed on the gate insulating film; a first region of a first conductivity type formed in a region under the gate electrode end in the semiconductor layer; and a semiconductor under the gate electrode. Formed in a region sandwiched between the first regions in the layer, and formed in a first conductivity type second region having a higher impurity concentration than the first region and a pair of regions sandwiching the first and second regions in the semiconductor layer. And a high-concentration diffusion region of a second conductivity type having a polarity opposite to that of the first conductivity type.

  A first region having a lower impurity concentration than the central portion is formed below the edge of the gate electrode. In other words, the impurity concentration at the edge portion in the body region (also referred to as a channel formation region) under the gate electrode is set lower than that in the central portion. With this configuration, the electric field in the vicinity of the junction between the high-concentration diffusion region and the body region is relieved, so that generation of hot carriers in this portion can be reduced. As a result, the Schottky barrier at the junction between the high concentration diffusion region and the body region can be reduced, and hot carriers generated in the body region can be efficiently extracted from the high concentration diffusion region side. As a result, the substrate floating effect of the semiconductor device can be suppressed. Further, the first region is a region having a channel concentration lower than that of the second region located in the substantially central portion under the gate electrode. However, the first region according to the present invention is a region having a lower impurity concentration than the second region. That is, the first region is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a first region is a region where variation in threshold voltage caused by counter doping is avoided, and as a result, variation in threshold voltage of the semiconductor device can be suppressed.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer; Forming a first insulating film, forming an opening in the first insulating film, forming a first conductivity type first region in a region below the opening end of the semiconductor layer, and opening the semiconductor layer Forming a second region of the first conductivity type sandwiched between the first region and having a higher impurity concentration than the first region, and first filling the opening completely on the first insulating film and in the opening A step of forming a conductor film, a step of planarizing the surface of the first conductor film and exposing the upper surface of the first insulating film, thereby forming a gate electrode in the opening, and a step of removing the first insulating film The second conductive layer is formed in a pair of regions sandwiching the gate electrode under the semiconductor layer. Constructed and a step of forming a high concentration diffusion region of.

  A first region having a lower impurity concentration than the central portion is formed below the edge of the opening in which the gate electrode is formed. In other words, the impurity concentration at the edge portion in the body region (also referred to as a channel formation region) under the gate electrode is set to the center. By making it lower than the portion, the electric field in the vicinity of the junction between the high concentration diffusion region and the body region is relaxed, so that a semiconductor device in which the generation of hot carriers in this portion is reduced can be manufactured. In such a semiconductor device, the Schottky barrier at the junction between the high concentration diffusion region and the body region can be reduced, so that hot carriers generated in the body region can be efficiently extracted from the high concentration diffusion region side. Is possible. Therefore, a semiconductor device in which the substrate floating effect is suppressed can be manufactured. Further, the first region is a region having a channel concentration lower than that of the second region located in the substantially central portion under the gate electrode. However, the first region according to the present invention is a region having a lower impurity concentration than the second region. That is, the first region is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a first region is a region where variation in threshold voltage caused by counter-doping is avoided, and as a result, a semiconductor device in which variation in threshold voltage is suppressed can be manufactured.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can suppress a board | substrate floating effect, and its manufacturing method are realizable, without varying the threshold voltage in each position of a gate width direction.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following description, each drawing only schematically shows the shape, size, and positional relationship to the extent that the contents of the present invention can be understood. Therefore, the present invention is illustrated in each drawing. It is not limited to only the shape, size, and positional relationship. Moreover, in each figure, a part of hatching in a cross section is abbreviate | omitted for clarity of a structure. Furthermore, the numerical values exemplified below are merely preferred examples of the present invention, and therefore the present invention is not limited to the illustrated numerical values.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. In the following description, an SOI-MOSFET in which an n-type channel is formed will be described as an example.

Configuration FIG. 1 is a diagram showing a schematic configuration of an SOI-MOSFET 1 which is a semiconductor device according to the present embodiment. FIG. 1 is a cross-sectional view of the SOI-MOSFET 1 cut along a plane perpendicular to the gate width direction.

  As shown in FIG. 1, the SOI-MOSFET 1 includes a support substrate 11a, a BOX layer (insulating layer) 11b formed on the support substrate 11a, and an SOI layer (semiconductor layer) 11c formed on the BOX layer 11b. SOI substrate 11, gate insulating film 13 and gate electrode 14 formed on SOI layer 11c of SOI substrate 11, and element isolation insulating film (also referred to as field oxide film) 12 formed on SOI layer 11c of SOI substrate 11 And a body region 15 and a pair of source region 16s and drain region 16d. Further, on the SOI-MOSFET 1 formed on the SOI substrate 11 as described above, the interlayer insulating film 17, the via wiring 18, and the metal wiring 19 are formed as shown in FIG.

In the above configuration, the support substrate 11a in the SOI substrate 11 is a bulk silicon substrate containing, for example, p-type impurities so as to have a concentration of, for example, about 1 × 10 ¹⁵ / cm ³ . The substrate resistance is, for example, about 8 to 22 Ω (ohms). However, the present invention is not limited to this, and various semiconductor substrates can be applied.

  The BOX layer 11b in the SOI substrate 11 is a silicon oxide film having a thickness of about 1000 to 2000 angstroms, for example. However, the present invention is not limited to this, and various insulating films can be applied.

The SOI layer 11c in the SOI substrate 11 is a silicon thin film containing, for example, a p-type impurity so as to have a concentration of about 1 to 3 × 10 ¹⁵ / cm ³ , for example, like the support substrate 11a. The film thickness can be about 200 to 1000 mm, for example. Note that a non-doped silicon thin film can also be applied to the SOI layer 11c. In this case, the impurity concentration is the same as that of the support substrate 11a, for example, about 1 × 10 ¹⁵ / cm ³ .

  As described above, the SOI layer 11c in the SOI substrate 11 is divided into an element formation region (also referred to as an active region) and an element isolation region (also referred to as a field region) by forming the element isolation insulating film 12. Yes. The element isolation insulating film 12 can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method. However, the present invention is not limited to this, and it can be formed by using, for example, an STI (Shallow Trench Isolation) method.

  As described above, the body region 15 is formed in the element formation region in the SOI layer 11c. The body region 15 is a region into which a predetermined impurity is implanted in order to control the threshold voltage Vt of the SOI-MOSFET 1. In this embodiment, a p-type impurity is implanted into the body region 15 to illustrate an SOI-MOSFET in which an n-type channel is formed. For example, boron ions (including boron difluoride ions) can be applied to the p-type impurities. However, when manufacturing an SOI-MOSFET in which a p-type channel is formed, an n-type impurity is implanted into the body region 15. For example, phosphorus ions or arsenic ions can be applied to the n-type impurity.

  The body region 15 according to this embodiment includes a low concentration region (first region) 15b formed below the edge of the gate electrode 14 described later, and a high concentration region (first region) formed substantially below the gate electrode 14, respectively. Second region) 15a. In other words, the body region 15 is formed in a low concentration region 15b formed in a portion in contact with a pair of a source region 16s and a drain region 16d described later, and a region sandwiched between the two low concentration regions 15b. And a high concentration region 15a. The high concentration region 15a and the low concentration region 15b are in contact with each other.

The high concentration region 15a is a region where p-type impurities are implanted so as to have a concentration of about 1 × 10 ¹⁸ / cm ^3, for example. The low-concentration region 15b is a region in which p-type impurities are implanted so as to have a concentration lower than that of the high-concentration region 15a, for example, a concentration of about 0.75 × 10 ¹⁸ / cm ³ . Therefore, the channel concentration of the low concentration region 15b is lower than the channel concentration of the high concentration region 15a. The low concentration region 15b is not a region formed by counter-doping an impurity having a polarity opposite to that of the conductivity type (in this example, n-type) of the high concentration region 15a (in this example, p-type). The impurity concentration of the region 15b is also lower than the impurity concentration of the high concentration region 15a.

  Further, the gate insulating film 13 is formed on the body region 15 having the above configuration. The gate insulating film 13 is a silicon oxide film formed by, for example, thermally oxidizing the surface of the SOI layer 11c. However, the present invention is not limited to this. For example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method or an insulating film formed by another film forming method can be applied. Moreover, the film thickness of the gate insulating film 13 can be about 20-50 mm, for example.

  As described above, the gate electrode 14 is formed on the gate insulating film 13. The gate electrode 14 is a polysilicon film having conductivity by containing a predetermined impurity (preferably an n-type impurity), for example. However, the present invention is not limited to this, and various conductor films such as a metal film formed of, for example, titanium, aluminum, copper, another metal, or an alloy containing any of them can be used. The film thickness of the gate electrode 14 can be about 2000 mm, for example. The length of the gate electrode 14 in the gate length direction (hereinafter simply referred to as the gate length) can be, for example, about 2000 mm. However, the film thickness and the gate length of the gate electrode 14 are not limited to the above values, and can be variously modified as long as the formation process of the body region 15 described later can be performed.

A source region 16s and a drain region 16d are respectively formed in a pair of regions sandwiching the gate electrode 14 under the SOI layer 11c. In other words, a pair of source region 16s and drain region 16d sandwiching the body region 15 are formed in the element formation region in the SOI layer 11c. The source region 16s and the drain region 16d are high-concentration diffusion regions in which n-type impurities are implanted and diffused so as to have a concentration of about 1 × 10 ²¹ / cm ^3, for example. The source region 16s is a region that can also function as a drain. The drain region 16d is a region that can also function as a source. In this embodiment, for convenience of explanation, one of the pair of high concentration diffusion regions is a source region 16s and the other is a drain region 16d.

  As described above, the SOI-MOSFET 1 according to this embodiment has the low concentration regions 15b formed under the edge of the gate electrode 14, respectively. In this way, by setting the channel concentration under the edge of the gate electrode 14 lower than the channel concentration under the center of the gate electrode 14, the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 15 is relaxed. Therefore, the generation of hot carriers in this portion can be reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 15 can be reduced, and hot carriers generated in the body region 15 can be efficiently extracted from the source region 16s side. It becomes. As a result, the substrate floating effect of the SOI-MOSFET 1 can be suppressed. This principle will be described with reference to FIG.

  FIG. 2A is a diagram showing the potential of electrons and holes for each position along the gate length direction in the SOI-MOSFET 900 that does not have a low concentration region at the end of the body region. FIG. 2B is a diagram showing the potential of electrons and holes for each position along the gate length direction in the SOI-MOSFET 1 according to this embodiment having a low concentration region at the end of the body region. As is apparent from FIGS. 2A and 2B, this embodiment is compared with the SOI-MOSFET 900 (see FIG. 2A) which does not have a low concentration region at the end of the body region. SOI-MOSFET 1 (see FIG. 2B) has a low Schottky barrier due to the displacement of the potential of electrons and holes. For this reason, in the SOI-MOSFET 1 according to this embodiment, hot carriers accumulated at the bottom of the body region 15 can be efficiently extracted toward the source region 16s, and as a result, the substrate floating effect of the SOI-MOSFET 1 can be reduced. Can do.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 1 according to this embodiment will be described in detail with reference to the drawings. 3 to 9 are process diagrams showing a method for manufacturing the SOI-MOSFET 1.

In this manufacturing method, first, as shown in FIG. 3A, an SOI substrate 11 in which a BOX layer 11b and an SOI layer 11c are sequentially stacked on a support substrate 11a is prepared. The BOX layer 11b is a silicon oxide film having a film thickness of about 1000 to 2000 mm, for example, as described above. Further, as described above, the SOI layer 11c is a silicon thin film having a film thickness of about 200 to 1000 mm and an impurity concentration of about 1 × 10 ¹⁵ / cm ^3, for example.

  Next, an element isolation insulating film 12 is formed on the SOI layer 11c in the SOI substrate 11 by using, for example, the STI method, thereby dividing the element formation region 11A in the SOI layer 11c as shown in FIG.

  Next, the surface of the SOI layer 11c is thermally oxidized to form a buffer oxide film 101 thereon. The buffer oxide film 101 is an adhesion layer for bringing the silicon nitride film 102 to be formed next and the SOI substrate 11 into close contact, and is, for example, a silicon oxide film having a thickness of about 70 to 100 mm. Subsequently, a silicon nitride film 102 having a thickness of, for example, about 500 mm is formed on the buffer oxide film 101. This silicon nitride film 102 is a stopper film for limiting the etching amount (depth) when patterning a relatively thick glass oxide film (first insulating film) 103 to be formed next. Therefore, a film (a silicon nitride film in this example) that has a sufficient selection ratio with respect to the glass oxide film 103 is used for this film. Subsequently, a glass oxide film (also referred to as an NSG (Nondoped Silicate Glass) film) 103 having a film thickness of, for example, about 2000 mm is formed on the silicon nitride film 102. Subsequently, the upper surface of the glass oxide film 103 formed as described above is planarized by using, for example, a CMP (Chemical and Mechanical Polishing) method. Thus, as shown in FIG. 3C, the buffer oxide film 101, the silicon nitride film 102, and the glass oxide film 103 are sequentially stacked on the SOI layer 11c. In the thermal oxidation at the time of forming the buffer oxide film 101, the heating temperature is set to 500 ° C., for example, and the heating time is set to 30 minutes, for example.

  Next, a predetermined resist solution is spin-coated on the glass oxide film 103, and after passing through an existing photolithography process, on a region where the gate electrode 14 is formed in a later step, that is, on a region where the body region 15 is formed. A resist pattern R11 having openings in the glass oxide film 103 is formed. Subsequently, the glass oxide film 103, the silicon nitride film 102, and the buffer oxide film 101 are sequentially etched using the resist pattern R11 as a mask, thereby forming a body region 15 as shown in FIG. An opening 103A having a length in the gate length direction of, for example, about 2000 mm is formed in the upper glass oxide film 103. As a result, the glass oxide film 103 becomes a so-called blank pattern (dummy gate 103B) obtained by inverting the pattern of the gate electrode 14, and the region where the gate electrode 14 is formed in the element formation region 11A of the SOI layer 11c is exposed. Is done. Note that the glass oxide film 103 is preferably etched by isotropic wet etching using HF. This is because the glass oxide film 103 formed on the side surface of the gate electrode 14 is easily removed when isotropic etching is used.

  Next, after removing the resist pattern R11, the surface of the element formation region 11A exposed from the opening 103A is thermally oxidized, so that the mask oxide film 104 is formed on the exposed element formation region 11A as shown in FIG. Form. The mask oxide film 104 is a film for reducing damage to the body region 15 when an impurity for adjusting the threshold voltage Vt is implanted into the body region 15 in a later process. It is an oxide film. In the thermal oxidation when forming the mask oxide film 104, the heating temperature can be set to 850 ° C., for example, and the heating time can be set to 30 minutes, for example.

  Next, while using the dummy gate 103B as a mask, a predetermined impurity (p-type ions in this example) for adjusting the threshold voltage Vt is applied to the element formation region 11A from the opening 103A of the dummy gate 103B through the mask oxide film 104. By implanting, the body region 15 is formed under the opening 103A. At this time, the predetermined impurity for adjusting the threshold voltage Vt is implanted in an oblique direction with respect to the surface of the SOI substrate 11. As a result, as shown in FIG. 5A, the body region 15 including the high concentration region 15a and the low concentration region 15b is formed in the element formation region 11A. An element formation region 11S in which a source region 16s is formed in a later process is formed in a region below the dummy gate 103B and in contact with one end of the body region 15, and in a region in contact with the other end. The element formation region 11D in which the drain region 16d is formed in a later step is formed.

  The formation process of the body region 15 will be described in more detail. In this step, the SOI substrate 11 processed as described above is placed on the turntable 111 provided in the ion implantation apparatus 110 as shown in FIG. The rotation axis of the turntable 111 is inclined at a predetermined angle (hereinafter referred to as an incident angle θ) with respect to the ion implantation direction (in this example, the vertical direction). Therefore, when predetermined ions are implanted while rotating the SOI substrate 11 in this state, the sidewall of the opening 103A of the dummy gate 103B is formed on the element formation region 11A (actually on the mask oxide film 104) below the opening 103A. The shadow is made. The range of the incident angle θ employed in this embodiment will be described in detail later.

  For example, as shown in FIG. 6A, when the SOI substrate 11 is inclined so that the side where the drain region 16d is formed (the element formation region 11D side in FIG. 6A) is higher, the element formation region The side wall of the dummy gate 103B on the 11D side becomes a mask protruding onto the body region 15. Therefore, when a predetermined impurity is implanted from the vertical direction in this state, the protruding shadow of the dummy gate 103B is formed on the end of the body region 15 on the element forming region 11D side. For this reason, the amount of impurities implanted into this portion is reduced.

  On the other hand, as shown in FIG. 6B, for example, when the SOI substrate 11 is tilted so that the side where the source region 16s is formed (the element formation region 11S side in FIG. 6B) is high. A side wall of the dummy gate 103B on the formation region 11S side becomes a mask protruding onto the body region 15. For this reason, when a predetermined impurity is implanted from the vertical direction in this state, a shadow of the protruding dummy gate 103B is formed on the end of the body region 15 on the element forming region 11S side. For this reason, the amount of impurities implanted into this portion is reduced.

  Note that since the shadow of the side wall of the dummy gate 103B as described above is not formed substantially at the center in the element formation region 11A under the opening 103A, the amount of impurities implanted into this portion is not reduced.

  As a result of the above steps, the region under the opening 103A in the element formation region 11A has a low concentration region 15b in the outer peripheral portion and a high concentration region 15a in the central portion as shown in FIG. Region 15 is formed.

In the above process, for example, boron ions (including boron difluoride ions) can be applied to the predetermined impurity for adjusting the threshold voltage Vt. As the impurity implantation conditions, for example, the acceleration energy is set to about 20 KeV (kiloelectron volts) and the dose amount is set to about 1 × 10 ¹² / cm ² . However, for example, when forming a p-type SOI-MOSFET, phosphorus ions, arsenic ions, or the like can be applied to the predetermined impurity for adjusting the threshold voltage Vt. In this case, as the impurity implantation conditions, for example, the acceleration energy is set to about 15 to 20 KeV and the dose amount is set to about 1 × 10 ¹² / cm ² can be applied.

  Next, after removing the mask oxide film 104 under the opening 103A, the exposed body region 15 surface is thermally oxidized, so that, for example, a film thickness is formed on the surface of the body region 15 as shown in FIG. A gate insulating film 13 made of a silicon oxide film of about 20 to 50 mm is formed. For removing the mask oxide film 104, for example, wet etching using a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be applied. Moreover, as thermal oxidation conditions at the time of forming the gate insulating film 13, the heating temperature can be set to, for example, 850 ° C., and the heating time can be set to, for example, 20 minutes.

  Next, polysilicon containing n-type impurities such as phosphorus is deposited on the surface of the SOI substrate 11 by, for example, an existing CVD method, and as shown in FIG. A polysilicon film (first conductor film) 14A is formed in the opening 103A. The thickness of the deposited polysilicon film 14A is set to be equal to or greater than the thickness of the dummy gate 103B, in other words, equal to or greater than the depth of the opening 103A. As a result, the opening 103A can be completely filled with the polysilicon film 14A.

  Next, the polysilicon film 14A on the dummy gate 103B is removed by, for example, the existing CMP method, so that the opening 103A of the dummy gate 103B, that is, on the body region 15 is formed as shown in FIG. Then, the gate electrode 14 having a thickness of about 2000 mm is formed.

  Next, by sequentially removing the dummy gate 103B, the silicon nitride film 102, and the buffer oxide film 101 on the SOI substrate 11 by etching, as shown in FIG. 8B, an element formation region adjacent to the bottom of the gate electrode 14 is formed. 11S and 11D are exposed. Note that it is preferable to use isotropic wet etching with HF to remove the dummy gate 103B which is a glass oxide film. This is because the glass oxide film 103 formed on the side surface of the gate electrode 14 is easily removed when isotropic etching is used.

  Next, the entire upper surface of the SOI substrate 11 is thermally oxidized, for example, to form a mask oxide film 105 at least on the exposed surface of the element formation regions 11S and 11D, as shown in FIG. This mask oxide film 105 is a film for reducing the damage to the element formation regions 11S and 11D due to the impurity implantation when forming the source region 16s and the drain region 16d in a later process. It is a silicon oxide film. In the thermal oxidation when forming the mask oxide film 104, the heating temperature can be set to 850 ° C., for example, and the heating time can be set to 30 minutes, for example.

Next, predetermined impurities such as boron ions (including boron difluoride ions) are implanted into the entire upper surface of the SOI substrate 11. At this time, since the gate electrode 14 and the element isolation insulating film 12 serve as a mask, predetermined impurities are implanted into the element formation regions 11S and 11D in a self-aligning manner. Subsequently, the impurities implanted into the element formation regions 11S and 11D are thermally diffused. As a result, as shown in FIG. 9B, a pair of source region 16s and drain region 16d sandwiching the body region 15 under the gate electrode 14 is formed. In the ion implantation at the time of forming the source region 16s and the drain region 16d, a condition in which the dose amount is set to about 1 × 10 ¹⁵ / cm ² and acceleration energy is set to about 10 KeV can be applied. Further, for the heat treatment at the time of diffusion, for example, lamp annealing with a heating temperature of 1000 ° C. and a heating time of 10 seconds can be applied.

  Through the above steps, the SOI-MOSFET 1 according to this embodiment is manufactured.

  Thereafter, an interlayer insulating film 17 is formed by depositing silicon oxide on the formed SOI-MOSFET 1 to such an extent that it is buried. Next, an opening that exposes the gate electrode 14 and the upper surfaces of the source region 16s and the drain region 16d is formed in the interlayer insulating film 17 by using an existing photolithography method and etching method. Subsequently, by filling the formed opening with a conductor such as tungsten (W), via wiring for drawing out the electrical connection between the gate electrode 14, the source region 16 s and the drain region 16 d up to the interlayer insulating film 17. 18 is formed. At this time, the surface of the gate electrode 14, the surface of the source region 16s, and the surface of the drain region 16d exposed from the opening formed in the interlayer insulating film 17 may be silicidized to form silicide films respectively. Subsequently, after a conductor film such as copper or aluminum is formed on the interlayer insulating film 17, it is electrically connected to each via wiring 18 by patterning it using an existing photolithography process and etching process. A metal wiring 19 is formed. Thereby, SOI-MOSFET 1 having a cross-sectional structure as shown in FIG. 1 can be manufactured.

  As described above, in this embodiment, the low concentration region 15b is formed at the end of the body region 15, and the high concentration region 15a is formed at the center. For this reason, the tilt angle of the turntable 111 with respect to the ion implantation direction, in other words, the tilt of the ion implantation direction with respect to the surface of the SOI substrate 11 (incident angle θ) is set within the range represented by the following Expression 1. In the following formula 1, L represents the width of the opening 103A in the gate length direction. Therefore, L corresponds to the gate length. Further, H indicates the height of the side surface of the opening 103A. Therefore, L corresponds to the film thickness of the dummy gate 103B (glass oxide film 103).

  By setting the incident angle θ within the above range, as is clear from the diagram shown in FIG. 10, the shadow of the dummy gate 103B is not formed in the substantially central portion of the body region 15. This part is always irradiated with ions. Thereby, the impurity concentration at the substantially central portion in the body region 15 is increased, and as a result, the high concentration region 15a is formed. In addition, FIG. 10 is a figure for demonstrating the range of incident angle (theta) in a present Example.

  However, in the present embodiment, it is preferable to make the incident angle θ as small as possible if a desired value can be obtained for the width of the low concentration region 15b in the gate length direction. For example, in this embodiment, it is preferable to set the film thickness H of the dummy gate 103B and the length L in the gate length direction of the opening 103A so that the incident angle θ is 10 ° or more and 20 ° or less. As a result, the acceleration energy of the implanted impurity can be reduced, and as a result, damage to the body region 15 during the impurity implantation can be reduced.

  In addition, the present inventors have experimented that it is preferable to set the width of the low concentration region 15b in the gate length direction to about 1/5 to 1/3 of the gate length, for example, about 1/4. It was found by. In this case, if the thickness of the dummy gate 103B is about 2000 mm, the width of the opening 103A in the gate length direction is about 2000 mm, and the thickness of the SOI layer 11c is about 500 mm, the incident angle θ is about 14 °. .

  As described above, in the method for manufacturing the SOI-MOSFET 1 according to the present embodiment, a predetermined impurity is implanted while rotating the SOI substrate 11 in an inclined state, whereby the high concentration region 15a having a high channel concentration is injected into the body region 15. Since the low concentration region 15b having a low channel concentration is formed, it is not necessary to counter-dope the body region 15 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 1 can be adjusted more easily than the counter dope method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used.

  Further, in the method for manufacturing the SOI-MOSFET 1 according to the present embodiment, when the impurity implantation for adjusting the threshold voltage Vt is performed, the shadow of the dummy gate 103B does not extend to the approximate center of the body region 15 (incident angle θ). Impurities are implanted. Therefore, the width in the gate length direction of the low-concentration region 15b does not depend on the length in the gate length direction of the opening 103A of the dummy gate 103B, that is, the gate length, and only by the height H of the dummy gate 103B and the incident angle θ. It is determined. For this reason, in the present embodiment, the threshold voltage Vt of the SOI-MOSFET 1 can be controlled only by the amount of impurities to be implanted.

  Further, in the method for manufacturing the SOI-MOSFET 1 according to the present embodiment, the gate electrode 14 is formed by removing the polysilicon film 14A deposited to the same thickness as the dummy gate 103B up to the upper surface of the dummy gate 103B by CMP. To do. For this reason, even when the gate electrode 14 having a long gate length is formed, the height of the gate electrode 14 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

As described above, the SOI-MOSFET 1 according to the present embodiment includes the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. The substrate 11, the gate insulating film 13 formed on the SOI layer 11c, the gate electrode 14 formed on the gate insulating film 13, and the first conductivity formed in the region below the end of the gate electrode 14 in the SOI layer 11c. A first conductive layer formed in a region sandwiched between a low concentration region 15b of a type (for example, p type) and the low concentration region 15b in the SOI layer 11c under the gate electrode 14, and having a higher impurity concentration than the low concentration region 15b. The first conductivity type is formed in a pair of regions sandwiching the high concentration region 15a and the low concentration region 15b in the SOI layer 11c. It has a source region 16s and a drain region 16d of the second conductivity type (for example, n-type) having a polarity opposite to that of (for example, p-type).

  In the method for manufacturing the SOI-MOSFET 1 according to the present embodiment, the SOI substrate 11 having the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b is used. A glass oxide film 103 is formed on the SOI layer 11c, an opening 103A is formed in the glass oxide film 103 to form a dummy gate 103B, and a first conductivity type is formed in a region below the edge of the opening 103A in the SOI layer 11c. A low-concentration region 15b (for example, p-type) is formed, and the first conductivity type (for example, p-type) is interposed between the low-concentration region 15b in the region below the opening 103A in the SOI layer 11c and has a higher impurity concentration than the low-concentration region 15b. ) High-concentration region 15a, and the polysilicon film 1 completely filling the opening 103A on the dummy gate 103B and in the opening 103A A is formed, the surface of the polysilicon film 14A is flattened to expose the upper surface of the dummy gate 103B, thereby forming the gate electrode 14 in the opening 103A, removing the dummy gate 103B, and under the gate electrode 14 in the SOI layer 11c. A source region 16s and a drain region 16d of the second conductivity type (for example, n-type) are formed in a pair of regions sandwiching.

  A low concentration region 15b having a lower impurity concentration than the central portion is formed under the edge of the gate electrode 14, in other words, the impurity concentration of the edge portion in the body region 15 (also referred to as a channel formation region) under the gate electrode 14 is set to the central portion. Since the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 15 is relaxed, the generation of hot carriers in this portion can be reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 15 can be reduced, and hot carriers generated in the body region 15 can be efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 1 can be suppressed. Further, the low concentration region 15b is a region having a channel concentration lower than that of the high concentration region 15a located at the substantially central portion under the gate electrode 14. However, the low concentration region 15b according to the present embodiment is a region having a lower impurity concentration than the high concentration region 15a. That is, the low concentration region 15b is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a low concentration region 15b is a region where variation in threshold voltage caused by counter-doping is avoided, and as a result, variation in threshold voltage of the SOI-MOSFET 1 can be suppressed.

  Further, the gate electrode 14 according to the present embodiment is formed by removing the polysilicon film 14A deposited to the same thickness as the dummy gate 103B up to the upper surface of the dummy gate 103B by CMP. For this reason, even when the gate electrode 14 having a long gate length is formed, the height of the gate electrode 14 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

  Further, in this embodiment, the high concentration region 15a and the low concentration region 15b tilt the SOI substrate 11 on which the dummy gate 103B having the opening 103A is formed by a predetermined angle (θ) with respect to a predetermined direction (ion implantation direction). The first conductivity type (for example, p-type) impurity is implanted through the opening 103A from the ion implantation direction while rotating in a state. For this reason, it is not necessary to counter-dope the body region 15 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 1 can be adjusted more easily than the counter dope method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used.

  Further, the predetermined angle (θ) at this time is set within a range satisfying the above-described expression 1 when the film thickness of the dummy gate 103B is H and the length of the opening 103A in the gate length direction is L. . By setting the predetermined angle (θ) within a range that satisfies the above conditions, the shadow of the dummy gate 103B does not extend to substantially the center of the body region 15 during impurity implantation for adjusting the threshold voltage Vt. Therefore, the width in the gate length direction of the low-concentration region 15b does not depend on the length in the gate length direction of the opening 103A of the dummy gate 103B, that is, the gate length, and only by the height H of the dummy gate 103B and the incident angle θ. It is determined. For this reason, in the present embodiment, the threshold voltage Vt of the SOI-MOSFET 1 can be controlled only by the amount of impurities to be implanted.

  In the present embodiment, the length of the low concentration region 15b in the gate length direction is set to be one fifth to one third of the length of the gate electrode 14 in the gate length direction. preferable.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, an SOI-MOSFET in which an n-type channel is formed will be described as an example. Moreover, in the following description, about the structure similar to Example 1, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment.

Configuration FIG. 11 is a diagram showing a schematic configuration of an SOI-MOSFET 2 which is a semiconductor device according to the present embodiment. FIG. 11 is a cross-sectional view of the SOI-MOSFET 2 cut along a plane perpendicular to the gate width direction.

  As shown in FIG. 11, the SOI-MOSFET 2 has the same configuration as that of the SOI-MOSFET 1 according to the first embodiment, and the gate insulating film 13 is replaced with a gate insulating film 23.

  The gate insulating film 23 is formed on the body region 15 similarly to the gate insulating film 13. The gate insulating film 23 is a high-k film formed by, for example, a CVD method. The High-k film is an insulating film having a relative dielectric constant higher than that of a silicon oxide film (3.9), for example. Moreover, the film thickness can be made into about 10-50 mm, for example.

  By using such a High-k film for the gate insulating film 23, the effect of suppressing leakage current can be enhanced. For this reason, the gate insulating film 23 can be made thinner.

  Since other configurations are the same as those of the SOI-MOSFET 1 according to the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 2 according to the present embodiment will be described in detail with reference to the drawings. 12 to 14 are process diagrams showing a method for manufacturing the SOI-MOSFET 2. In the manufacturing method according to the present embodiment, the steps until the dummy gate 103B is formed on the SOI substrate 11 (see FIGS. 3A to 4A) are the same as in the first embodiment. Then, detailed explanation is omitted. However, in this embodiment, the length in the gate length direction of the opening 103A ′ formed in the glass oxide film 103 is twice that of a high-k film 23A described later than the opening 103A according to the first embodiment. Also grows. Further, in the manufacturing method according to the present embodiment, after the gate insulating film 23 and the gate electrode 14 are formed on the body region 15, the steps after the element formation regions 11S and 11D are exposed (FIGS. 9A and 9D). b) is the same as that of the first embodiment, and thus detailed description thereof is omitted here.

  In this manufacturing method, when the dummy gate 103B is formed on the SOI substrate 11 using the steps according to the first embodiment (see FIGS. 3A to 4A), then, for example, the existing CVD method is used. Then, as shown in FIG. 12A, a High-k film 23A having a film thickness of, for example, about 10 to 50 mm is formed on the upper surface of the dummy gate 103B and on the side surface and the bottom surface of the opening 103A ′.

  Next, while using the dummy gate 103B as a mask, a predetermined impurity (in this example, n-type ions) for adjusting the threshold voltage Vt enters the element formation region 11A from the opening 103A ′ of the dummy gate 103B through the High-k film 23A. ) To form the body region 15 under the opening 103A ′. At this time, the predetermined impurity for adjusting the threshold voltage Vt is implanted in an oblique direction with respect to the surface of the SOI substrate 11 as in the first embodiment. As a result, as shown in FIG. 12B, the body region 15 composed of the high concentration region 15a and the low concentration region 15b is formed in the element formation region 11A, and the region below the dummy gate 103B is the body region. An element formation region 11S in which a source region 16s is formed in a later step is formed in a region in contact with one end of the region 15, and an element formation region 11D in which a drain region 16d is formed in a later step in a region in contact with the other end. It is formed.

In the above steps, for example, boron ions (including boron difluoride ions) can be applied to the predetermined impurities for adjusting the threshold voltage Vt, as in the first embodiment. As the impurity implantation conditions, for example, the acceleration energy is set to about 15 to 20 KeV (kiloelectron volts) and the dose amount is set to about 1 × 10 ¹² / cm ² . However, for example, when an n-type SOI-MOSFET is formed, phosphorus ions, arsenic ions, or the like can be applied to the predetermined impurity for adjusting the threshold voltage Vt. In this case, as the impurity implantation conditions, for example, the acceleration energy is set to about 20 KeV and the dose amount is set to about 1 × 10 ¹² / cm ² can be applied.

Next, polysilicon containing n-type impurities such as phosphorus is deposited on the surface of the SOI substrate 11 by an existing CVD method, for example, as shown in FIG. 13A, on the High-k film 23A. Then, a polysilicon film 14A is formed in the opening 103A ′. Note that the thickness of the deposited polysilicon film 14A is equal to or greater than the thickness of the dummy gate 103B, in other words, equal to or greater than the depth of the opening 103A ′. As a result, the opening 103A ′ can be completely filled with the polysilicon film 14A. In forming the polysilicon film 14A, for example, a mixed gas of SiH ₄ and PH ₃ can be used. The gas flow ratio at this time can be set to SiH ₄ : PH ₃ = 10: 1, for example. The film forming conditions can be set such that the pressure in the chamber is 0.6 Torr and the stage temperature is 620 ° C.

  Next, the polysilicon film 14A and the High-k film 23A on the dummy gate 103B are removed by, for example, an existing CMP method, so that the opening 103A ′ of the dummy gate 103B is formed as shown in FIG. That is, the gate electrode 14 having a film thickness of, for example, about 2000 mm is formed on the body region 15. Note that the High-k film 23 </ b> B remains on the side surface of the opening 103 </ b> A ′, that is, on the side surface of the gate electrode 14.

  Next, the dummy gate 103B and the High-k film 23B, the silicon nitride film 102, and the buffer oxide film 101 on the SOI substrate 11 are sequentially removed by etching, thereby adjacent to the lower part of the gate electrode 14, as shown in FIG. The element formation regions 11S and 11D are exposed, and a gate insulating film 23 made of a high-k film and having a thickness of, for example, about 10 to 50 mm is formed under the gate electrode 14, that is, over the body region 15. Note that it is preferable to use isotropic wet etching with HF to remove the dummy gate 103B which is a glass oxide film. This is because the glass oxide film 103 formed on the side surface of the gate electrode 14 is easily removed when isotropic etching is used.

  Thereafter, the source region 16s and the drain region 16d are formed using the steps according to the first embodiment (see FIGS. 9A and 9B), whereby the SOI-MOSFET 2 according to the present embodiment is manufactured.

  Subsequently, an interlayer insulating film 17 is formed by depositing silicon oxide on the formed SOI-MOSFET 2 to such an extent that it is buried. Next, an opening that exposes the gate electrode 14 and the upper surfaces of the source region 16s and the drain region 16d is formed in the interlayer insulating film 17 by using an existing photolithography method and etching method. Subsequently, by filling the formed opening with a conductor such as tungsten (W), via wiring for drawing out the electrical connection between the gate electrode 14, the source region 16 s and the drain region 16 d up to the interlayer insulating film 17. 18 is formed. At this time, the surface of the gate electrode 14, the surface of the source region 16s, and the surface of the drain region 16d exposed from the opening formed in the interlayer insulating film 17 may be silicidized to form silicide films respectively. Subsequently, after a conductor film such as copper or aluminum is formed on the interlayer insulating film 17, it is electrically connected to each via wiring 18 by patterning it using an existing photolithography process and etching process. A metal wiring 19 is formed. Thereby, SOI-MOSFET 2 having a cross-sectional structure as shown in FIG. 11 can be manufactured.

As described above, the SOI-MOSFET 2 according to this embodiment includes the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. The substrate 11, the gate insulating film 23 formed on the SOI layer 11c, the gate electrode 14 formed on the gate insulating film 23, and the first conductivity formed in the region below the end of the gate electrode 14 in the SOI layer 11c. A first conductive layer formed in a region sandwiched between a low concentration region 15b of a type (for example, p type) and the low concentration region 15b in the SOI layer 11c under the gate electrode 14, and having a higher impurity concentration than the low concentration region 15b. The first conductivity type is formed in a pair of regions sandwiching the high concentration region 15a and the low concentration region 15b in the SOI layer 11c. It has a source region 16s and a drain region 16d of the second conductivity type (for example, n-type) having the opposite polarity to (for example, p-type).

  In the method for manufacturing the SOI-MOSFET 2 according to the present embodiment, the SOI substrate 11 having the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b is used. Preparation is performed, a glass oxide film 103 is formed on the SOI layer 11c, an opening 103A ′ is formed in the glass oxide film 103 to form a dummy gate 103B, and a first region is formed in the SOI layer 11c below the end of the opening 103A ′. A low-concentration region 15b of a conductivity type (for example, p-type) is formed, and the first conductivity type (impurity concentration higher than that of the low-concentration region 15b is sandwiched between regions of the SOI layer 11c under the opening 103A ′ and the low-concentration region 15b. For example, a p-type high concentration region 15a is formed, and the opening 103A ′ is completely filled on the dummy gate 103B and in the opening 103A ′. A con film 14A is formed, the surface of the polysilicon film 14A is flattened to expose the upper surface of the dummy gate 103B, the gate electrode 14 is formed in the opening 103A ′, the dummy gate 103B is removed, and the gate in the SOI layer 11c A source region 16s and a drain region 16d of the second conductivity type (for example, n-type) are formed in a pair of regions sandwiching the electrode 14 below.

  A low concentration region 15b having a lower impurity concentration than the central portion is formed under the edge of the gate electrode 14, in other words, the impurity concentration of the edge portion in the body region 15 (also referred to as a channel formation region) under the gate electrode 14 is set to the central portion. Since the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 15 is relaxed as in the first embodiment, the generation of hot carriers in this portion is reduced. be able to. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 15 can be reduced, and hot carriers generated in the body region 15 can be efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 2 can be suppressed. Further, the low concentration region 15b is a region having a channel concentration lower than that of the high concentration region 15a located at the substantially central portion under the gate electrode 14. However, the low concentration region 15b according to the present embodiment is a region having a lower impurity concentration than the high concentration region 15a. That is, the low concentration region 15b is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a low concentration region 15b is a region where variation in threshold voltage caused by counter doping is avoided, and as a result, variation in threshold voltage of the SOI-MOSFET 2 can be suppressed.

  Further, the gate electrode 14 according to the present embodiment is formed by removing the polysilicon film 14A deposited to the same thickness as the dummy gate 103B up to the upper surface of the dummy gate 103B by CMP, as in the first embodiment. The For this reason, even when the gate electrode 14 having a long gate length is formed, the height of the gate electrode 14 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

  In the present embodiment, as in the first embodiment, the high-concentration region 15a and the low-concentration region 15b have the SOI substrate 11 on which the dummy gate 103B having the opening 103A ′ is formed in a predetermined direction (ion implantation direction). The first conductivity type (for example, p-type) impurity is implanted through the opening 103A ′ from the ion implantation direction while rotating at a predetermined angle (θ). For this reason, it is not necessary to counter-dope the body region 15 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 2 can be adjusted more easily than the counter dope method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used.

  The predetermined angle (θ) at this time is a value obtained by subtracting twice the thickness of the High-k film 23A from the length of the opening 103A ′ in the gate length direction, where L is the thickness of the dummy gate 103B. In this case, like the first embodiment, it is set within the range satisfying the above-described expression 1. By setting the predetermined angle (θ) within a range that satisfies the above conditions, the shadow of the dummy gate 103B does not extend to substantially the center of the body region 15 during impurity implantation for adjusting the threshold voltage Vt. Accordingly, the width in the gate length direction of the low concentration region 15b does not depend on the length in the gate length direction of the opening 103A ′ of the dummy gate 103B, that is, the gate length, and only the height H and the incident angle θ of the dummy gate 103B. Determined by For this reason, in the present embodiment, the threshold voltage Vt of the SOI-MOSFET 2 can be controlled only by the amount of impurities to be implanted.

  In the present embodiment, as in the first embodiment, the length of the low concentration region 15b in the gate length direction is not less than one fifth and not more than one third of the length of the gate electrode 14 in the gate length direction. It is preferable to set as follows.

  In this embodiment, the gate insulating film 23 is an insulating film having a relative dielectric constant higher than that of the silicon oxide film, for example, a High-k film. By using such a High-k film for the gate insulating film 23, the effect of suppressing leakage current can be enhanced. For this reason, the gate insulating film 23 can be made thinner.

  Next, Example 3 of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment or the second embodiment.

Configuration FIG. 15 is a diagram showing a schematic configuration of an SOI-MOSFET 3 which is a semiconductor device according to the present embodiment. FIG. 15 is a cross-sectional view of the SOI-MOSFET 3 cut along a plane perpendicular to the gate width direction.

  As shown in FIG. 15, the SOI-MOSFET 3 has the same configuration as the SOI-MOSFET 1 according to the first embodiment, in which the gate electrode 14 is replaced with the gate electrode 34 and the body region 15 is replaced with the body region 35.

  As in the first embodiment, the gate electrode 34 is a polysilicon film having conductivity by containing a predetermined impurity (preferably an n-type impurity), for example, and is formed on the gate insulating film 13. Moreover, the film thickness can be about 2000 mm, for example. However, the gate electrode 34 according to the present embodiment has a sidewall functioning as a protective film for protecting the low concentration region 35b from impurity implantation when forming the high concentration region 35a in a manufacturing process described later (a side wall 34B described later). And a polysilicon film (corresponding to a polysilicon film 34D described later) formed by filling the opening 103A in which the side wall 34B is formed with conductive polysilicon. A method for forming such a gate electrode 34 will be described in detail later.

The body region 35 is a region into which a predetermined impurity is implanted in order to control the threshold voltage Vt of the SOI-MOSFET 3 as in the first embodiment. Therefore, in this embodiment, this is a region into which p-type impurities (for example, boron ions) are implanted. The body region 35 includes a high concentration region 35 a formed at substantially the center of the body region 35 and a low concentration region 35 b formed at the end of the body region 35. However, in this embodiment, as described above, the side wall 34B is used to realize the impurity concentration difference between the high concentration region 35a and the low concentration region 35b. Therefore, in this embodiment, the length in the gate length direction of the low concentration region 35b can be arbitrarily set by the width of the sidewall 34B in the gate length direction, and the high concentration region 35a and the low concentration region 35b can be set. It is possible to arbitrarily set the respective densities. For example, the impurity concentration of the high concentration region 35a is about 1 × 10 ¹⁸ / cm ³ , and the impurity concentration of the low concentration region 35b is about 1 × 10 ¹⁷ / cm ³ , for example.

  In this way, the source region 16 s is configured such that the impurity concentration of the high concentration region 35 a in the body region 35 and the impurity concentration of the low concentration region 35 b in the body region 35 can be arbitrarily set independently. Since the electric field in the vicinity of the junction between / drain region 16d and body region 35 can be further relaxed, the generation of hot carriers in this portion can be further reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 35 can be further reduced, and hot carriers generated in the body region 35 are more efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 3 can be further suppressed.

  The impurity concentration in the low concentration region 35b is preferably less than or equal to half the impurity concentration in the high concentration region 35a. With such a value, the Schottky barrier on the source region 16s side can be reduced, so that hot carriers generated in the body region 35 can be efficiently extracted from the source region 16s side. It becomes possible to suppress the floating effect.

  Since other configurations are the same as those of the SOI-MOSFET 1 according to the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 3 according to the present embodiment will be described in detail with reference to the drawings. 16 to 19 are process diagrams showing a method for manufacturing the SOI-MOSFET 3. In the manufacturing method according to the present embodiment, the steps until the dummy gate 103B is formed on the SOI substrate 11 (see FIGS. 3A to 4A) are the same as in the first embodiment. Then, detailed explanation is omitted. Further, in the manufacturing method according to the present embodiment, the steps after the gate electrode 34 is formed in the opening 103A of the dummy gate 103B (see FIGS. 8B to 9B) are the same as those in the first embodiment. Therefore, detailed description is omitted here.

  In this manufacturing method, when the dummy gate 103B is formed on the SOI substrate 11 using the steps according to the first embodiment (see FIGS. 3A to 4A), the element exposed below the opening 103A is next formed. By thermally oxidizing the surface of the formation region 11A, as shown in FIG. 16A, the gate insulating film 13 made of a silicon oxide film having a thickness of, for example, about 20 to 50 mm is formed on the exposed surface of the element formation region 11A. To do. In addition, as thermal oxidation conditions at the time of forming the gate insulating film 13, the heating temperature can be set to 850 ° C., for example, and the heating time can be set to 20 minutes, for example.

Next, using the dummy gate 103B as a mask, a predetermined impurity (p-type ions in this example) for adjusting the threshold voltage Vt is applied from the opening 103A of the dummy gate 103B to the element formation region 11A through the gate insulating film 13. By implanting, as shown in FIG. 16B, a low concentration region 35A having an impurity concentration equivalent to that of the low concentration region 35b is formed under the opening 103A. In this step, for example, boron ions (including boron difluoride ions) can be applied to the predetermined impurities for adjusting the threshold voltage Vt. As the impurity implantation conditions, for example, the acceleration energy is set to about 20 KeV (kiloelectron volts) and the dose amount is set to about 1 × 10 ¹² / cm ² . However, for example, when forming a p-type SOI-MOSFET, phosphorus ions, arsenic ions, or the like can be applied to the predetermined impurity for adjusting the threshold voltage Vt. In this case, as the impurity implantation conditions, for example, the acceleration energy is set to about 15 to 20 KeV and the dose amount is set to about 1 × 10 ¹² / cm ² can be applied.

  Next, polysilicon containing n-type impurities such as phosphorus is deposited on the surface of the SOI substrate 11 by the existing CVD method, for example, as shown in FIG. A polysilicon film 34A having a thickness of, for example, about 250 mm is formed. At this time, a polysilicon film 34A having a thickness of, for example, about 250 mm is also formed on the side surface in the opening 103A and the gate insulating film 13.

Next, by patterning the polysilicon film 34A on the dummy gate 103B and in the opening 103A by, for example, existing anisotropic dry etching, as shown in FIG. 17B, on the side surface in the opening 103A, A sidewall 34B having a maximum width in the gate length direction of, for example, about 250 mm is formed. In this case, for example, a mixed gas of HBr gas and O ₂ gas can be used as the etching gas for the anisotropic dry etching. The flow rate ratio at this time can be, for example, HBr: O ₂ = 100: 3.

Next, using the dummy gate 103B and the sidewall 34B as a mask, a predetermined impurity (p-type in this example) for adjusting the threshold voltage Vt enters the element formation region 11A through the gate insulating film 13 from the opening 103A of the dummy gate 103B. As shown in FIG. 18A, a high concentration region 35a is formed at the approximate center of the low concentration region 35A. At this time, a low concentration region 35b is formed at the end of the body region 35 as the remainder of the low concentration region 35A. In this step, for example, boron ions (including boron difluoride ions) can be applied to the predetermined impurities for adjusting the threshold voltage Vt. As the impurity implantation conditions, for example, the acceleration energy is set to about 20 KeV (kiloelectron volts) and the dose amount is set to about 1 × 10 ¹² / cm ² . However, for example, when forming a p-type SOI-MOSFET, phosphorus ions, arsenic ions, or the like can be applied to the predetermined impurity for adjusting the threshold voltage Vt. In this case, as the impurity implantation conditions, for example, the acceleration energy is set to about 15 to 20 KeV and the dose amount is set to about 1 × 10 ¹² / cm ² can be applied.

  Next, polysilicon containing n-type impurities such as phosphorus is deposited on the surface of the SOI substrate 11 by the existing CVD method, for example, on the dummy gate 103B and this as shown in FIG. A polysilicon film 34C is formed in the opening 103A. The deposited polysilicon film 34C has a thickness equal to or greater than the thickness of the dummy gate 103B, in other words, equal to or greater than the depth of the opening 103A. As a result, the opening 103A can be completely filled with the sidewall 34B and the polysilicon film 34C.

  Next, by removing the polysilicon film 34C on the dummy gate 103B by, for example, an existing CMP method, the sidewall is formed in the opening 103A of the dummy gate 103B, that is, on the body region 35 as shown in FIG. A gate electrode 34 made of the polysilicon film 34D which is the remainder of the polysilicon film 34C is formed.

  Thereafter, the element formation regions 11D and 11S sandwiching the gate electrode 34 under the gate electrode 34 are exposed using the steps according to the first embodiment (see FIGS. 8B to 9B), and then predetermined impurities are implanted into these. Thus, the source region 16s and the drain region 16d are formed. Thereby, the SOI-MOSFET 3 according to the present embodiment is manufactured.

  Subsequently, an interlayer insulating film 17 is formed by depositing silicon oxide on the formed SOI-MOSFET 3 to such an extent that it is buried. Next, an opening that exposes the upper surface of the gate electrode 34 and the source region 16s and the drain region 16d is formed in the interlayer insulating film 17 by using an existing photolithography method and etching method. Subsequently, by filling the formed opening with a conductor such as tungsten (W), via wiring for drawing out the electrical connection between the gate electrode 34, the source region 16 s and the drain region 16 d to the interlayer insulating film 17. 18 is formed. At this time, the surface of the gate electrode 34, the surface of the source region 16s, and the surface of the drain region 16d exposed from the opening formed in the interlayer insulating film 17 may be silicided to form a silicide film respectively. Subsequently, after a conductor film such as copper or aluminum is formed on the interlayer insulating film 17, it is electrically connected to each via wiring 18 by patterning it using an existing photolithography process and etching process. A metal wiring 19 is formed. Thereby, SOI-MOSFET 3 having a cross-sectional structure as shown in FIG. 15 can be manufactured.

As described above, the SOI-MOSFET 3 according to this embodiment includes the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. The substrate 11, the gate insulating film 13 formed on the SOI layer 11c, the gate electrode 34 formed on the gate insulating film 13, and the first conductivity formed in the region under the edge of the gate electrode 34 in the SOI layer 11c. A first conductive layer formed in a region sandwiched between a low concentration region 35b of a type (for example, p type) and the low concentration region 35b in the SOI layer 11c under the gate electrode 34, and having a higher impurity concentration than the low concentration region 35b. The first conductivity type is formed in a pair of regions sandwiching the high concentration region 35a and the low concentration region 35b in the SOI layer 11c. It has a source region 16s and a drain region 16d of the second conductivity type (for example, n-type) having a polarity opposite to that of (for example, p-type).

  In the method for manufacturing the SOI-MOSFET 3 according to the present embodiment, the SOI substrate 11 having the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b is used. A glass oxide film 103 is formed on the SOI layer 11c, an opening 103A is formed in the glass oxide film 103 to form a dummy gate 103B, and a first conductivity type is formed in a region below the edge of the opening 103A in the SOI layer 11c. A low-concentration region 35b (for example, p-type) is formed, and the first conductivity type (for example, p-type) is interposed between the low-concentration region 35b and the impurity concentration higher than that of the low-concentration region 35b. ) To form a high concentration region 35a and completely fill the opening 103A on the dummy gate 103B and in the opening 103A. B and a polysilicon film 34C are formed, and the surface of the polysilicon film 34C is planarized to expose the upper surface of the dummy gate 103B, thereby forming the gate electrode 34 in the opening 103A, removing the dummy gate 103B, and removing the SOI layer 11c. A source region 16s and a drain region 16d of the second conductivity type (for example, n-type) are formed in a pair of regions sandwiching the gate electrode 34 below.

  A low concentration region 35b having a lower impurity concentration than the central portion is formed under the edge of the gate electrode 34. In other words, the impurity concentration of the edge portion in the body region 35 (also referred to as a channel formation region) under the gate electrode 34 is set to the central portion. Since the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 35 is relaxed, the generation of hot carriers in this portion can be reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 35 can be reduced, and hot carriers generated in the body region 35 can be efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 3 can be suppressed. Further, the low concentration region 35b is a region having a channel concentration lower than that of the high concentration region 35a located in the substantially central portion under the gate electrode 34. However, the low concentration region 35b according to the present embodiment is a region having a lower impurity concentration than the high concentration region 35a. That is, the low concentration region 35b is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a low concentration region 35b is a region where variation in threshold voltage caused by counter doping is avoided, and as a result, variation in threshold voltage of the SOI-MOSFET 3 can be suppressed.

  Further, the gate electrode 34 according to the present embodiment is formed by removing the polysilicon film 34C deposited to the same thickness as the dummy gate 103B to the upper surface of the dummy gate 103B by CMP. For this reason, even when the gate electrode 34 having a long gate length is formed, the height of the gate electrode 34 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

  In this embodiment, the sidewall 34B is formed on the side surface of the opening 103A. The low-concentration region 35b is formed by implanting a first conductivity type (for example, p-type) impurity into the SOI layer 11c through the opening 103A using the dummy gate 103B as a mask, and the high-concentration region 35a is formed by a dummy gate. The first conductivity type (for example, p-type) impurity is implanted into the SOI layer 11c through the opening 103A while using the 103B and the sidewall 34B as a mask. Therefore, it is not necessary to counter-dope the body region 35 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 3 can be adjusted more easily than the counter dope method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used. Further, since the high concentration region 35a is formed in a separate process using the sidewall 34B, the impurity concentration of each of the high concentration region 35a and the low concentration region 35b can be arbitrarily set. As a result, the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 35 can be further relaxed, and the generation of hot carriers in this portion can be further reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 35 can be further reduced, and hot carriers generated in the body region 35 are more efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 3 can be further suppressed.

  The impurity concentration in the low concentration region 35b is preferably less than or equal to half the impurity concentration in the high concentration region 35a. With such a value, the Schottky barrier on the source region 16s side can be reduced, so that hot carriers generated in the body region 35 can be efficiently extracted from the source region 16s side. It becomes possible to suppress the floating effect.

  Further, the sidewall 34B according to the present embodiment is formed by forming a polysilicon film 34C that does not completely fill the opening 103A on the dummy gate 103B and in the opening 103A, and anisotropically etching this polysilicon film 34C. I can do it.

  In this embodiment, the length in the gate length direction of the low-concentration region 35b is set to be one fifth to one third of the length of the gate electrode 34 in the gate length direction. preferable.

  Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as any one of the first to third embodiments.

Configuration FIG. 20 is a diagram showing a schematic configuration of an SOI-MOSFET 4 which is a semiconductor device according to the present embodiment. FIG. 20 is a cross-sectional view of the SOI-MOSFET 4 cut along a plane perpendicular to the gate width direction.

  As shown in FIG. 20, the SOI-MOSFET 4 has the same configuration as that of the SOI-MOSFET 1 according to the first embodiment except that the gate insulating film 13 is replaced with a gate insulating film 43 composed of a buffer oxide film 43a and a silicon nitride film 43b. Yes.

  The buffer oxide film 43a is an adhesion layer for bringing the upper silicon nitride film 43b and the SOI layer 11c into close contact, and is, for example, a silicon oxide film having a thickness of about 10 to 50 mm.

  The silicon nitride film 43 b is the main configuration of the gate insulating film 43. The film thickness is, for example, about 20 to 50 mm. The silicon nitride film 43b is an insulating film formed by patterning the silicon nitride film 43B used as a stopper film for limiting the etching amount (depth) when patterning the glass oxide film 103 in the manufacturing process. is there. That is, in this embodiment, the gate insulating film 43 is formed using the silicon nitride film 43B used as the stopper film.

  In this manner, by forming the gate insulating film 43 using the silicon nitride film 43B used as the stopper film, a process for separately forming the gate insulating film is not required, so that the manufacturing method can be simplified. . As a result, the manufacturing cost can be reduced.

  Since other configurations are the same as those of the SOI-MOSFET 1 according to the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 4 according to the present embodiment will be described in detail with reference to the drawings. 21 and 22 are process diagrams showing a method for manufacturing the SOI-MOSFET 4. In the manufacturing method according to the present embodiment, the process until the element formation region 11A is partitioned by forming the element isolation insulating film 12 on the SOI layer 11c in the SOI substrate 11 (FIGS. 3A and 3B). However, detailed description thereof is omitted here. Further, in the manufacturing method according to the present embodiment, the steps after forming the polysilicon film 14A for forming the gate electrode 14 on the dummy gate 103B and in the opening 103A thereof (see FIGS. 7B to 8B). ) Is the same as that of the first embodiment, and detailed description thereof is omitted here.

  In this manufacturing method, when the SOI layer 11c in the SOI substrate 11 is partitioned into a plurality of element formation regions 11A using the steps according to the first embodiment (see FIGS. 3A and 3B), the SOI layer The surface of 11c is thermally oxidized to form a buffer oxide film 43A thereon. This buffer oxide film 43A is an adhesion layer for closely adhering the silicon nitride film 43B to be formed next and the SOI substrate 11, and is a silicon oxide film having a thickness of about 10 to 50 mm, for example. Subsequently, a silicon nitride film 43B having a thickness of, for example, about 20 to 50 mm is formed on the buffer oxide film 43A. As described above, the silicon nitride film 43B is a stopper film for limiting the etching amount (depth) when patterning the relatively thick glass oxide film 103 to be formed next. Therefore, a film (a silicon nitride film in this example) that has a sufficient selection ratio with respect to the glass oxide film 103 is used for this film. Subsequently, a glass oxide film (NSG film) 103 having a film thickness of, for example, about 2000 mm is formed on the silicon nitride film 43B. Subsequently, the upper surface of the glass oxide film 103 formed as described above is planarized by using, for example, a CMP method. Thus, as shown in FIG. 21A, the buffer oxide film 43A, the silicon nitride film 43B, and the glass oxide film 103 are sequentially stacked on the SOI layer 11c. The formation conditions of the buffer oxide film 43A, the silicon nitride film 43B, and the glass oxide film 103 can be the same as those of the buffer oxide film 101, the silicon nitride film 102, and the glass oxide film 103 in the first embodiment.

  Next, a predetermined resist solution is spin-coated on the glass oxide film 103, and after passing through an existing photolithography process, on a region where the gate electrode 14 is formed in a later step, that is, on a region where the body region 15 is formed. A resist pattern R11 having an opening is formed in the glass oxide film 103. Subsequently, the glass oxide film 103 is etched using the resist pattern R11 as a mask, thereby forming an opening 103A in the glass oxide film 103 on the region where the body region 15 is to be formed, as shown in FIG. To do. As a result, the glass oxide film 103 becomes a so-called blank pattern (dummy gate 103B) obtained by inverting the pattern of the gate electrode 14, and the region where the gate electrode 14 is formed in the element formation region 11A of the SOI layer 11c is exposed. Is done.

  Next, using the dummy gate 103B as a mask, a predetermined impurity (in this example, nt) for adjusting the threshold voltage Vt enters the element formation region 11A from the opening 103A of the dummy gate 103B through the silicon nitride film 43B and the buffer oxide film 43A. The body region 15 is formed under the opening 103A. At this time, the predetermined impurity for adjusting the threshold voltage Vt is implanted in an oblique direction with respect to the surface of the SOI substrate 11 as in the first embodiment. As a result, as shown in FIG. 22, a body region 15 including a high concentration region 15a and a low concentration region 15b is formed in the element formation region 11A, and the region below the dummy gate 103B and in the body region 15 is formed. An element formation region 11S in which a source region 16s is formed in a later step is formed in a region in contact with one end, and an element formation region 11D in which a drain region 16d is formed in a later step in a region in contact with the other end. .

  Thereafter, the gate electrode 14, the source region 16s and the drain region 16d are formed using the steps according to the first embodiment (see FIGS. 7B to 9B), and the silicon nitride film 43B and the buffer oxide film 43A are formed. By patterning to form a gate insulating film 43 made of a silicon nitride film 43b and a buffer oxide film 43a, the SOI-MOSFET 4 according to this embodiment is manufactured. The silicon nitride film 43B and the buffer oxide film 43A other than on the body region 15 can be removed by the same method as the silicon nitride film 102 and the buffer oxide film 101 in the first embodiment.

  Subsequently, an interlayer insulating film 17 is formed by depositing silicon oxide on the formed SOI-MOSFET 4 so as to be buried. Next, an opening that exposes the gate electrode 14 and the upper surfaces of the source region 16s and the drain region 16d is formed in the interlayer insulating film 17 by using an existing photolithography method and etching method. Subsequently, by filling the formed opening with a conductor such as tungsten (W), via wiring for drawing out the electrical connection between the gate electrode 14, the source region 16 s and the drain region 16 d up to the interlayer insulating film 17. 18 is formed. At this time, the surface of the gate electrode 14, the surface of the source region 16s, and the surface of the drain region 16d exposed from the opening formed in the interlayer insulating film 17 may be silicidized to form silicide films respectively. Subsequently, after a conductor film such as copper or aluminum is formed on the interlayer insulating film 17, it is electrically connected to each via wiring 18 by patterning it using an existing photolithography process and etching process. A metal wiring 19 is formed. Thereby, SOI-MOSFET 4 having a cross-sectional structure as shown in FIG. 20 can be manufactured.

As described above, the SOI-MOSFET 4 according to this embodiment includes the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. The substrate 11, the gate insulating film 43 formed on the SOI layer 11c, the gate electrode 14 formed on the gate insulating film 43, and the first conductivity formed in the region below the end of the gate electrode 14 in the SOI layer 11c. A first conductive layer formed in a region sandwiched between a low concentration region 15b of a type (for example, p type) and the low concentration region 15b in the SOI layer 11c under the gate electrode 14, and having a higher impurity concentration than the low concentration region 15b. The first conductivity type is formed in a pair of regions sandwiching the high concentration region 15a and the low concentration region 15b in the SOI layer 11c. It has a source region 16s and a drain region 16d of the second conductivity type (for example, n-type) having the opposite polarity to (for example, p-type).

  In the method for manufacturing the SOI-MOSFET 4 according to this embodiment, the SOI substrate 11 having the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b is used. A glass oxide film 103 is formed on the SOI layer 11c, an opening 103A is formed in the glass oxide film 103 to form a dummy gate 103B, and a first conductivity type is formed in a region below the edge of the opening 103A in the SOI layer 11c. A low-concentration region 15b (for example, p-type) is formed, and the first conductivity type (for example, p-type) is interposed between the low-concentration region 15b in the region below the opening 103A in the SOI layer 11c and has a higher impurity concentration than the low-concentration region 15b. ) High-concentration region 15a, and the polysilicon film 1 completely filling the opening 103A on the dummy gate 103B and in the opening 103A A is formed, the surface of the polysilicon film 14A is flattened to expose the upper surface of the dummy gate 103B, thereby forming the gate electrode 14 in the opening 103A, removing the dummy gate 103B, and under the gate electrode 14 in the SOI layer 11c. A source region 16s and a drain region 16d of the second conductivity type (for example, n-type) are formed in a pair of regions sandwiching.

  A low concentration region 15b having a lower impurity concentration than the central portion is formed under the edge of the gate electrode 14, in other words, the impurity concentration of the edge portion in the body region 15 (also referred to as a channel formation region) under the gate electrode 14 is set to the central portion. Since the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 15 is relaxed as in the first embodiment, the generation of hot carriers in this portion is reduced. be able to. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 15 can be reduced, and hot carriers generated in the body region 15 can be efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 4 can be suppressed. Further, the low concentration region 15b is a region having a channel concentration lower than that of the high concentration region 15a located at the substantially central portion under the gate electrode 14. However, the low concentration region 15b according to the present embodiment is a region having a lower impurity concentration than the high concentration region 15a. That is, the low concentration region 15b is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a low concentration region 15b is a region where variation in threshold voltage caused by counter doping is avoided, and as a result, variation in threshold voltage of the SOI-MOSFET 4 can be suppressed.

  Further, the gate electrode 14 according to the present embodiment is formed by removing the polysilicon film 14A deposited to the same thickness as the dummy gate 103B up to the upper surface of the dummy gate 103B by CMP. Therefore, as in the first embodiment, even when the gate electrode 14 having a long gate length is formed, the height of the gate electrode 14 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

  Further, in this embodiment, the high concentration region 15a and the low concentration region 15b tilt the SOI substrate 11 on which the dummy gate 103B having the opening 103A is formed by a predetermined angle (θ) with respect to a predetermined direction (ion implantation direction). The first conductivity type (for example, p-type) impurity is implanted through the opening 103A from the ion implantation direction while rotating in a state. Therefore, as in the first embodiment, it is not necessary to counter-dope the body region 15 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 4 can be adjusted more easily than the counter dope method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used.

  Further, the predetermined angle (θ) at this time is set within a range satisfying the above-described expression 1 when the film thickness of the dummy gate 103B is H and the length of the opening 103A in the gate length direction is L. . By setting the predetermined angle (θ) within a range that satisfies the above conditions, the shadow of the dummy gate 103B is substantially at the center of the body region 15 at the time of impurity implantation for adjusting the threshold voltage Vt, as in the first embodiment. Does not extend to. Therefore, the width in the gate length direction of the low-concentration region 15b does not depend on the length in the gate length direction of the opening 103A of the dummy gate 103B, that is, the gate length, and only by the height H of the dummy gate 103B and the incident angle θ. It is determined. Therefore, in this embodiment, the threshold voltage Vt of the SOI-MOSFET 4 can be controlled only by the amount of impurities to be implanted.

  In the present embodiment, as in the first embodiment, the length of the low concentration region 15b in the gate length direction is not less than one fifth and not more than one third of the length of the gate electrode 14 in the gate length direction. It is preferable to set as follows.

  In this embodiment, a silicon nitride film 43B having an etching rate lower than that of the dummy pattern 103B under a predetermined condition is formed on the SOI layer 11c, and a portion other than the portion under the gate electrode 14 in the silicon nitride film 43B is removed. A gate insulating film 43 including a silicon nitride film 43 b is formed under the gate electrode 14. The dummy gate 103B is formed on the silicon nitride film 43B. In this manner, by forming the gate insulating film 43 using the silicon nitride film 43B used as the stopper film, a process for separately forming the gate insulating film is not required, so that the manufacturing method can be simplified. . As a result, the manufacturing cost can be reduced.

  Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to fourth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of any one of the first to fourth embodiments.

Configuration FIG. 23 is a diagram showing a schematic configuration of an SOI-MOSFET 5 which is a semiconductor device according to the present embodiment. FIG. 23 shows a cross-sectional view of the SOI-MOSFET 5 taken along a plane perpendicular to the gate width direction.

  As shown in FIG. 23, the SOI-MOSFET 5 has the same configuration as that of the SOI-MOSFET 1 according to the first embodiment, and sidewalls 57 respectively formed on both side surfaces of the gate electrode 14 and below the sidewalls 57 in the SOI layer 11c. It further has an LDD (Lightly Doped Drain) region (low concentration diffusion region) 56 formed in each region.

  The sidewall 57 is a silicon oxide film having a thickness in the gate length direction of about 1000 mm, for example. The sidewall 57 is a spacer for defining the distance between the end of the body region 15 and the source region 16s or the drain region 16d.

The LDD region 56 is implanted and diffused so that impurities having the same polarity as the impurities implanted into the source region 16s and the drain region 16d, for example, n-type impurities, have a concentration of about 1 × 10 ¹⁹ / cm ^3, for example. It is a low concentration diffusion region. By providing such an LDD region 56, the electric field between the source region 16s or drain region 16d and the body region 15 can be relaxed.

  Since other configurations are the same as those of the SOI-MOSFET 1 according to the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 5 according to the present embodiment will be described in detail with reference to the drawings. 24 and 25 are process diagrams showing a method for manufacturing the SOI-MOSFET 5. In the manufacturing method according to the present embodiment, the steps until the gate electrode 14 is formed on the body region 15 in the SOI substrate 11 (see FIGS. 3A to 8B) are the same as those in the first embodiment. Therefore, detailed description is omitted here.

  In this manufacturing method, when the gate electrode 14 is formed on the body region 15 in the SOI layer 11c using the process according to the first embodiment (see FIGS. 3A and 8B), the upper surface of the SOI layer 11c is then formed. The entire surface is thermally oxidized, for example, to form a mask oxide film 501 at least on the exposed surface of the element formation regions 11S and 11D, as shown in FIG. This mask oxide film 501 is a film for reducing damages received by the element formation regions 11S and 11D due to impurity implantation when forming the LDD region 56A in a later process. For example, the mask oxide film 501 is a silicon oxide film having a thickness of about 100 mm. is there. In the thermal oxidation at the time of forming the mask oxide film 501, the heating temperature can be set to 850 ° C., for example, and the heating time can be set to 30 minutes, for example.

Next, predetermined impurities such as boron ions (including boron difluoride ions) are implanted into the entire upper surface of the SOI substrate 11. At this time, since the gate electrode 14 and the element isolation insulating film 12 serve as a mask, predetermined impurities are implanted into the element formation regions 11S and 11D in a self-aligning manner. As a result, as shown in FIG. 24A, an LDD region 56A having an impurity concentration similar to that of the LDD region 56 described above is formed in the pair of element formation regions 11S and 11D sandwiching the body region 15 below the gate electrode 14. It is formed. In the ion implantation at the time of forming the LDD region 56A, a condition in which the dose is set to about 1 × 10 ¹³ / cm ² and the acceleration energy is set to about 10 KeV can be applied.

Next, after removing the mask oxide film 501 on the surface of the SOI substrate 11, as shown in FIG. 24B, the silicon oxide film 57A having a film thickness of, eg, about 1000 mm is formed by the existing CVD method, for example. It is formed on the upper and gate electrodes 14 and on the side surfaces of the gate electrode 14. In forming the silicon oxide film 57A, for example, a mixed gas of TEOS and O ₂ can be used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

Next, the silicon oxide film 57A formed on the SOI substrate 11, the gate electrode 14, and the side surface of the gate electrode 14 is subjected to anisotropic dry etching, so that both side surfaces of the gate electrode 14 are formed as shown in FIG. In addition, a sidewall 57 having a thickness in the gate length direction of, for example, about 1000 mm is formed. In this anisotropic dry etching, for example, a mixed gas of CHF ₃ , CF ₄ and O ₂ can be used as an etching gas. The gas flow rate ratio at this time can be set to CHF ₃ : CF ₄ : O ₂ = 100: 100: 3.

Next, a mask oxide film 502 is formed on at least the exposed LDD region 56A by, for example, thermally oxidizing the entire upper surface of the SOI layer 11c. The mask oxide film 502 is a film for reducing damage to the LDD region 56A due to impurity implantation when forming the source region 16s and the drain region 16d in a later step. For example, the silicon oxide film having a thickness of about 100 mm It is. Subsequently, predetermined impurities such as boron ions (including boron difluoride ions) are implanted into the entire upper surface of the SOI substrate 11. At this time, since the gate electrode 14, the sidewall 57, and the element isolation insulating film 12 serve as a mask, a predetermined impurity is self-aligned from the body region 15 in the LDD region 56A (in this example, the gate length of the sidewall 57). (Thickness in the direction) is injected into a remote area. Subsequently, the impurity implanted into the LDD region 56A is thermally diffused. As a result, as shown in FIG. 25B, a pair of LDD regions 56 sandwiching the body region 15 under the gate electrode 14 is formed, and a pair of LDD regions 56 sandwiching the body region 15 and the pair of LDD regions 56 therebetween. A source region 16s and a drain region 16d are formed. In the thermal oxidation when forming the mask oxide film 502, the heating temperature can be set to 850 ° C., for example, and the heating time can be set to 30 minutes, for example. In addition, in the ion implantation for forming the source region 16s and the drain region 16d, a condition in which the dose is set to about 1 × 10 ¹⁵ / cm ² and the acceleration energy is set to about 10 KeV can be applied. Further, for the heat treatment at the time of diffusion, for example, lamp annealing with a heating temperature of 1000 ° C. and a heating time of 10 seconds can be applied.

  Through the above steps, the SOI-MOSFET 5 according to this embodiment is manufactured.

  Thereafter, an interlayer insulating film 17 is formed by depositing silicon oxide on the formed SOI-MOSFET 5 to such an extent that it is buried. Next, an opening that exposes the gate electrode 14 and the upper surfaces of the source region 16s and the drain region 16d is formed in the interlayer insulating film 17 by using an existing photolithography method and etching method. Subsequently, by filling the formed opening with a conductor such as tungsten (W), via wiring for drawing out the electrical connection between the gate electrode 14, the source region 16 s and the drain region 16 d up to the interlayer insulating film 17. 18 is formed. At this time, the surface of the gate electrode 14, the surface of the source region 16s, and the surface of the drain region 16d exposed from the opening formed in the interlayer insulating film 17 may be silicidized to form silicide films respectively. Subsequently, after a conductor film such as copper or aluminum is formed on the interlayer insulating film 17, it is electrically connected to each via wiring 18 by patterning it using an existing photolithography process and etching process. A metal wiring 19 is formed. Thereby, SOI-MOSFET 5 having a cross-sectional structure as shown in FIG. 23 can be manufactured.

As described above, the SOI-MOSFET 5 according to this embodiment includes the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. The substrate 11, the gate insulating film 13 formed on the SOI layer 11c, the gate electrode 14 formed on the gate insulating film 13, and the first conductivity formed in the region below the end of the gate electrode 14 in the SOI layer 11c. A first conductive layer formed in a region sandwiched between a low concentration region 15b of a type (for example, p type) and the low concentration region 15b in the SOI layer 11c under the gate electrode 14, and having a higher impurity concentration than the low concentration region 15b. The first conductivity type is formed in a pair of regions sandwiching the high concentration region 15a and the low concentration region 15b in the SOI layer 11c. It has a source region 16s and a drain region 16d of the second conductivity type (for example, n-type) having a polarity opposite to that of (for example, p-type).

  In the method for manufacturing the SOI-MOSFET 5 according to the present embodiment, the SOI substrate 11 having the support substrate 11a, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b is used. A glass oxide film 103 is formed on the SOI layer 11c, an opening 103A is formed in the glass oxide film 103 to form a dummy gate 103B, and a first conductivity type is formed in a region below the edge of the opening 103A in the SOI layer 11c. A low-concentration region 15b (for example, p-type) is formed, and the first conductivity type (for example, p-type) is interposed between the low-concentration region 15b in the region below the opening 103A in the SOI layer 11c and has a higher impurity concentration than the low-concentration region 15b. ) High-concentration region 15a, and the polysilicon film 1 completely filling the opening 103A on the dummy gate 103B and in the opening 103A A is formed, the surface of the polysilicon film 14A is flattened to expose the upper surface of the dummy gate 103B, thereby forming the gate electrode 14 in the opening 103A, removing the dummy gate 103B, and under the gate electrode 14 in the SOI layer 11c. A source region 16s and a drain region 16d of the second conductivity type (for example, n-type) are formed in a pair of regions sandwiching.

  A low concentration region 15b having a lower impurity concentration than the central portion is formed under the edge of the gate electrode 14, in other words, the impurity concentration of the edge portion in the body region 15 (also referred to as a channel formation region) under the gate electrode 14 is set to the central portion. Since the electric field in the vicinity of the junction between the source region 16s / drain region 16d and the body region 15 is relaxed, the generation of hot carriers in this portion can be reduced. As a result, the Schottky barrier at the junction between the source region 16s / drain region 16d and the body region 15 can be reduced, and hot carriers generated in the body region 15 can be efficiently extracted from the source region 16s side, for example. It becomes possible. As a result, the substrate floating effect of the SOI-MOSFET 5 can be suppressed. Further, the low concentration region 15b is a region having a channel concentration lower than that of the high concentration region 15a located at the substantially central portion under the gate electrode 14. However, the low concentration region 15b according to the present embodiment is a region having a lower impurity concentration than the high concentration region 15a. That is, the low concentration region 15b is not a region formed by counter-doping a second conductivity type impurity having a polarity opposite to that of the first conductivity type. Such a low concentration region 15b is a region where variation in threshold voltage caused by counter doping is avoided, and as a result, variation in threshold voltage of the SOI-MOSFET 5 can be suppressed.

  Further, the gate electrode 14 according to the present embodiment is formed by removing the polysilicon film 14A deposited to the same thickness as the dummy gate 103B up to the upper surface of the dummy gate 103B by CMP. For this reason, even when the gate electrode 14 having a long gate length is formed, the height of the gate electrode 14 can be made uniform. As a result, variation in transistor characteristics due to gate length can be suppressed.

  Further, in this embodiment, the high concentration region 15a and the low concentration region 15b tilt the SOI substrate 11 on which the dummy gate 103B having the opening 103A is formed by a predetermined angle (θ) with respect to a predetermined direction (ion implantation direction). The first conductivity type (for example, p-type) impurity is implanted through the opening 103A from the ion implantation direction while rotating in a state. For this reason, it is not necessary to counter-dope the body region 15 with an impurity having the opposite polarity. As a result, the threshold voltage Vt of the SOI-MOSFET 5 can be adjusted more easily than the counter-doping method. In addition, it is possible to suppress the variation in threshold voltage Vt that occurs when the counter dope method is used.

  Further, the predetermined angle (θ) at this time is set within a range satisfying the above-described expression 1 when the film thickness of the dummy gate 103B is H and the length of the opening 103A in the gate length direction is L. . By setting the predetermined angle (θ) within a range that satisfies the above conditions, the shadow of the dummy gate 103B does not extend to substantially the center of the body region 15 during impurity implantation for adjusting the threshold voltage Vt. Therefore, the width in the gate length direction of the low-concentration region 15b does not depend on the length in the gate length direction of the opening 103A of the dummy gate 103B, that is, the gate length, and only by the height H of the dummy gate 103B and the incident angle θ. It is determined. Therefore, in this embodiment, the threshold voltage Vt of the SOI-MOSFET 5 can be controlled only by the amount of impurities to be implanted.

  In the present embodiment, the length of the low concentration region 15b in the gate length direction is set to be one fifth to one third of the length of the gate electrode 14 in the gate length direction. preferable.

  The SOI-MOSFET 5 according to the present embodiment further includes a sidewall 57 formed on the side surface of the gate electrode 14 and an LDD region 56 formed in a region under the sidewall 57 in the SOI layer 11c. The source region 16s and the drain region 16d sandwich the LDD region 56 with the high concentration region 15a and the low concentration region 15b. By providing such an LDD region 56, the electric field between the source region 16s or drain region 16d and the body region 15 can be relaxed.

  In the present embodiment, the SOI-MOSFET 1 according to the first embodiment is cited and described, but the present invention is not limited to this, and for example, any of the SOI-MOSFETs 1 to 4 shown in the first to fourth embodiments is cited. Is also possible.

  In addition, the first to fifth embodiments described above are merely examples for carrying out the present invention, and the present invention is not limited to these. Various modifications of these embodiments are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

It is sectional drawing which shows schematic structure of SOI-MOSFET by Example 1 of this invention. (A) is a figure which shows the potential of the electron and the hole for every position along the gate length direction in SOI-MOSFET which does not have a low concentration area | region in a body area | region edge part, (b) is a body area | region edge part. It is a figure which shows the potential of the electron and hole for every position along the gate length direction in SOI-MOSFET by a present Example which has a low concentration area | region. It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (1). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (2). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (3). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (4). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (5). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (6). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (7). It is a figure for demonstrating the range of incident angle (theta) in this invention. It is sectional drawing which shows schematic structure of SOI-MOSFET by Example 2 of this invention. It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (8). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (9). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (10). It is sectional drawing which shows schematic structure of SOI-MOSFET by Example 3 of this invention. It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (11). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (12). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (13). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (14). It is sectional drawing which shows schematic structure of SOI-MOSFET by Example 4 of this invention. It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (15). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (16). It is sectional drawing which shows schematic structure of SOI-MOSFET by Example 5 of this invention. It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (17). It is a process figure which shows the manufacturing method of SOI-MOSFET by this invention (18).

Explanation of symbols

1, 2, 3, 4, 5 SOI-MOSFET
11 SOI substrate 11A, 11D, 11S Element formation region 11a Support substrate 11b BOX layer 11c SOI layer 12 Element isolation insulating film 13, 23, 43 Gate insulating film 14, 34 Gate electrode 14A, 34A, 34C, 34D Polysilicon film 15, 35 Body region 15a, 35a High concentration region 15b, 35b, 35A Low concentration region 16d Drain region 16s Source region 17 Interlayer insulating film 18 Via wiring 19 Metal wiring 23A, 23B High-k film 34B Side wall 43a, 43A, 101 Buffer oxidation Film 43b, 43B, 102 Silicon nitride film 56, 56A LDD region 57 Side wall 57A Silicon oxide film 103 Glass oxide film 103A, 103A ′ Opening 103B Dummy gate 104, 105 Mask oxide film 110 Ion Implanter 111 Turntable 501, 502 Mask oxide film R11 Resist pattern

Claims (14)

An SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer;
A gate insulating film formed on the semiconductor layer;
A gate electrode formed on the gate insulating film;
A first region of a first conductivity type formed in a region under the gate electrode end in the semiconductor layer;
A second region of the first conductivity type formed in a region sandwiched between the first regions in the semiconductor layer under the gate electrode, and having a higher impurity concentration than the first region;
A semiconductor device comprising: a high concentration diffusion region of a second conductivity type formed in a pair of regions sandwiching the first and second regions in the semiconductor layer and having a polarity opposite to that of the first conductivity type.   2. The semiconductor device according to claim 1, wherein the gate insulating film is an insulating film having a relative dielectric constant higher than that of a silicon oxide film.   3. The semiconductor device according to claim 1, wherein the impurity concentration of the first region is less than or equal to one half of the impurity concentration of the second region. A sidewall formed on a side surface of the gate electrode;
A low-concentration diffusion region formed in a region under the sidewall in the semiconductor layer,
4. The semiconductor device according to claim 1, wherein the pair of high concentration diffusion regions sandwich the first and second regions and the low concentration diffusion region. 5.   5. The length of the second region in the gate length direction is not less than one fifth and not more than one third of the length of the gate electrode in the gate length direction. 6. The semiconductor device according to item. Preparing an SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer;
Forming a first insulating film on the semiconductor layer;
Forming an opening in the first insulating film;
Forming a first region of a first conductivity type in a region under the opening end in the semiconductor layer;
Forming a second region of the first conductivity type sandwiched between the first regions and having a higher impurity concentration than the first region in a region under the opening in the semiconductor layer;
Forming a first conductor film completely filling the opening on the first insulating film and in the opening;
Forming a gate electrode in the opening by planarizing the surface of the first conductor film and exposing the upper surface of the first insulating film;
Removing the first insulating film;
Forming a second conductivity type high-concentration diffusion region in a pair of regions sandwiching the gate electrode under the gate electrode in the semiconductor layer.   The first and second regions rotate from the predetermined direction through the opening while rotating the SOI substrate on which the first insulating film having the opening is formed at a predetermined angle with respect to the predetermined direction. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is formed by implanting an impurity of the first conductivity type. When the film thickness of the first insulating film is H and the length of the opening in the gate length direction is L, the predetermined angle θ is

The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is set within a range satisfying the above. Further comprising forming a first sidewall on a side surface of the opening;
The first region is formed by implanting the first conductivity type impurity into the semiconductor layer through the opening while using the first insulating film as a mask.
The second region is formed by implanting the first conductivity type impurity into the semiconductor layer through the opening while using the first insulating film and the first sidewall as a mask. A method for manufacturing a semiconductor device according to claim 6. The first sidewall is formed by forming a second conductor film that does not completely fill the opening on the first insulating film and in the opening, and anisotropically etching the second conductor film. And
The method of manufacturing a semiconductor device according to claim 9, wherein the first conductor film is a conductor film including the sidewall.   The length of the second region in the gate length direction is not less than one fifth and not more than one third of the length of the gate electrode in the gate length direction. A method for manufacturing the semiconductor device according to the item. Forming a second insulating film having a relative dielectric constant higher than that of a silicon oxide film on the first insulating film and in the opening;
The method further comprises the step of forming a gate insulating film under the gate electrode by removing portions of the second insulating film formed on the first insulating film and on the side surfaces of the opening. Item 12. The method for manufacturing a semiconductor device according to any one of Items 6 to 11. Forming a third insulating film having an etching rate under a predetermined condition lower than that of the first insulating film on the semiconductor layer;
Removing a portion of the third insulating film other than under the gate electrode to form a gate insulating film under the gate electrode;
The method for manufacturing a semiconductor device according to claim 6, wherein the first insulating film is formed on the third insulating film. Forming a low concentration diffusion region by implanting the second conductivity type impurity into the semiconductor layer using the gate electrode as a mask;
Forming a fourth insulating film on the semiconductor layer and the gate electrode;
And further forming a second sidewall on the side surface of the gate electrode by anisotropic dry etching the fourth insulating film,
7. The pair of high-concentration diffusion regions are formed by implanting the second conductivity type impurity into the semiconductor layer using the gate electrode and the second sidewall as a mask. 14. A method for manufacturing a semiconductor device according to any one of items 1 to 13.

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