JP3680417B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, particularly a MOS transistor, which is a low-concentration impurity diffusion layer (hereinafter referred to as an offset) between a channel portion and a source and drain composed of a high-concentration impurity diffusion layer. Note that a high withstand voltage semiconductor device (hereinafter, abbreviated as a semiconductor device having an offset) in which the withstand voltage between the source and the drain is improved by providing a lightly doped drain (also often referred to as LDD for short) to obtain an electric field relaxation effect. )).
[0002]
[Prior art]
As a conventional method for manufacturing a semiconductor device having an offset, there are mainly two methods described below. One is a so-called side wall method for creating an offset by providing a side wall spacer on the side wall of the gate electrode, and the other is a so-called mask offset method for creating an offset by covering the gate electrode with a photoresist.
[0003]
First, the so-called side wall method will be described with reference to FIG.
[0004]
A gate insulating film 102 is formed over the semiconductor substrate 101, and then a gate electrode 103 is formed. Ion implantation 104 is performed using the gate electrode 103 as a mask to form a low-concentration impurity diffusion layer 105 in the semiconductor substrate 101 (FIG. 1a). Next, an insulating film 106 is deposited (FIG. 2b), and the insulating film 106 is removed by anisotropic etching. After the etching, the sidewall spacer 107 remains on the side wall of the gate electrode (FIG. 1c). Using the sidewall spacer 107 and the gate electrode 103 as a mask, ion implantation 108 is performed to form a high-concentration impurity diffusion layer 109. Subsequently, an interlayer insulating film is formed, a connection hole is opened in the interlayer insulating film, and a metal wiring is formed, thereby completing the semiconductor device.
[0005]
Next, a so-called mask offset method will be described with reference to FIG.
[0006]
A gate insulating film 202 is formed over the semiconductor substrate 201, and then a gate electrode 203 is formed. Ions are implanted using the gate electrode 203 as a mask to form a low-concentration impurity diffusion layer 204 in the semiconductor substrate 201 (FIG. 2a). Next, a photoresist 205 is formed so as to cover the gate electrode 203, and ion implantation 206 is performed using this as a mask to form a high-concentration impurity diffusion layer 207 (FIG. 2b). Subsequently, after removing the photoresist 205, the semiconductor device is completed in the same manner as the sidewall method described above.
[0007]
Regardless of the side wall method or mask offset method, by providing a low concentration impurity diffusion layer (offset) between the channel and the high concentration impurity diffusion layer, the horizontal electric field is alleviated and the breakdown voltage between the source and drain of the transistor is reduced. It has improved. In addition, the provision of an offset also has an effect of suppressing hot carrier injection into the gate insulating film and suppressing characteristic fluctuations of the semiconductor device.
[0008]
[Problems to be solved by the invention]
However, the side wall method has a problem that the offset, that is, the distance in the horizontal direction (direction connecting the channel and the drain) of the low-concentration impurity diffusion layer is small, and a sufficient breakdown voltage may not be obtained. That is, the magnitude of the offset is determined by the length of the side wall in the horizontal direction (the direction connecting the source and drain), and even if the horizontal length of the side wall is large, it is about the thickness of the gate electrode. There was a limit to trying to increase the size of the offset.
[0009]
Further, in the mask offset method, an withstand voltage can be improved by providing an offset of an arbitrary size, but an ion implantation mask (photoresist 205 in FIG. 2) for forming a high concentration impurity diffusion layer. Is formed by photolithography, there is a problem that misalignment occurs at the time of exposure and the magnitude of the offset changes, so that the electrical characteristics become non-uniform.
[0010]
[Means for Solving the Problems]
  The semiconductor device of the present invention includes a step of forming a gate insulating film on a semiconductor layer, a step of forming a cover layer and a gate electrode on the gate insulating film by the same process and photolithography, and the cover layer. And a step of forming a low impurity concentration diffusion layer using the gate electrode as a mask, a step of forming a spacer between the cover layer and the gate electrode, a step of removing the cover layer, and the removed cover A semiconductor device manufactured by a method for manufacturing a semiconductor device, comprising: implanting impurity ions into the semiconductor layer under the layer to form a high impurity concentration diffusion layer to be a source and drain impurity diffusion layer Per unit length in the channel length direction of the low impurity concentration diffusion layer present in the portion between the impurity diffusion layer of the source and drain and the channel The air resistance, characterized in that one of the electrical resistance of 2 minutes per unit length in the channel length direction of the channel in the case of the on state by the addition of specified voltage to the gate electrode and the drain.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the semiconductor device manufacturing method of the present invention will be described in detail with reference to FIGS.
[0012]
3 and 4 are process cross-sectional views showing a method for manufacturing a semiconductor device of the present invention. First, a first insulating film 302 was formed over the semiconductor layer 301, and then a first conductive film 303 was deposited over the first insulating film 302 (FIG. 3a). In this embodiment, the semiconductor layer 301 is single crystal silicon (Si), and the first insulating film 302 is silicon oxide (SiO 2) obtained by thermally oxidizing the surface of single crystal silicon.₂). The first insulating film 302 is a gate insulating film of a MOS transistor. Polycrystalline silicon was used for the first conductive film 303.
[0013]
Next, the first conductive film 303 was processed using one photolithography, so that the first conductive film region 304 and the second conductive film region 305 were formed at the same time. The first conductive film region 304 is a gate electrode of a MOS transistor, and the second conductive film region 305 is a region that covers a portion where a high-concentration impurity diffusion layer (source and drain of a MOS transistor) will be formed later. Hereinafter, it is abbreviated as a cover layer). Further, ion implantation was performed from above the first conductive film region 304 and the second conductive film region 305 to form a low-concentration impurity diffusion layer 306 in the semiconductor layer 301 (FIG. 3b).
[0014]
As an ion implantation condition for forming the low concentration impurity diffusion layer, the implantation amount is preferably 10.^Ten-10¹⁴(1 / cm²), More preferably 10¹²-10¹³(1 / cm²)
It is. The implantation energy is preferably 10 to 150 keV, more preferably 30 to 100 keV. The ion species is B⁺, BF₂ ⁺, P⁺And As⁺However, there is no particular limitation as long as it is a substance that can function as a donor or acceptor for the semiconductor substrate. These ion implantation conditions are an example, and are generally determined by the required breakdown voltage and capability of the MOS transistor.
[0015]
For example, if the ion species is BF₂ ⁺In this case, the injection amount is preferably 10^Ten-10¹⁴(1 / cm²), More preferably 10¹²-10¹³(1 / cm²), More preferably 4 × 10¹²-10¹³(1 / cm²). 10^Ten(1 / cm²This is because the diffusion layer resistance becomes too large and the capability as a MOS transistor is insufficient, and the desired conductivity type may not be obtained. 10¹⁴(1 / cm²This is because the electric field relaxation effect is small and a sufficient breakdown voltage cannot be secured in many cases. The implantation energy is not particularly limited, but is preferably 20 to 60 keV, more preferably 30 to 50 keV, and further preferably 40 ± 5 keV. This is because if it is less than 20 keV, impurities may not penetrate the gate insulating film. This is because if it exceeds 60 keV, it may penetrate to the mask layer for ion implantation. Of course, if such inconvenience does not occur, the implantation energy can be freely set in accordance with the required characteristics of the MOS transistor, and even in other ion species and other ion implantation processes, Are the same.
[0016]
Ion species is B⁺In this case, the injection amount is preferably 10^Ten-10¹⁴(1 / cm²), More preferably 10¹²-10¹³(1 / cm²), More preferably 4 × 10¹²-10¹³(1 / cm²). The implantation energy is not particularly limited, but is preferably 10 to 40 keV, more preferably 20 to 30 keV.
[0017]
Ion species is P⁺In this case, the injection amount is preferably 10^Ten-10¹⁴(1 / cm²), More preferably 5 × 10¹²~ 5x10¹³(1 / cm²), More preferably 10¹³~ 4x10¹³(1 / cm²). The implantation energy is not particularly limited, but is preferably 40 to 80 keV, more preferably 50 to 70 keV, and still more preferably 60 ± 5 keV.
[0018]
Ion species is As⁺In this case, the injection amount is preferably 10^Ten-10¹⁴(1 / cm²), More preferably 5 × 10¹²~ 5x10¹³(1 / cm²). The implantation energy is not particularly limited, but is preferably 40 to 80 keV, more preferably 50 to 70 keV.
[0019]
Next, a second insulating film 307 was deposited (FIG. 3c). This second insulating film 307 is a so-called spacer insulating film, a part of which becomes a spacer for forming an offset later. The second insulating film 307 is silicon oxide deposited using a vapor deposition method. Thereafter, the second insulating film 307 was gradually removed from the top using a chemical mechanical polishing (CMP) technique to expose the top of the second conductive film region 305. At this time, part of the second insulating film 307 remains between the first conductive film region 304 and the second conductive film region 305, and this is a high-concentration impurity diffusion formed later with the first conductive film region 304. A spacer 308 for separating layers (forming an offset) (FIG. 3d).
[0020]
Next, a photoresist 309 is formed so as to cover the first conductive film region 304 and the second conductive film region 305 is exposed, and then the second conductive film region 305 is removed (FIG. 3e). ). Ion implantation was performed on a portion of the semiconductor layer 301 that is not covered with the first conductive film region 304 and the spacer 308 to form a high-concentration impurity diffusion layer 310 (FIG. 4a).
[0021]
As the ion implantation conditions for forming the high-concentration impurity diffusion layer, the implantation amount is preferably 10¹⁴-10¹⁷(1 / cm²), More preferably 10¹⁵-10¹⁶(1 / cm²)
It is. The implantation energy is preferably 10 to 150 keV, more preferably 30 to 100 keV. The ion species is B⁺, BF₂ ⁺, P⁺And As⁺However, there is no particular limitation as long as it is a substance that can function as a donor or acceptor for the semiconductor substrate. These ion implantation conditions are merely examples, and are generally determined by the required breakdown voltage, capacity, and the like.
[0022]
For example, if the ion species is BF₂ ⁺In this case, the injection amount is preferably 10¹⁴-10¹⁷(1 / cm²), More preferably 10¹⁵-10¹⁶(1 / cm²), More preferably 1 × 10¹⁵~ 8x10¹⁵(1 / cm²). 10¹⁴(1 / cm²This is because the diffusion layer resistance (parasitic resistance of the source and drain) increases and the capability of the transistor may be hindered. 10¹⁷(1 / cm²This is because it is difficult to recover crystal defects due to ion implantation in a later step, and the characteristics of the transistor may be hindered due to junction leakage or the like. The implantation energy is not particularly limited, but is preferably 20 to 60 keV, more preferably 30 to 50 keV, and further preferably 40 ± 5 keV. This is because if it is less than 20 keV, impurities may not penetrate the gate insulating film. Further, if it is higher than 60 keV, it may penetrate to the mask layer for ion implantation.
[0023]
Ion species is B⁺In this case, the injection amount is preferably 10¹⁴-10¹⁷(1 / cm²), More preferably 10¹⁵-10¹⁶(1 / cm²), More preferably 1 × 10¹⁵~ 8x10¹⁵(1 / cm²). The implantation energy is not particularly limited, but is preferably 20 to 60 keV, more preferably 30 to 50 keV, and further preferably 40 ± 5 keV.
[0024]
Ion species is P⁺In this case, the injection amount is preferably 10¹⁴-10¹⁷(1 / cm²), More preferably 10¹⁵-10¹⁶(1 / cm²), More preferably 1 × 10¹⁵~ 8x10¹⁵(1 / cm²). The implantation energy is not particularly limited, but is preferably 50 to 90 keV, more preferably 60 to 80 keV, and still more preferably 70 ± 5 keV.
[0025]
Ion species is As⁺In this case, the injection amount is preferably 10¹⁴-10¹⁷(1 / cm²), More preferably 10¹⁵-10¹⁶(1 / cm²), More preferably 1 × 10¹⁵~ 8x10¹⁵(1 / cm²). The implantation energy is not particularly limited, but is preferably 30 to 70 keV, more preferably 40 to 60 keV, and still more preferably 50 ± 5 keV.
[0026]
Thereafter, an interlayer insulating film 311 was deposited, heat treatment for impurity activation was performed, connection holes were opened, and metal wiring 312 was formed to complete the semiconductor device (FIG. 4b).
[0027]
In this embodiment, the semiconductor layer 301 is made of single crystal silicon. However, for example, when a polycrystalline silicon thin film transistor is manufactured, the semiconductor layer 301 is polycrystalline silicon formed on a glass or quartz glass substrate. Alternatively, amorphous silicon thin film transistors may be manufactured, and the semiconductor layer 301 may be amorphous silicon formed on a glass or quartz glass substrate.
[0028]
Furthermore, even if the single crystal silicon of the semiconductor layer 301 is a single crystal silicon substrate or a single crystal silicon grown on an SOI (Silicon on Insulator) or SOS (Silicon on Saphire), it is manufactured by the method of the present invention. There is no change in the effect obtained by doing.
[0029]
However, when a semiconductor device is actually manufactured by the method of the present invention using a single crystal silicon substrate, an element isolation method or the like must be considered. This is because the first conductive layer on the element isolation insulating film has a step in the element isolation region other than the part included in the drawing shown in this embodiment, particularly when chemical mechanical polishing (CMP) is used. This is because the region 304 becomes thin and cannot be used for wiring in the element isolation region. A case where element isolation is performed by LOCOS (Local Oxidation of Silicon) using a single crystal silicon substrate will be described later as another example.
[0030]
In this embodiment, chemical mechanical polishing (CMP) is used to remove the second insulating film 307. However, the second insulating film 305 exposes the top of the second conductive film region 305 and becomes the spacer 308. Other techniques may be used as long as the film 307 can be left with a film thickness that can serve as an ion implantation blocking mask. For example, in the state where the second insulating film 307 is deposited as shown in FIG. 3c, the entire surface is coated under the condition that the etching rate of the photoresist and the second insulating film 307 is almost the same after the photoresist is applied thereon. The so-called resist etch back method in which etching is performed also serves the purpose of the present invention.
[0031]
More specifically, in this embodiment, polycrystalline silicon is used for the first conductive layer 303, but this is made of silicide of a refractory metal such as molybdenum (Mo), tungsten (W), titanium (Ti) or the like. Alternatively, a laminated structure of these and polycrystalline silicon may be used.
[0032]
In the manufacturing method of the semiconductor device of this embodiment, the positional relationship between the gate electrode, the source, and the drain, that is, the offset length of the source and drain in the MOS transistor is processed and shaped to form the first conductive film 303. It is determined by one-time photolithography for forming the film region 304 and the second conductive film region 305. Therefore, the distance between the gate electrode, source and drain (offset length) can always be kept constant regardless of the alignment accuracy of the exposure apparatus as in the conventional mask offset method, and therefore the semiconductor has uniform electrical characteristics. The device could be manufactured. Moreover, unlike the conventional sidewall method, the magnitude of the offset can be arbitrarily determined, and the source-drain breakdown voltage can be easily obtained as required.
[0033]
The second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below in the order of manufacturing steps with reference to FIG. In the second embodiment, a silicon oxide film for element isolation is formed on a single crystal silicon substrate by a LOCOS method, and then the manufacturing method of the present invention is applied. When the method of the first embodiment described above is applied to the manufacture of a semiconductor device using a single crystal silicon substrate in which a silicon oxide film for element isolation must be formed so as to rise from the substrate, Since the wiring portion extending from the gate electrode in the same layer as the electrode is on the silicon oxide film for element isolation (not shown in FIGS. 3 and 4 in which the first embodiment is described), a planarization technique is used. Since this wiring part may become thin or disappear when used, this is an example of a manufacturing method that solves this problem.
[0034]
After forming a thin silicon oxide film on the single crystal silicon substrate 501, the exposed silicon portion is thermally oxidized using the silicon nitride film as a mask, and then an element isolation insulating film 502 is formed by a so-called LOCOS method of removing the silicon nitride film. A gate insulating film 503 is formed in a portion other than the element isolation insulating film 502, and a first conductive film 504 made of polycrystalline silicon is further deposited (FIG. 5a).
[0035]
The first conductive film 504 was processed using one photolithography, and the first conductive film region 505 and the second conductive film region 506 were formed at the same time. The first conductive film region 505 is a gate electrode of the MOS transistor, and the second conductive film region 506 covers a portion where a high-concentration impurity diffusion layer (source and drain of the MOS transistor) will be formed later. . Further, ion implantation is performed from above the first conductive film region 505 and the second conductive film region 506, a low-concentration impurity diffusion layer 507 is formed in the single crystal silicon substrate 501, and the second insulating film 508 is formed. Deposited (Figure 5b).
[0036]
Next, using a chemical mechanical polishing (CMP) technique, 508 was removed until the tops of the first conductive film region 505 and the second conductive film region 506 were exposed (FIG. 5c).
[0037]
Next, a first wiring 509 is formed so as to cover the first conductive film region 505 and expose the second conductive film region 506, and the second conductive film region 506 is formed using the first wiring 509 as a mask. Removed. Subsequently, a high-concentration impurity diffusion layer 510 was formed by ion implantation in the portion of the single crystal silicon 501 that was under the second conductive film region 506 (FIG. 5d). The ion implantation conditions for forming the low-concentration and high-concentration impurity diffusion layers are the same as in Example 1.
[0038]
Thereafter, an interlayer insulating film 511, connection holes 512, and metal wirings 513 were formed to complete the semiconductor device (FIG. 5e).
[0039]
The materials and techniques used for each part in the second example are basically the same as the corresponding parts in the first example except for the single crystal silicon substrate 501, and changes in materials and techniques are also the first example. According to The first wiring 509 necessary only for the second embodiment is polycrystalline silicon. Since the first wiring 509 is made of polycrystalline silicon and the first conductive film 504 is also polycrystalline silicon, in this embodiment, etching up to the second conductive film region 506 is performed for the processing of the first wiring 509. It was possible to remove. However, another material may be used for the first wiring 509 as long as it is a material that can be electrically connected to the first conductive film region 505.
[0040]
In the semiconductor device manufactured by the method of the second embodiment, the electrical characteristics are uniform for the same reason as in the first embodiment, and the required withstand voltage according to the distance between the gate electrode, the source and the drain. Could get.
[0041]
In the second embodiment, a single crystal silicon substrate is used. For example, in the case of manufacturing a polycrystalline silicon thin film transistor, the semiconductor layer may be polycrystalline silicon formed on a glass or quartz glass substrate. In the case of producing a crystalline silicon thin film transistor, the semiconductor layer may be amorphous silicon formed on a glass or quartz glass substrate.
[0042]
Furthermore, even if the single crystal silicon of the semiconductor layer is single crystal silicon grown on SOI (Silicon on Insulator) or SOS (Silicon on Saphire), it can be obtained by manufacturing by the method of this embodiment. There is no change in the effect that a semiconductor device with high uniformity and high breakdown voltage can be obtained.
[0043]
Moreover, in the second embodiment, unlike the first embodiment, when a semiconductor device is manufactured by the method of the present invention using a single crystal silicon substrate, an element isolation insulating film is formed by LOCOS method for element isolation. Even when a step is formed in the element isolation region, since the first wiring 509 is formed, the wiring of the element isolation region can be secured.
[0044]
In the two embodiments described above, the right and left objects are drawn with the center of the gate electrode as a boundary. It is easy to change the length and use the source side and drain side properly.
[0045]
In the following, still another embodiment of the semiconductor device manufacturing method of the present invention will be described as a third embodiment with reference to FIG. In the third embodiment, a silicon oxide film for element isolation is formed on a single crystal silicon substrate by a LOCOS method, and then the manufacturing method of the present invention is applied. When the method of the first embodiment described above is applied to the manufacture of a semiconductor device using a single crystal silicon substrate in which a silicon oxide film for element isolation must be formed so as to rise from the substrate, Since the wiring part extending from the gate electrode in the same layer as the gate electrode is on the step of the silicon oxide film for element isolation, the wiring part may be thinned or lost when using the planarization technique. Therefore, this is an example different from the second embodiment of the manufacturing method that solves this problem.
[0046]
After forming a thin silicon oxide film on the single crystal silicon substrate 601, an element isolation insulating film 602 is formed by a so-called LOCOS method in which the exposed silicon portion is thermally oxidized using the silicon nitride film as a mask and then the silicon nitride film is removed. A gate insulating film 603 is formed in a portion other than the element isolation insulating film 602, and a first conductive film 604 made of polycrystalline silicon is further deposited (FIG. 6a).
[0047]
The first conductive film 604 was processed using one photolithography, and the first conductive film region 605 and the second conductive film region 606 were formed at the same time.
[0048]
Here, in the case where the wiring portion is provided over the silicon oxide film for element isolation, the first conductive film 604 is processed and formed using photolithography, and the above-described first conductive film region 605 and In addition to the second conductive film region 606, a conductive film region may be formed over the element isolation insulating film 602. The first conductive film region 605 is a gate electrode of a MOS transistor, and the second conductive film region 606 covers a portion where a high-concentration impurity diffusion layer (source and drain of a MOS transistor) will be formed later. . Further, ion implantation is performed from above the first conductive film region 605 and the second conductive film region 606, a low-concentration impurity diffusion layer 607 is formed in the single crystal silicon substrate 601, and the second insulating film 608 is formed. Deposited (FIG. 6b).
[0049]
Next, a photoresist 609 is formed by photolithography, and using this as a mask, the second insulating film 608 over the second conductive film region 606 is exposed so that the top of the second conductive film region 606 is exposed. In addition, the second insulating film 608 was partially removed from the upper part so as to remain (FIG. 6c). The lower portion of the remaining second insulating film 608 needs to have a thickness that prevents ions implanted by subsequent ion implantation for forming a high concentration impurity from reaching the lower single crystal silicon substrate 601.
[0050]
Further, the second conductive film region 606 was removed, and a high-concentration impurity diffusion layer 610 was formed by ion implantation in the portion of the single crystal silicon substrate 601 under the created gap (FIG. 6d). The ion implantation conditions for forming the low-concentration and high-concentration impurity diffusion layers are the same as in Example 1.
[0051]
Thereafter, the interlayer insulating film 611, the connection hole 612, and the metal wiring 613 were formed to complete the semiconductor device (FIG. 6e).
[0052]
The materials and techniques used for each part in the third example are basically the same as the corresponding parts in the first example except for the single crystal silicon substrate 601, and changes in materials and techniques are also the first example. According to
[0053]
Even in the semiconductor device manufactured by the method of the third embodiment, the uniformity of the electrical characteristics is good for the same reason as in the first and second embodiments, and the distance between the gate electrode and the source and drain is good. The required breakdown voltage could be obtained according to the conditions.
[0054]
The manufacturing method of the third embodiment has an advantage that the first conductive film region 605 can be used as a wiring as it is, without the need to form a new wiring (first wiring 509), as compared with the second embodiment. is there.
[0055]
Also, in the third embodiment, the left and right objects are drawn with the center of the gate electrode as the boundary. However, as in the other embodiments, the left and right objects are excluded as necessary. By changing the length of the offset, it is easy to use the source side and the drain side separately.
[0056]
The MOS transistor manufactured by the semiconductor device manufacturing method of the present invention as described above has good uniformity in electrical characteristics because the offset length is not affected by misalignment of the exposure apparatus unlike the mask offset method. In addition, an offset having a size larger than that of the side wall method can be provided. Apart from such effects, in a MOS transistor manufactured using the semiconductor manufacturing method of the present invention, it is possible to reduce non-uniform electrical characteristics due to non-uniform gate length.
[0057]
Another factor causing the non-uniformity of the MOS transistor electrical characteristics is the non-uniformity of the gate length. The non-uniformity of the gate length is mainly caused by non-uniformity of photolithography for forming the gate electrode, and partly due to non-uniformity of the subsequent etching process. The gate length is a large factor that determines the electrical characteristics of the MOS transistor, and a slight change in the gate length appears as a change in electrical characteristics. However, it is a MOS transistor manufactured by the method of manufacturing a semiconductor device of the present invention, and as described below as a fourth embodiment, a portion between the impurity diffusion layers of the source and drain and the channel (low concentration impurity) The electrical resistance per unit length in the channel length direction (referred to as a diffusion layer or offset) is the electrical resistance per unit length of the channel when a specified voltage, such as the rated voltage, is applied to the gate and drain. In the MOS transistor which is approximately one-half of the above, it is possible to reduce non-uniformity in electrical characteristics due to non-uniform gate length.
[0058]
A fourth embodiment will be described below with reference to FIG.
[0059]
FIG. 7 is a cross-sectional view when the MOS type transistor of the second invention is manufactured by the manufacturing method of the second embodiment. The horizontal direction in the figure is the channel length direction of the MOS transistor, that is, the gate length direction.
[0060]
Let Ro be the resistance per unit length in the channel length direction of the low-concentration impurity diffusion layer 701 (offset). Further, when the source terminal 702 is set to 0 V and a specified voltage is applied to the gate terminal 703 and the drain terminal 704, an average resistance value from end to end of the channel 705 in a conductive state (hereinafter referred to as an on state) is expressed as a gate length. The divided resistance per unit length is Rc. In the MOS transistor of this embodiment, Ro is approximately one half of Rc. Ro obtained a desired value by adjusting the amount of ions implanted during the formation of the low-concentration impurity diffusion layer.
[0061]
Here, a case where the dimension of the gate electrode 706 is changed is considered. When the lateral width of the gate electrode 706 in FIG. 7, that is, the gate length varies by dL, the channel length also varies by dL. The fluctuation of the offset length at this time is -2 dL for both the source side and the drain side. This is because the MOS type transistor of FIG. 7 is manufactured by the method described in the second embodiment, so that the dimensions of the first conductive film region 505 to be the gate electrode of the MOS type transistor as shown in FIG. When the dimensions of the conductive film region 506 are the same and the dimension of the first conductive film region 505 varies by dL, the dimension of the second conductive film region 506 formed at the same time also varies by dL. This is because the distance between the region 505 and the second conductive film region 506 varies by −dL in one offset side. Thus, when the channel length fluctuates by dL, if dL is sufficiently smaller than the gate length, for example, if dL is less than 10% of the gate length, the fluctuation of the total resistance of the channel in the on state multiplies Rc by dL. It is almost equal to the size. On the other hand, since the variation in the offset dimension is -2 dL for both the source side and the drain side, the variation in the offset resistance is the magnitude obtained by multiplying -2 dL by Ro. In the MOS transistor of this embodiment, Ro is approximately one half of Rc, so that the variation in the channel resistance in the on state is almost offset by the variation in the offset resistance. That is, in the MOS transistor of the fourth embodiment, the change in electrical characteristics due to the variation in gate length can be reduced.
[0062]
Although the MOS transistor of the fourth embodiment is manufactured by the manufacturing method of the second embodiment, the same effect can be obtained even when manufactured by the manufacturing method of another embodiment of the present invention. .
[0063]
In the MOS transistor of the fourth embodiment, the offset (low-concentration impurity diffusion layer 701) does not necessarily have the first purpose of improving the breakdown voltage by relaxing the electric field at the drain end. This is because when the impurity concentration of the offset must be determined in order to make Ro approximately one half of Rc, the offset electric field relaxation effect may not be sufficiently obtained with the determined concentration. However, if the effect of reducing the non-uniformity of the electrical characteristics due to the non-uniformity of the gate length is obtained while adding the electric field relaxation effect to the offset of the MOS transistor after using the manufacturing method of the semiconductor device of the present invention, It should be noted that this is one end of the effect of the present invention.
[0064]
【The invention's effect】
As described above, in the method of manufacturing a semiconductor device according to the present invention, the magnitude of the offset of the MOS transistor can be made uniform and arbitrary. Therefore, when a semiconductor device having an offset is manufactured by the method for manufacturing a semiconductor device of the present invention, it is possible to obtain a semiconductor device having uniform electrical characteristics and a high degree of freedom in setting a breakdown voltage between the source and drain. There is. This is an effect obtained in any of the embodiments of the semiconductor device manufacturing method of the present invention.
[0065]
Further, the electrical resistance per unit length in the channel length direction of the so-called offset portion between the high concentration impurity diffusion layers of the source and drain and the channel manufactured by the method of manufacturing a semiconductor device of the present invention is the gate electrode and drain. In the MOS transistor of the present invention, which is approximately one half of the electrical resistance per unit length of the channel when a prescribed voltage is applied to the electrical characteristics, the electrical characteristics caused by the variation in the gate length due to non-uniform photolithography Can be reduced.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view showing a process of a so-called sidewall method in a conventional method of manufacturing a semiconductor device having an offset.
FIG. 2 is a process cross-sectional view showing a process of a so-called mask offset method in a conventional method of manufacturing a semiconductor device having an offset.
FIG. 3 is a process cross-sectional view illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention. The steps from the beginning to the middle are shown, and the subsequent steps are shown in FIG.
FIG. 4 is a process cross-sectional view illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 4 shows a continuation process from FIG. 3. FIG.
FIG. 5 is a process cross-sectional view illustrating a second embodiment of the method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a process cross-sectional view illustrating a third embodiment of a method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view illustrating a MOS transistor according to the fourth embodiment of the present invention.
[Explanation of symbols]
101, 201 ... Semiconductor substrate
102, 202, 503, 603... Gate insulating film
103, 203, 706... Gate electrode
104, 108, 206 ... ion implantation
105, 204, 306, 507, 607, 701... Low-concentration impurity diffusion layer
106 ... Insulating film
107 ... side wall spacer
109, 207, 310, 510, 610... High concentration impurity diffusion layer
205, 309, 609 ... Photoresist
301 ... Semiconductor layer
302... First insulating film
303, 504, 604 ... first conductive film
304, 505, 605 ... first conductive film region
305, 506, 606... Second conductive film region
307, 508, 608 ... second insulating film
308 ... Spacer
311, 511, 611... Interlayer insulating film
312, 513, 613 ... Metal wiring
501 601 ... single crystal silicon substrate
502, 602 ... Element isolation insulating film
509: First wiring
512, 612 ... connection hole
702 ... Source terminal
703: Gate terminal
704 ... Drain terminal
705 ... Channel

Claims (1)

Forming a gate insulating film on the semiconductor layer;
Forming a cover layer and a gate electrode on the gate insulating film by the same process and the same photolithography; and
Forming a diffusion layer having a low impurity concentration using the cover layer and the gate electrode as a mask;
Forming a spacer between the cover layer and the gate electrode;
Removing the cover layer;
And a step of implanting impurity ions into the semiconductor layer under the removed cover layer to form a high impurity concentration diffusion layer to be an impurity diffusion layer of a source and a drain. In the semiconductor device
The electrical resistance per unit length in the channel length direction of the low impurity concentration diffusion layer existing between the impurity diffusion layer and the channel of the source and drain is set to a predetermined voltage on the gate electrode and the drain. In addition, the semiconductor device is characterized in that the electric resistance per unit length of the channel in the channel length direction when the channel is turned on is ½.

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