JP3859439B2 - Method for manufacturing MOSFET structure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of integrated circuits, and more particularly to the manufacture of MOSFET devices formed using replacement gates.
[0002]
[Prior art]
The manufacture of MOSFET semiconductors is well known in the art. Such a structure is shown in US Pat. No. 4,702,792 by Chow et al., Which discloses a technique for fabricating a small conductive channel.
[0003]
This replacement, or “cast” process, is a promising method for fabricating transistors with a wide selection of gate materials. However, this process is not widely used due to process control problems in current technology. The main obstacle to using the replacement gate process is controlling the exact dimensions of the gate during the gate replacement process.
[0004]
Chatterjee et al., IDEM Tech., For the replacement gate process, specifically the use of polysilicon as the replacement gate material. Digest, 777, 1998. A disadvantage of using polysilicon as a replacement gate material is the difficulty in using a wet etch process to remove polysilicon that selectively covers silicon dioxide.
[0005]
Yagishita et al. Also described IEDM Tech. Digest, p. 785, 1998. Yagishita also discloses the use of polysilicon as a replacement gate material.
[0006]
Evans et al., In patent application 09 / 028,157, which is a continuation-in-part of this application, filed February 23, 1998, discloses the use of silicon nitride as a replacement gate material. Although using silicon nitride as the replacement gate material is effective, it can be difficult to pattern the silicon nitride replacement gate using a dry etch process. To optimize dry silicon nitride etching, it is necessary to have etch selectivity for both silicon and silicon dioxide.
[0007]
To date, during the manufacture of MOSFET devices, silicon germanium and other group IV-B elemental alloys have not been used as dummy gates or replacement gates.
[0008]
It would be advantageous to have a replacement gate MOSFET fabrication process with high etch selectivity between the replacement gate material and the adjacent materials used in spacers and other structures. Although the above references discuss the manufacture of MOSFET devices, they do not provide the advantages of the present invention.
[0009]
[Problems to be solved by the invention]
It is an object of the present invention to provide a method for manufacturing a MOSFET device, characterized in that a source region and a drain region are formed before forming a gate.
[0010]
Another object of the present invention is to provide a MOSFET device in which the MOSFET device can be built on both normal silicon and silicon on insulator (SOI) substrates.
[0011]
It is a further object of the present invention to provide the manufacture of a MOSFET device that allows the use of any type of gate dielectric material.
[0012]
Yet another object of the present invention is to provide the manufacture of a MOSFET device having a highly conductive material such as a refractory metal or copper as the gate electrode.
[0013]
It is a further object of the present invention to provide a fabrication of a MOSFET device that allows the application of a fabrication process that allows high etch controllability and achieves the desired exact gate dimensions.
[0014]
[Means for Solving the Problems]
A method of manufacturing a MOSFET structure on a substrate according to the present invention comprises forming an island on a gate region in the substrate, wherein the island is formed from an alloy of a group IV-B element, and surrounding the island Forming sidewalls; forming source and drain regions in the substrate; selectively removing the islands without removing the sidewalls, thereby leaving voids on the gate regions; Filling the void with a gate structure, thereby achieving the object.
[0015]
The alloy of the IV-B group element is Si _1-X Ge _X And x may range from about 0.05 to about 1.0.
[0016]
Depositing an oxide layer having a thickness between 5 and 30 nm on the substrate prior to forming the islands, the step of forming the islands forming an island on the oxide layer; A forming step may be included.
[0017]
The step of forming the islands may include depositing a layer of material formed from an alloy of Group IV-B elements having a thickness of about 150 to about 500 nm on the oxide layer.
[0018]
Forming the island comprises depositing a layer of material formed from an alloy of group IV-B elements on the oxide layer; masking the deposited layer in the region of the island; and The method may further include etching the deposited layer to remove the layer except for the region on the gate region.
[0019]
Removing the island of the IV-B group element alloy comprises depositing a non-island material layer over the island, the sidewalls around it, and the source and drain regions; Chemical mechanical polishing of the structure, and dissolving the islands with a solvent, thereby leaving the voids.
[0020]
The non-island-like material layer is polysilicon, the non-island material layer is a first polysilicon layer, and the step of filling the void includes a gate material on the remaining first polysilicon layer and the void. Depositing a layer and chemically and mechanically polishing the structure to remove material to a level above the first polysilicon layer.
[0021]
The gate material is titanium nitride (TiN), tantalum nitride (TaN), or polysilicon used in combination with a barrier metal such as tungsten nitride (WN) and polysilicon germanium, tungsten (W), tantalum (Ta), You may select from the group which consists of platinum (Pt), molybdenum (Mo), and copper (Cu).
[0022]
The non-island material layer may be a first dielectric material layer.
[0023]
The first dielectric material layer may be selected from the group consisting of silicon nitride and oxide.
[0024]
Following the step of filling the void with a gate structure, a step of planarizing the top surface of the structure by chemical mechanical polishing may be included.
[0025]
Following the step of planarizing the structure, depositing a second dielectric material layer on the planarized structure; forming an opening through the second dielectric material layer to the gate structure; Forming an opening through the second dielectric material layer and the first dielectric material layer to the source and drain regions; depositing a metal layer on the structure and in the opening; and Forming an electrode so as to be in electrical contact with the gate region and the drain region.
[0026]
Generating the sidewalls around the island may include forming the sidewalls of a material selected from the group consisting of silicon nitride and oxide.
[0027]
The void may have a length that extends from the source region to the drain region between 0.10 and 0.2 microns.
[0028]
Filling the void with a gate structure comprises depositing the source region, the drain region, and a gate dielectric layer over the void, whereby a layer of gate dielectric is deposited within the void; and And then depositing a layer of gate electrode material over the layer of gate dielectric.
[0029]
The step of forming the gate dielectric may include the step of depositing a material having a high dielectric constant and a high pressure strength.
[0030]
The deposited gate dielectric is Ta ₂ O _Five TiO ₂ , ZrO ₂ , HfO ₂ The following materials doped with Si, Ta ₂ O _Five TiO ₂ , ZrO ₂ , HfO ₂ And the following materials doped with Al, Ta ₂ O _Five TiO ₂ , ZrO ₂ , HfO ₂ A material selected from the group comprising:
[0031]
The step of depositing the gate dielectric layer is by a process selected from the following physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma chemical vapor deposition (PECVD): May be implemented.
[0032]
Following the step of filling the void with a gate structure, a step of planarizing the upper surface of the structure by chemical mechanical polishing may be included.
[0033]
Following the step of planarizing the top surface of the structure, a metal layer is deposited on the top surface of the structure to metallize the structure so that it is in electrical contact with the source region, the gate region, and the drain region. An electrode may be formed on the substrate.
[0034]
Following the step of depositing a metal layer on the top surface of the structure, the method may include annealing the structure to facilitate the salicide process prior to metallizing the structure.
[0035]
A method of manufacturing a MOSFET according to the present invention comprises the steps of depositing an oxide layer on a silicon substrate, forming a silicon tin alloy island on a gate region in the substrate, and surrounding the silicon tin alloy island. Forming sidewalls in the substrate; forming source and drain regions in the substrate; removing the silicon tin alloy islands, thereby leaving voids on the gate region; and Filling the region on the source region and the drain region and planarizing the top surface of the structure by chemical mechanical polishing, thereby achieving the object.
[0036]
The silicon tin alloy is Si _1-X Sn _X Where x may be in the range of about 0.05 to about 1.0.
[0037]
Forming the sidewall around the silicon tin alloy island may include forming the sidewall from a sidewall material selected from the group consisting of silicon nitride and oxide.
[0038]
A process for manufacturing a MOSFET according to the present invention includes depositing an oxide layer on a silicon substrate, forming a silicon germanium alloy island on a gate region in the substrate, and surrounding the silicon germanium alloy island. Forming sidewalls on the substrate, forming source and drain regions in the substrate,
Removing the silicon germanium alloy islands, thereby leaving voids on the gate region; filling the voids and regions on the source and drain regions; and top surface of the structure by chemical mechanical polishing. Flattening, thereby achieving the above object.
[0039]
The silicon germanium alloy is Si _1-X Ge _X Where x may range from about 0.05 to about 1.0.
[0040]
Forming the sidewalls around the silicon germanium alloy island may include forming the sidewalls from a sidewall material selected from the group consisting of silicon nitride and oxide.
[0041]
Accordingly, the method of the present invention forms a silicon germanium or similar alloy island on the gate region in the substrate, the alloy material preferably being selected from elements of groups IV-B of the Periodic Table of Elements. Forming oxide or nitride sidewalls around the silicon germanium islands (silicon germanium is used herein as a representative example of a group IV-B element suitable alloy to be used. A process of forming source and drain regions in the substrate, and removing the silicon germanium island without removing the sidewalls around the island, thereby leaving a void on the gate region, and preferably Includes forming a gate dielectric over the gate region in the void and filling the remainder of the void with a gate electrode material.
[0042]
The step of removing silicon germanium (or other group IV-B alloy) islands preferably includes depositing a non-island material layer on the islands and in regions on the source and drain regions. The layer allows the island alloy to be selectively dissolved or otherwise removed without simultaneously removing the deposited non-island material layer. The non-island material layer may be polysilicon (or known to those skilled in the art, such as polycrystalline silicon) if a stacked source / drain region is provided, or if a normal source / drain region is provided It can be any suitable dielectric such as silicon nitride or oxide. After filling the void with the gate structure, the method preferably includes planarizing the top surface of the structure by chemical mechanical polishing. In an embodiment of the invention characterized in that stacked source / drain regions are formed, the method preferably comprises the steps of depositing a metal layer on the top surface of the structure, and the source region, gate region and drain region. The method further includes metallizing the structure to form an electrically contacting electrode.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
This application was invented by David Russel Evans and Sheng TengHsu, “Fabrication of a PlanarMOSFET with Raised Source / Drain by Chemical Mechanical Polishing and Nitth on Feb. , 157, claim priority based on a continuation-in-part application.
[0044]
1-12 illustrate successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention having stacked source / drain regions.
[0045]
Turning now to the drawings and initially to FIG. 1, the substrate is in this case a single crystal silicon substrate, generally indicated at 20. As used herein, “substrate” or “silicon substrate” means a silicon-on-insulator (SOI) substrate, including a bulk silicon, single crystal substrate, or oxygen-implanted silicon (SIMOX) substrate. The substrate 20 has been specially processed to form electrically active and / or isolated regions suitable for subsequent device fabrication described herein. Pre-processing is infinite and includes normal n-well and / or p-well definition and isolation, trench isolation with polysilicon or oxide refill, normal local oxidation (LOCOS) or full recess local oxidation (LOCOS) ) And / or SOI mesa structures produced by either LOCOS or etching. Such steps may be combined or used individually. Silicon-on-insulator (SOI) substrates are SIMOX, bonded silicon wafers and etchback, heteroepitaxy, etc., manufactured by high dose oxygen implantation into single crystal silicon with subsequent annealing. An example of SIMOX is 1 × 10 ¹⁸ ~ 2x10 ¹⁸ cm ^-2 Oxygen implantation at about 200 keV. The wafer is then annealed at 1300 ° C.-1350 ° C. for 4-10 hours. The thickness of the buried oxide is about 300 nm. When the pretreatment is complete, the substrate can be planarized by planarization, ie, chemical mechanical polishing (CMP).
[0046]
An oxide layer 22 is formed on the substrate 20 to a thickness of about 5 to about 30 nm (note that the drawing is not a constant magnification ratio). The oxide layer 22 is referred to herein as the pad oxide layer 22. A layer of material that is an alloy of group IV-B elements of the periodic table is then deposited on the oxide layer 22. In the example first described herein, the IV-B element alloy is preferably polysilicon germanium deposited to a thickness of about 150 nm to about 500 nm by chemical vapor deposition (CVD). It is. Silicon germanium is used herein as a representative example of a suitable alloy of group IV-B elements, thereby functioning as an “island” material as described below.
[0047]
The silicon germanium layer is preferably Si _1-X Ge _X It is expressed. Here, x is typically in the range of 0.1 to 0.5, but may be anywhere within the range of about 0.05 to about 1.0. A silicon germanium alloy layer is formed on the silicon germanium island 24 of FIG. 1 by photolithography and plasma anisotropic etching processes of the deposited silicon germanium layer. The silicon germanium region removed by etching is shown by a dotted line in FIG. Etching of the region 23 other than the island region 24 is stopped at the pad oxide layer 22. That is, the silicon germanium layer 23 is masked in the gate region, and then the remaining portion of the silicon germanium is etched to form islands 24. The pad oxide layer 22 outside the masked “island” region 24 can be partially etched or completely removed during this etching process, although the pad oxide layer 22 can also be removed in a later step. It may remain to function as an etch stop. In the illustrated embodiment herein, the pad oxide layer 22 has not been removed.
[0048]
The silicon germanium island 24 forms a replacement “cast” for the gate electrode. That is, the silicon germanium island 24 forms a dielectric image of what will become the gate electrode. This image can preferably be used as a metal gate electrode, or a pattern or form for forming a gate electrode made of another material, without additional photolithography steps as described later herein. . For example, an image of island 24 is transferred to a gate electrode of high impurity polysilicon or polysilicon germanium alloy material.
[0049]
The drawings herein show the formation of MOSFET transistors that can be either n-channel or p-channel. If both molds are formed simultaneously during manufacturing, p ^- Photoresist is used to mask the n-channel transistor during low dose (or low impurity) drain (LDD) ion implantation. P shown in FIG. ^- The LDD regions 26 and 28 are BF ₂ It is formed by ion implantation or plasma doping. The preferred ion dose is 5 × 10 ¹³ ~ 50x10 ¹³ cm ^-2 And BF ₂ The ion energy is 10 keV to 80 keV. The ion energy is sufficiently small that no ions are implanted through the silicon germanium layer. Then remove the photoresist and n ^- Mask the p-channel transistor with a new photoresist for LDD ion implantation. n ^- The LDD region is formed by arsenic or phosphorus ion implantation. At this time, the ion dose is 5 × 10. ¹³ ~ 50x10 ¹³ cm ^-2 In the case of arsenic, the ion energy is 40 to 100 keV, or in the case of phosphorus, the ion energy is 10 to 60 keV. The exemplary transistors shown in the drawings represent either n-channel or p-channel transistors.
[0050]
An oxidation step may also be performed for the purpose of thickening the pad oxide 22. The result is a “bird's beak” at the edge of the island, as shown at 30 and 32 in FIG. Bird's beak improves the breakdown voltage of the gate oxide at the edge of the gate electrode. The oxidation step is performed by heating the structure of FIG. 1 in oxygen to thicken the pad oxide region 22 that is not covered by the “islands” 24 as is well known. During this oxidation step, ions in the LDD region are diffused and spread beyond the length of the bird's beak as shown in FIG. Silicon nitride layer 34 is deposited over the structure by any state of the art process such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) and is illustrated in FIG. It becomes composition. In another embodiment, oxide may be used as the material for layer 34.
[0051]
Assuming that silicon nitride is used in layer 34 (FIG. 2), the wafer then undergoes an anisotropic nitride etch and a thin layer of nitride 36 around the sidewall of the silicon germanium layer as shown in FIG. And leave 38.
[0052]
Referring now to FIG. 4, a layer of material different from the IV-B group element alloy used on island 24 is deposited on the structure of FIG. Layer 40 (FIG. 4) refers to a layer formed from a non-island material. This is because the material of the island 24 needs to be different to allow convenient removal of the island without simultaneously removing the material used in the layer 40. In the first embodiment of the invention, layer 40 is preferably deposited with polysilicon. Polysilicon layer 40 is deposited on the alloy islands, island sidewalls and source and drain regions on the wafer. Layer 40 is thicker than silicon germanium layer 24 by an amount “T”. Layer 40 is referred to herein as first polysilicon layer 40 instead. As shown in FIG. 5, the structure is then processed by CMP to expose the silicon germanium islands 24.
[0053]
A photoresist mask 33 is then applied to cover the active area of the device. The polysilicon layer 40 in the field region 35 (indicated by the parallel line pattern in FIG. 6) is not covered with resist. The polysilicon layer 40 and any suitable portion of the substrate 20 are etched to remove the field region 35. Next, the resist layer 33 is peeled off. At this point, p ^- Channel and n ^- Only the source region 26 and the drain region 28 of both channel transistors are covered with the polysilicon layer 40. The wafer is then coated with an oxide layer (indicated by dotted line 37 in FIG. 6). The oxide layer has a thickness equal to or greater than the depth of the oxide deposited in the field region 35. The oxide is CMP planarized and stops on top of the polysilicon and silicon germanium layers. A highly selective slurry that removes oxide faster than polysilicon is desirable for this process. As a result, devices on the substrate are isolated from each other by oxide regions 41 surrounding the polysilicon layer 40 as shown in FIGS. The region 41 is shown only in FIG. 7 and FIG. 8, but this region also exists in the configurations of other drawings showing the state after the steps described using FIG. 5 and FIG. 6.
[0054]
The next step is source / drain ion implantation into the remaining polysilicon region 40 in FIGS. Assuming that both p and n channel devices are processed and implantation is first performed on the p channel device, a photoresist is formed to mask the n channel transistors. In FIG. 5, the p-channel source / drain region including the polysilicon region 40 is BF. ₂ Ions are implanted. The preferred ion dose is 1.0 × 10 ¹⁵ ~ 5.0 × 10 ¹⁵ cm ^-2 And BF ₂ The ion energy is 10 keV to 80 keV. Again, since the ion energy is sufficiently small, no ions are implanted through the gate dielectric layer to the channel region. This ion implantation results in a stacked p-channel transistor for p-channel transistors. ⁺ Source region and p ⁺ A drain region is formed. The photoresist is stripped and a new photoresist is used to mask the p-channel transistor for n-channel source / drain ion implantation.
[0055]
The n-channel source / drain region is 1.0 × 10 ¹⁵ ~ 5.0 × 10 ¹⁵ Of ion energy of 40 keV to 100 keV, or phosphorus ion implantation of ion energy of 10 keV to 60 keV. The masking resist was peeled off, and the wafer was annealed in an inert gas atmosphere at a temperature ranging from about 800 ° C. to about 1100 ° C. for 15 seconds to 60 minutes. The source and drain of the p-channel transistor is p ⁺ While the corresponding region of the n-channel transistor is n ⁺ To be doped.
[0056]
Referring to FIG. 9, the silicon germanium island 24 is removed by any one of several methods (eg, highly selective wet etching). There are several wet etching processes that selectively remove silicon germanium on silicon. For example, in a wet etching process with a mixture of acetic acid, nitric acid and HF, silicon germanium to silicon is 100 to 1, silicon germanium to silicon dioxide is Etch selectivity better than 1000 to 1. NH _Four OH, H ₂ O ₂ And a mixture of water can selectively etch silicon germanium at least five times faster than silicon. H ₂ O ₂ A mixture of HF and water can selectively etch silicon germanium on silicon. Any wet etching process may have the configuration shown in FIG. The exact dimensions, i.e. the gate length, can be controlled by the high selectivity and pattern control available during the etching of the silicon germanium island 24. That is, because the inner sidewalls of spacers 36 and 38 are substantially perpendicular to the surface of the gate region during the process disclosed herein, the exact dimensions of the gate do not change during the manufacturing steps. In the illustrated embodiment, the gate has a critical dimension between 0.10 and 0.2 microns, preferably about 0.13 microns, spanning the width of the gate region from region 26 to region 28. spread. A region from which the island 24 is removed (a region extending to a channel region 42 of a finally completed transistor) is referred to as a void 45 in this specification. Void 45 is instead referred to as a void on the gate region.
[0057]
Removal of the silicon germanium exposes the remaining portion of the initial pad oxide 22 and is shown only by line 22 in FIG. Although this oxide layer can function as a gate dielectric, after removal of the silicon germanium island, the remaining pad oxide is not considered to be contaminated or undamaged. The pad oxide 22 functions as a shielding oxide for unmasked threshold adjustment implants. Of course, threshold adjustment implants that are not masked will necessarily contaminate the oxide pad 22. Thus, the oxide pad 22 is not desirable as a gate dielectric, and after removing the oxide pad 22, the channel region 42 is exposed and requires the formation of some gate dielectric thereon.
[0058]
The simplest approach to forming the gate dielectric is to regrow the dielectric on the exposed silicon in the channel region 42, but such regrowth can make the edges thinner and ultimately gained. The resulting device will have an undesirable low gate breakdown voltage. This effect can be reduced by appropriate design of the above-described oxidation step described with reference to FIG. During the oxidation step, bird's beaks 30 and 32 are formed around the silicon germanium island and thicken the pad oxide at the edge of the gate. If the remaining pad oxide is removed with good controllability, a “toe” is formed under the spacers (36 and 38) to prevent edge thinning.
[0059]
Alternatively, the gate dielectric may be formed by some deposition method. For this, materials other than silicon oxide may be used. AlN, Al ₂ O _Three TiO ₂ , ZrO ₂ Or Ta ₂ O _Five Other materials such as are advantageous because they have desirable physical properties such as high dielectric constant and / or high pressure strength. Furthermore, zirconium oxide and hafnium oxide compounds such as aluminum-doped zirconium oxide, silicon-doped zirconium oxide, hafnium oxide, aluminum-doped hafnium oxide, and silicon-doped hafnium oxide may be used. In these examples, bird's beak formation by the oxidation step described above is not required, and that step may be omitted from the process path. This material can be deposited by CVD, PVD, or atomic layer deposition (ALD). Regardless of which method is used, the end result is forming a gate dielectric layer 44 as shown in FIG.
[0060]
After formation of the gate dielectric 44, a gate electrode material 46 is deposited over the entire structure, resulting in the configuration shown in FIG. The deposited layer 46 is polysilicon. However, it may be deposited over the source, gate and drain regions as the void is filled with a material other than polysilicon. Refractory metals such as tungsten (W), tantalum (Ta), platinum (Pt), molybdenum (Mo), or high conductivity metals such as copper (Cu) are titanium nitride (TiN), tantalum nitride (TaN). ), Or in combination with a barrier metal such as tungsten nitride (WN). In another embodiment, polysilicon germanium is also used for gate formation. Whether the structure is covered with any selected metal, the structure is subjected to overall planarization by CMP to remove portions of the polysilicon layer 40 and gate material layer 46, and portions of the sidewall spacers 36 and 38. As a result, the structure shown in FIG. 11 is obtained.
[0061]
An optional salicide (self-aligned silicide) process is performed to minimize the parasitic resistance of the gate, source, and drain electrodes. Referring to FIG. 12, silicide layers 52 and 54 are formed by any state-of-the-art salicide process. A problem in the Salicide prior art is that the unetched metal remaining on the spacers 36 and 38 can cause the gate to short with the source and / or drain. This problem is solved by “touch polish”, a very short CMP step.
[0062]
Here, the device of FIG. 12 is ready for conductor metallization. Conductor metallization is accomplished by any technique known to those skilled in the art to form electrodes for the source, gate, and drain regions. Those electrodes are in electrical contact with the respective regions. This metallization of the conductor is accomplished by conventional patterning and etching metallization, such as using an aluminum alloy. However, since the surface is already entirely planarized, copper embedding and damascene metallization by CMP can be easily performed.
[0063]
Referring now to FIG. 13, a structure applied on a SIMOX substrate having a bulk silicon layer 60 and a buried oxide layer 62 is shown. The remaining structures are indicated using the reference numbers used for the same elements.
[0064]
14 and 15 illustrate another embodiment of the present invention where the barrier layer is deposited in the void 45 of FIG. The barrier layer 70 is preferably a suitable material such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) that has a barrier property to the copper gate electrode 73 subsequently deposited in the void 45. Barrier metal (see FIG. 15). Excess barrier metal on the source and drain regions is removed by CMP, and as a result, the barrier material is naturally formed in a self-aligned manner with respect to the gate electrode 73. FIG. 16 shows the embodiment of FIG. 15 on a SIMOX substrate. The gate dielectric 44 in FIGS. 14-16 is, for example, Ta ₂ O _Five TiO ₂ , ZrO ₂ , HfO ₂ Provided by any suitable means such as deposition of high dielectric constant materials, such as any material doped with either Si and Al, or other suitable dielectric material, and some of them Can optionally be doped with either Si or Al, or other suitable dielectric material. In the embodiment described with reference to FIG. 10, a similar process can be used to provide the gate dielectric 44.
[0065]
Other IV-B group alloys such as SiSn may also be used as dummy gates (ie replacement gates) in the above-described process. Similar processing steps and process modifications can be used in silicon germanium and silicon tin alloy processes based on the similar chemistry of these materials. These new dummy gate materials may also be used for the manufacture of other devices such as ferroelectric memories.
[0066]
Embodiments of the foregoing invention use a stacked source / drain configuration. The embodiment of FIGS. 17-22 has a conventional source / drain structure. 17, 18, 19 and 20 show the steps equivalent to the first embodiment shown in FIGS. 3, 4, 5 and 9, respectively, in which the same reference numerals are used for the same elements. . In FIG. 17, after formation of island 24 and sidewall spacers 36 and 38, an implantation step is performed to implant a suitable p or n-type dopant (depending on the conductivity type of the device being formed) into substrate 20. After a suitable anneal is performed to activate the dopant, the result is a source region 100 and a drain region 102 formed.
[0067]
In this embodiment, the next step (FIG. 18) is to deposit a layer of dielectric 106, such as silicon dioxide, on the alloy islands, island sidewalls, and source and drain regions. Layer 106 is also referred to as a non-island material or “first dielectric material layer” deposited on the structure described above. Similar to layer 40 of FIG. 4, layer 106 is thicker than silicon germanium (“island”) layer 24 by an amount “T” (see FIG. 4). Then, as shown in FIG. 19, the structure is processed by CMP to expose the silicon germanium island 24. In FIG. 19, the source / drain regions 100/102 are covered by silicon dioxide layers 110/112, respectively. The formation of field regions for element isolation is performed as shown and described with reference to FIGS. 6-8 above.
[0068]
Here, the silicon germanium island 24 is removed by any suitable method that selectively removes the material of the island 24 but does not remove the sidewall spacers 36 and 38 or the silicon dioxide regions 110 and 112. There are several wet etching processes well known to those skilled in the art, which selectively remove silicon germanium on silicon dioxide or silicon nitride. As shown in FIG. 20, the removal step results in the creation of voids 45 on the gate region (ie, channel region 42) of the device.
[0069]
The formation of the gate dielectric layer 44 (FIG. 21) and the deposition of the gate electrode material layer 46 in the embodiment of FIGS. 17-22 are the same as described above with reference to FIG. By filling void 45 with a gate structure, the top surface of the structure is planarized to a level approximately indicated by line 118 in FIG. The planarization step is performed by chemical mechanical polishing.
[0070]
Finally, a second dielectric layer 122 is deposited on the planarized structure. Openings 124, 126, 128 are formed through layer 122. Layer 122 includes an opening 126 extending to gate structure 130 and openings 124 and 128 extending through first dielectric layers 110 and 112 to source region 100 and drain region 102, respectively. A suitable metal layer (not shown) is then deposited on the structure and in the openings 124, 126, 128 to form electrodes in electrical contact with the source region 100, gate region 130, and drain region 102. Complete the device.
[0071]
Accordingly, a method of forming a MOSFET using a silicon germanium replacement gate or similar alloy replacement gate has been disclosed. Although preferred methods of forming the structure and their application to SIMOX substrates have been disclosed, further variations and modifications can be made without departing from the scope of the invention as defined in the appended claims. Should be understood.
[0072]
【The invention's effect】
The manufacturing method of the MOSFET includes the following steps. That is, an oxide layer is deposited on a silicon substrate, and a silicon-based alloy island is formed on a gate region in the substrate, whereby the silicon-based alloy is a silicon germanium alloy, a silicon tin alloy, or a group IV-B A step of forming a sidewall around the silicon-based alloy island, forming a source region and a drain region in the substrate, removing the silicon-based alloy island and thereby the gate Leaving a void on the region, filling the region on the void and source and drain regions, and planarizing the top surface of the structure by chemical mechanical polishing. Alternatively, another embodiment is disclosed that provides a conventional stacked source / drain structure.
[0073]
The present invention uses new materials for dummy gates (ie replacement gates) that can be selectively removed with better control of the gate's exact dimensions. In particular, silicon germanium replacement gates can be etched faster and more easily patterned than prior art replacement gates. In addition, prior art polysilicon replacement gates can only be formed with oxide spacers, while using silicon germanium or similar alloys as the replacement gate material allows the use of oxide or nitride spacers. , Thereby forming a replacement gate island.
[Brief description of the drawings]
FIG. 1 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention having stacked source / drain regions.
FIG. 2 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 3 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 4 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 5 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 6 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention having stacked source / drain regions.
FIG. 7 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 8 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 9 shows successive steps in the manufacture of a MOSFET device according to the first embodiment of the invention with stacked source / drain regions.
FIG. 10 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention with stacked source / drain regions.
FIG. 11 shows successive steps in the manufacture of a MOSFET device according to a first embodiment of the invention having stacked source / drain regions.
FIG. 12 shows successive steps in the manufacture of a MOSFET device according to the first embodiment of the invention with stacked source / drain regions.
FIG. 13 shows a device on an SOI substrate.
FIG. 14 shows the structure of the device after barrier layer deposition in another embodiment of the invention.
FIG. 15 shows a complete device structure with a deposited barrier layer.
FIG. 16 shows a complete device structure with a gate barrier layer deposited on a SIMOX substrate.
FIG. 17 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
FIG. 18 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
FIG. 19 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
FIG. 20 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
FIG. 21 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
FIG. 22 shows successive steps in the manufacture of a MOSFET device according to yet another embodiment of the invention.
[Explanation of symbols]
20 substrates
41 Oxide region
42 channel region
45 void
48, 50 Polysilicon layer
60 Bulk silicon layer
62 buried oxide layer
100 source region
102 Drain region
106 Dielectric layer (first dielectric layer)
110, 112 Silicon dioxide layer (first dielectric layer)
122 Second dielectric layer
124, 126, 128 opening
130 Gate area

Claims (15)

A method of manufacturing a MOSFET structure on a silicon substrate, comprising:
Forming a silicon tin alloy island on the gate region in the silicon substrate;
Forming a sidewall around the island;
Forming a source region and a drain region in the silicon substrate;
Depositing polysilicon on the island, the sidewalls around it, and the source and drain regions;
Removing the polysilicon until the islands are exposed by chemical mechanical polishing;
Removing the islands by wet etching so that voids remain on the gate region without removing the sidewalls;
Depositing a gate material layer over the remaining polysilicon layer and the void;
Filling the void with a gate structure by removing the gate material layer by chemical mechanical polishing until the polysilicon layer is exposed ;
A method comprising the steps of: Depositing a silicon oxide layer having a thickness of between 5 and 30 nm on the substrate prior to forming the islands, the step of forming the islands on the silicon oxide layer; The method of claim 1, comprising forming an island. The method of claim 2 , wherein forming the island comprises depositing a layer of silicon tin alloy having a thickness of 150 to 500 nm on the silicon oxide layer. Forming the islands comprises: depositing a layer of silicon tin alloy on the silicon oxide layer; masking the deposited layer in a region of the island; and excluding regions on the gate region. The method of claim 3 , further comprising etching the deposited layer to remove.   The gate material is polysilicon, tungsten (W), used in combination with a barrier metal selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and polysilicon germanium. The method of claim 1, wherein the method is selected from the group consisting of tantalum (Ta), platinum (Pt), molybdenum (Mo), and copper (Cu). The method of claim 1, wherein forming a sidewall around the island includes forming the sidewall with a material selected from the group consisting of silicon nitride and silicon oxide.   The method of claim 1, wherein the void has a length extending from the source region to the drain region between 0.10 and 0.2 microns.   Filling the void with a gate structure comprises depositing a gate dielectric layer on the source region, on the drain region, in the void and on the void, and then on the gate dielectric layer. Depositing the layer. The method of claim 8 , wherein forming the gate dielectric comprises depositing the gate dielectric of a material having a high dielectric constant and high breakdown strength. The deposited gate dielectric is Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , HfO ₂ ; Si doped materials below, Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , HfO ₂ ; and Al doped the following materials are, including Ta ₂ O _5, TiO _2, a material selected from ZrO _2, the group comprising HfO _2, the method of claim 9. The step of depositing the gate dielectric layer is performed by a process selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma chemical vapor deposition (PECVD). The method according to claim 9 . Following the step of filling the void with a gate structure, the gate structure and the polysilicon layer are coated with a silicon oxide layer, and then the gate structure and the polysilicon layer are exposed by chemical mechanical polishing, The method of claim 1, comprising planarizing a top surface of the gate structure. Following the step of planarizing the top surface of the gate structure, a metal layer is deposited on the top surface of the gate structure and is in electrical contact with the source region, the gate region, and the drain region by the metal of the metal layer. The method according to claim 12 , comprising forming an electrode to be formed. 14. The method of claim 13 , comprising depositing a metal layer on top of the gate structure and annealing to facilitate a salicide process prior to forming the electrode. The method of claim 1 , wherein the silicon tin alloy is represented as Si _1-X Sn _X , where x is 0.05 or greater .

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