JPH0567785A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent lowering of a drain breakdown voltage, to increase a resistance of a diffusion region and to prevent contact defective by providing a film thickness of a channel region of a semiconductor layer with specific relation with impurity concentration, dielectric constant, Fermi energy and basic charge of electron of the channel region. CONSTITUTION:A source/drain 5 is selfmatchingly formed to an n-type impurity concentration of 5X10<20>cm<-3> and a diffusion layer depth of about 0.15mum using a gate electrode 8 as a mask. A thickness T1 of an Si layer 3 at a groove bottom part is 700Angstrom , for example and this is thinner than a thickness which realizes complete depletion of a bottom part region of a groove which becomes a part of the channel region in an operation state of an element. That is, it satisfies conditions of T<=[2epsilonphiF/qNsub)]<1/2>. Here, Nsub shows an impurity concentration (cm<-3>), epsilon shows dielectric constant, phiF shows Fermi energy (eV) and q shows a basic charge (coulomb) of electron of a silicon layer. Problems are thereby solved and performance and reliability are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET device, and more particularly, to a thin film SOI having improved FET device characteristics.
It relates to the structure of a MOSFET.

[0002]

2. Description of the Related Art SOI (Silicon on Ins)
The MOSFET formed on the ultor) film is a promising device in that it has advantages such as latch-up free and low floating capacitance. In particular, it has been reported that when the SOI film is thinned so that the channel region is fully depleted in the operating state, performances such as improvement of punch-through resistance and reduction of punch-through effect are improved (IEDM: Techni).
cal Digest. p107, 1982).

FIG. 40 is a sectional view showing a MOSFET having the element structure of such a semiconductor device. That is, the SiO ₂ insulating film 2 is provided on the silicon film 1, and the SOI film 3 is formed on the SiO ₂ insulating film 2. A gate electrode 8 is formed on the surface of the SOI film 3 via a gate oxide film 6.
Source / drain regions 5 are formed on both sides of the gate electrode 8.
n and a channel region 16p are formed.

In FIG. 40, 9 is an insulating film and 10 is an electrode.

Here, the SOI film 3 has a thickness of 500 so that the channel region 16p is fully depleted in the operating state of the device.
It has been thinned to a thickness of Å.

Therefore, as a result of detailed examination of the characteristics of the above-mentioned conventional element by the inventors of the present invention by simulation and actual measurement, as the element becomes finer, the drain current rapidly increases with the drain voltage, so that the drain breakdown occurs. It has become clear that this is likely to occur, and as a result, the usable power supply voltage is significantly limited. This is because a region having a low potential is formed at the boundary between the source and the channel SOI part, and holes generated by impact ionization near the drain are accumulated in the region. That is, when holes are accumulated between the source channel SOI, the source channel SO
The energy barrier between I is lowered and an excessive current flows, resulting in drain breakdown.

On the other hand, when the SOI film is made thin, the following problems occur in addition to the above problems. That is, when the SOI film is thinned, the source / drain diffusion regions formed in the SOI film are inevitably thinned, and the resistance of the diffusion region is increased to cause a decrease in current amplification factor. Further, when the contact hole is opened to the thin diffusion region by the dry etching method, the SOI film in the contact hole portion is scraped off, and there is a problem that electric wiring thereafter becomes impossible. That is, SO
It has been difficult to sufficiently bring out the capability of the MOS transistor with the thinning of the I film.

[0008]

As described above, conventionally, in the semiconductor device in which the MOS transistor is formed on the thin SOI film, there is a problem that the drain breakdown voltage is lowered as the element is miniaturized. Further, there is a problem that the resistance of the diffusion region is increased due to the thinning of the SOI film and contact failure is caused by disappearance of the diffusion region when the contact hole is opened.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the drain breakdown voltage of a MOS transistor formed in an SOI film and to increase the operation speed. To provide.

Another object of the present invention is to prevent the contact failure due to the increase in the resistance of the source / drain diffusion region accompanying the thinning of the SOI film and the disappearance of the diffusion region when the contact hole is opened. It is an object of the present invention to provide a semiconductor device which can sufficiently bring out the capability of a MOS transistor associated with thinning.

[0011]

The essence of the present invention is that the thickness of the SOI film is made sufficiently thin so that the channel region is completely depleted in the operating state of the device, and the channel region and the source / drain diffusion region are formed. Is to optimally set the conductivity and thickness of the.

That is, according to the present invention, a pair of high-concentration impurity diffusion regions (source / drain regions) provided at a predetermined distance in a semiconductor layer formed on an insulating film and sandwiched between the diffusion regions. In a MOS semiconductor device including a gate electrode formed on a channel region via a gate insulating film, the thickness T of the second semiconductor layer in the channel region is set to the impurity concentration of the second semiconductor layer in Nsub (cm ^-3 ), permittivity ε, Fermi energy φ _F (eV), and electron basic charge q (clone), set T ≦ [2ε φ _F / (qNsub)] ^1/2 and source The drain diffusion layer and the insulating film below these diffusion layers are not in contact with each other.

Also, the semiconductor layer has a recess.

Further, the high concentration layer is provided in a part of the semiconductor layer (channel region) between the source / drain diffusion layer region and the insulating film on the substrate.

[0015]

[Operation] (1) According to the present invention, a thin film SOI MOSFE
Despite T, since the source / drain regions are formed without making contact with the first substrate isolation insulating film layer, holes generated by impact ionization are not formed in the source region near the channel but in the region distant from the channel. Disperse and accumulate. Further, a back gate bias is applied to the ground voltage or a negative potential to increase the moving speed of holes, reduce the holes from the channel region, and provide a hole escape hole in the second semiconductor region to generate a large amount from the channel region. Since it has the effect of reducing holes, it is unlikely to affect the channel region. For this reason, a highly reliable MOS that is unlikely to cause drain breakdown of MOSFET characteristics
A FET can be realized.

(2) In addition, by using a trench type thin film SOI MOSFET in which the gate electrode is embedded in the recess of the semiconductor region, the depletion layer from the source / drain can be formed by the conventional MO transistor.
It does not penetrate deeply into the channel like SFET.
Therefore, even if the depth X _j of the source / drain diffusion layer is large, it is possible to suppress the influence of the short channel effect accompanying the expansion of the depletion layer extending from the source / drain diffusion layer as much as possible.

(3) Further, by providing the source / drain regions by the n ⁺ impurity layer and the n ⁻ impurity layer penetrating the groove above the side wall of the groove, a so-called LDD structure is formed and the drain breakdown voltage is remarkably improved. To do.

(4) Furthermore, by providing a high-concentration impurity layer below the source / drain, holes generated by impact ionization can be efficiently collected in the p-type impurity layer, and the channel region can be formed. It is possible to reduce the influence of the accumulated holes on the drain and improve the drain breakdown voltage.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a semiconductor device of the present invention will be described in detail below with reference to the drawings.

FIGS. 1, 2 and 3 are a plan view of the MOSFET of the first embodiment according to the present invention and a sectional view taken along the line AA ', B of FIG.
It is a -B 'sectional view. As shown in FIG. 2, a SiO ₂ layer (insulating film) 2 having a thin film of about 0.4 μm is formed on a Si substrate 1, and a film having a film thickness of about 0.3 μm is formed thereon with an impurity concentration of 1 × 10 ¹⁶ cm. A p-type Si layer ^{3 of} about ^-3 is formed, and a MOSFET is formed there. The p-type Si layer 3 is separated by an element isolation insulating film 7, and an impurity concentration of 5 ×
N ^{− of} about 10 ¹⁸ cm ⁻³ and a diffusion layer depth of about 0.15 μm.
The type diffusion layer 4n is formed, and the depth d = 0.
A depression (groove) of about 23 μm is formed. Here, about 0.1 μm is provided between the element isolation insulating film 7 and the SiO ₂ layer 2.
There are some differences. Further, in this region, a filled ion implantation layer 24 for preventing channel inversion is formed as in a normal bulk MOSFET.

The bottom region Si layer 3 of the groove is formed very thin on the SiO ₂ layer 2, and the film thickness of that portion is T ₁ . The channel region is composed of this thin Si layer 3 and the bottom side surface of the groove. S for forming the source / drain diffusion layer 5
The film thickness of the i layer 3 is T ₂ . Further, a gate electrode 8 is formed on the surface of the Si layer 3 via a gate insulating film 6 so as to cover the groove. In the figure, 9 is an insulating film and 10 is an electrode. Here, the film thickness of the insulating film 11 where the source / drain 5 and the gate electrode 8 face each other may be formed thicker than that of the gate insulating film in order to reduce the coupling capacitance. For example, 15 in the groove
nm, and the thickness is 100 nm on the upper surface of the substrate.

The source / drain 5 is formed in a self-aligning manner with the gate electrode 8 as a mask, with an n-type impurity concentration of 5 × 10 ²⁰ cm ⁻³ and a diffusion layer depth of about 0.15 μm. The thickness T ₁ of the Si layer 3 at the bottom of the groove is, for example, 700Å, which is smaller than the thickness at which the bottom region of the groove, which is a part of the channel region in the operating state of the device, is completely depleted. .. That is, T ≦ [2εφ _F / (qNsu
b)] It satisfies the condition of ^1/2 . Here, Nsub is the impurity concentration (cm ⁻³ ) of the silicon layer 3, ε
Is the permittivity, φ _F is the Fermi energy (eV), and q is the basic charge (Coulomb) of the electron.

FIG. 4 shows a p ^- channel MOSF according to this embodiment.
This is a modified example when applied to ET and corresponds to the AA ′ cross section of FIG. 1. This embodiment is the same as the previous embodiment except that the semiconductor layer 3n is an n ⁻ layer, the source / drain 5p is a p ⁺ layer, and the diffusion layer 4p on the side wall of the recess is a p ⁻ layer. The same symbols are attached to the symbols of the part.

Next, one embodiment of the manufacturing process of such a MOSFET will be described with reference to FIGS. That is, FIGS. 5 to 11 are sectional views of the manufacturing process corresponding to FIG. 2 of the embodiment shown in FIGS.

First, as shown in FIG. 5, for example, a SiO ₂ film 2 having a thickness of about 4000 Å is formed on a Si substrate 1, and a p ⁻ type Si film having a film thickness of about 3000 Å and an impurity concentration of about 1 × 10 ¹⁶ cm ^{−3 is} formed thereon. Form the layer 3p.

As a method of forming such an SOI substrate, Si substrates 1 are bonded to each other with an oxide film 2 interposed therebetween, and then one Si substrate 1 is lapped and mirror-polished.
A so-called bonding method, a so-called SIMOX method in which oxygen ions are ion-implanted with a high dose and a high acceleration and then annealed at a high temperature.

There is a so-called electron beam annealing method in which the polycrystalline silicon film on the SiO ₂ film 2 is melted and recrystallized by an electron beam or the like and then etched to make it thin, but any method may be used. Further, the film thickness of the SiO ₂ film 2 is not limited to this.

Next, as shown in FIG. 6, an n-channel type MOS
The n ⁻ -type diffusion layer 4n is implanted only in the region where the FET is formed, for example, phosphorus (p ⁺ ) ions are implanted at 100 Kev, 4 × 10 ¹³ c.
It is formed by ^performing about m ^-2 . This step is subsequently formed 2
It may be performed through a 0 nm thermal oxide film (not shown). Further, it may be performed in the next step after processing the Si layer 3 into an element formation region pattern. The patterning of the Si layer 3 was performed by etching so as to leave a film thickness of about 0.1 μm in a portion other than the element formation region.

That is, after forming a mask layer 11 made of a CVD-SiO ₂ film having a film thickness of, for example, about 10 nm on the entire surface, a resist (not shown) is patterned by photolithography, and the resist is used as a mask to form reactive ions. The mask layer 11 is first etched by an etching (hereinafter abbreviated as RIE) method or the like, and then the Si layer 3 is etched by RIE using, for example, a chlorine-based or fluorine-based gas to divide each element forming region.

The resist may be removed before the etching of the Si layer 3.

This mask layer 11 is used as a mask material during RIE, but is also used as an etching stopper in a later step. This mask layer is also used as CVD-Si ₃ N.
_It may be _four membranes or a composite membrane with them.

Next, as shown in FIG. 7, S in each element formation region
The side surface of the i layer 3 is thermally oxidized to, for example, about 20 nm of Si.
After the O ₂ film 12 is formed, for example, boron is ion-implanted at about 30 KeV and 1 × 10 ¹³ cm ⁻² to prevent field inversion, and the p-type layer 24 is selectively formed only on the bottom surface of the isolation trench.
By forming p, further depositing a CVD-SiO ₂ film or the like on the entire surface, and using a so-called etch-back flattening method using a resist or the like, the insulating film 7 for isolation between the element regions formed previously is formed. Form.

After forming a resist film 13 on the entire surface, the resist film 13 is patterned by photolithography, and the mask layer 11 and then the Si layer 3 are etched by the RIE method using this as a mask. A groove 14 is formed in the groove. At this time, the film thickness T ₁ of the Si layer 3 left on the bottom surface of the groove 14 is important and needs to be sufficiently controlled to, for example, about 700 Å. That is, this film thickness is set so as to satisfy the condition of being completely depleted in the operating state of the element as described above.

Next, as shown in FIG. 8, the RI of the inner wall of the groove 14 is
The damage layer caused by E is formed by dry O ₂ oxidation and NH ₄ F, for example.
After removal by etching with a liquid, for example, the thermal oxide film 1
5 is formed, and then, for example, boron (B ⁺ ) ions are added to 1
The p-type channel impurity layer 16p may be selectively formed only in the bottom region of the groove by performing ion implantation at 0 KeV and 5 × 10 ¹¹ cm ⁻² . By adjusting the film thickness of the thermal oxide film 15, the p-type layer 16p can be selectively formed at the bottom of the groove. Ion implantation may be performed with a slight tilt to prevent channeling, or vertical ion implantation may be used to implant only on the bottom surface of the groove. This step may be omitted because channel ion implantation is no longer effective in controlling Vth, which is a feature of the thin film SOI transistor.

After the thermal oxide film 15 is selectively removed, a gate insulating film (SiO ₂ film) 6 of about 15 nm is formed as shown in FIG. The gate electrode 8 is formed by depositing a film and patterning it.

Thereafter, a thick oxide film 17 of about 150 nm is formed on the surface of the poly-Si gate electrode 8 by thermal oxidation in an O ₂ / H ₂ O atmosphere at 850 ° C., for example. This has the role of improving the masking property of the poly-Si gate electrode 8 during counter ion implantation. Next, the mask layer 11 in the source / drain regions is removed and exposed, and then, for example, a thermal oxide film 18 is formed to a thickness of about 10 nm, and arsenic (As ⁺ ) is passed through this, for example, at 50 KeV and 5 × 10 ¹⁵ cm ^{−. About 2} ions are implanted to form an n ⁺ -type impurity diffusion layer 5n (see FIG. 1).
0).

Next, as shown in FIG. 11, a CVD-SiO ₂ / BPSG film of 600 n is formed as an interlayer insulating film 19 on the entire surface.
m, and a BPSG melt process at 850 ° C. for about 60 minutes to flatten the entire surface.
Open a contact hole 20 to the gate electrode, for example A
The l film is deposited on the entire surface, and the Al film is patterned by the photolithography technique and the RIE method to form the wiring layer 10. Thus, the MOSFET according to the embodiment of the present invention
Is obtained.

FIG. 32 shows the result of comparison of the drain current-drain voltage characteristics of the element thus obtained according to the example and the conventional element. In the device of this example, the drain breakdown voltage of 2.5 V was significantly improved to 6 V in the n-channel MOSFET having a channel length of 0.3 μm. The reason for this is that the electric field near the drain is relaxed by the structure of the present invention.

Further, the structure of the embodiment of the present invention has a channel S
Despite the thinning of the i layer, the source / drain diffusion layer depth X _j can be designed deep without being restricted by the film thickness of the Si layer in the channel region as in the conventional example. The source / drain diffusion layer resistance and contact resistance can be reduced. That is, it is possible to prevent the deterioration of the device characteristics such as the decrease of the drain current due to the increase of the parasitic resistance.

Further, in the structure of the embodiment of the present invention, since the source / drain regions are located above the channel region, the influence of the extension of the depletion layer from the drain is suppressed and the structure is strong against the punch-through between the source / drain. And the short channel effect is improved.

Further, the structure of the embodiment of the present invention has a channel S
Since the thickness of the i layer can be controlled by etching, the S
It is also possible to change the film thickness of the i layer not uniformly but individually, and as a result, the degree of freedom in element design is increased, circuit design is facilitated, and performance is improved.

The structure of the embodiment of the present invention not only reduces the impact ionization rate by relaxing the electric field in the vicinity of the drain, but, for example, even when electrons and holes are generated by impact ionization, the vicinity of the source of the channel portion as in the conventional case. The holes are not accumulated in the area, and most of them are gathered under the source region away from the channel region, which makes it difficult to affect the channel. Here, as shown in FIG. 2, the element isolation insulating film 7 is not in contact with the SiO ² layer 2 so as to form an escape route for these storage holes (n-channel) and storage electrons (p-channel). With this, further effects can be obtained.

12 to 22 are sectional views for explaining another embodiment of the present invention, and are drawings corresponding to the AA 'sectional view of FIG.

First, FIG. 12 shows a second embodiment according to the present invention. In FIG. 1, the source / drain regions are so-called LDs.
It was designed to have a D (Lightly Doped Domain) structure, but as shown in FIG. 12, a so-called GDD (Graded Diffused Drain) is used.
n) The structure may be adopted. At this time, the source
The process may be changed so that not only the n ⁻ diffusion layer 4n but also the n ⁺ diffusion layer 5n is simultaneously formed at the time of implanting impurities into the drain (step of FIG. 6).

In this way, a step of forming an n ⁺ diffusion layer later (particularly in the case of CMOS, which is complicated because n ⁺ and p ⁺ are separately formed using a resist step) can be omitted. There is a merit of simplification.

Next, a third embodiment of the present invention will be described with reference to FIG. In the first embodiment, the source / drain regions have a so-called LDD structure as shown in FIG. 2 to relax the electric field near the drain.
In the case of the concave MOSFET as described above, since the structure itself has the effect of relaxing the drain electric field, even if the structure is the single source / drain 22 instead of the LDD,
The drain breakdown voltage is improved due to the relaxation of the drain electric field as compared with a normal thin film SOI MOSFET.

It is possible to prevent characteristic deterioration such as decrease in drain current due to increase in parasitic resistance of source / drain and contact resistance.

It is possible to reduce the short channel effect by suppressing punch-through for source / drain.

SOI M with thin Si channel layer
Features such as realization of an OSFET, optional Si channel layer, and design of film thickness can be realized.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, unlike the first embodiment, the gate electrode 8a does not extend to the source / drain portions, and the gate electrode is retained only in the groove. By doing so, the distance between the gate electrode 8 and the contact hole of the source / drain can be reduced, and the structure is suitable for miniaturization.

FIG. 15 shows a modification of the fourth embodiment in which the gate electrode 8 is completely embedded in the groove. By doing so, the steps can be reduced, the flatness can be improved, and the processing of the upper layer can be made easier.

14 and 15 show a single source / drain structure and a source / drain structure, an LDD structure using a spacer material formed by leaving the sidewalls and an LDD (Lightly Dope) using mask alignment.
d Drain) structure may be used.

Next, a fifth embodiment according to the present invention will be described with reference to FIG.
Will be explained. In the first embodiment, the so-called trench isolation method is used for element isolation, but a so-called selective oxidation method (LOCOS method) as shown in FIG. 16 may be used instead. At this time, the thick field oxide film 23 formed by the selective oxidation method is brought into contact with the substrate insulating film layer 2. In this way, the impurity formation step for preventing field inversion is not required, and the step can be simplified. Such a structure in which the field oxide film is not in contact with the SiO ₂ layer 2 can be applied to the above-described embodiments and the following embodiments.

As a modification of the fifth embodiment, there is also an embodiment as shown in FIG. At this time, the field oxide film 2
3 is not in contact with the substrate insulating film layer 2 and requires the impurity layer 24p for field inversion prevention, but a relatively thin field oxide film 23 is sufficient and the process can be shortened and simplified.

Next, a sixth embodiment according to the present invention will be described with reference to FIG. Although the formation of the channel / ion-implanted layer was not described in detail in the first embodiment, the p-layer 25 may be formed only in the thin film Si channel layer as in FIG. For this purpose, a protective film is provided on the side surface of the groove and is formed by the vertical ion implantation method. According to the structure of the present invention,
Since the p layer 25 is selectively present on the bottom surface of the groove, the threshold V
th is determined, and the channel region on the other side surface of the groove does not contribute to Vth determination. That is, the threshold value of the bottom of the groove is higher than the threshold value of the p ⁻ region on the side surface of the groove. Therefore, during operation, the resistance of the side surface is small and the source / drain regions are located above the P layer 25 at the bottom of the groove, which is the main channel region.
It is not easily affected by the extension of the depletion layer from the drain. Therefore, the short channel effect can be prevented, and at the same time, a larger driving capability can be obtained as compared with the MOSFET having the same channel length.

Further, FIG. 19 shows a seventh embodiment of the present invention. In the first embodiment, the contact was opened in the source / drain diffusion layer in the SOI layer.
An impurity-doped polycrystalline silicon layer 26 is formed on the source / drain layer of the OI substrate and electrically connected to it, and source / drain contacts are opened therein. By doing so, the contacts for the source / drain can be extended over the element isolation region, which is suitable for increasing the density of the element. 27 is an electrode. 5n is an n ⁺ impurity diffusion layer from the polycrystalline silicon layer 26 or an n ⁺ diffusion layer generated by n ⁺ impurity ion implantation for ensuring electrical connection.

Further, FIG. 20 shows an eighth embodiment of the present invention. In the first embodiment, both are realized by making a groove in the SOI substrate to obtain a thin channel layer and a deep diffusion layer in the source / drain regions. In this embodiment, the structure is subjected to selective epitaxial growth (SEG). It has been realized by using it. Reference numeral 29 is an insulating film, and 27 is an electrode.

That is, the thin SOI film 3 (film thickness = T ₁ )
Then, the diffusion layer depth X _j of the source / drain is formed to be shallower than T ₁ , and only the exposed surface of the source / drain portion is formed with the epitaxial silicon layer 28 on the source / drain by the selective epitaxial growth method. This layer 28
May be a polycrystalline silicon layer. The selective epitaxial silicon layer 28 is doped to electrically connect to the source / drain and open the source / drain contact. By doing so, even if the source / drain diffusion layer is formed to be shallower than the channel silicon film thickness T ₁ of the thin film SOI layer, the selective epitaxial silicon layer is formed thicker thereon, so that the source / drain diffusion layer is formed. The resistance never increases. Further, the same effect can be obtained without etching the SOI substrate.

Further, FIGS. 21 and 22 show ninth and tenth embodiments of the present invention. 21 and 22 respectively form the gate electrode 30 by the selective epitaxial silicon growth of FIG. 20 of the eighth embodiment, and the gate electrode 30 is covered with the insulating film 31.
It is done after covering with, and the source / drain n ⁺
When the diffusion layer 31 and the n ⁻ diffusion layer 4n are located above the channel surface (FIG. 21), the source / drain n ⁻ diffusion layer 32 is formed.
This is the case where n is set below the channel surface and above the substrate insulating film 2 (FIG. 22). Reference numeral 6 in FIG. 22 is an insulating film.

In either case, the thin film SOI MOSFET
In addition to the merit that it is not necessary to etch the Si layer in order to realize the above, the ninth embodiment shown in FIG. 21 projects the depth X _j of the n ⁺ and n ⁻ impurity layers into the channel region of 3p. Since it is not performed, the short channel effect can be suppressed.

Next, FIG. 23 shows an eleventh embodiment of the present invention. In this embodiment, instead of the p-type semiconductor layer 3p, the i-type semiconductor layer 33 (n-type and p-type carrier concentrations (donor concentration,
MO has the same McScepter concentration) and exhibits characteristics as an intrinsic semiconductor) as a semiconductor layer on the insulating film, and the i-type semiconductor layer 33 is left in the channel region.
It is an SFET structure. A p-type Si layer 34p is formed under the source / drain regions.

Since the p-type layer 34 is under the source / drain regions, holes generated by impact ionization do not accumulate in the channel region and the p-type Si layer 34p is formed.
Since it can be collected in the device and discharged through the p-type impurity layer 24p below the element isolation film, a highly reliable MOSFET can be realized even in a thin film MOSFET. At this time, the threshold value is determined by the side surface of the groove, and the threshold value can be set by controlling the concentration of the p-type Si layer 34p.

24 to 25 are views showing the positional relationship of the p-type layer 34p in the eleventh embodiment of FIG. 23, and FIG.
24, unlike the case where the p-type layer 34p extends to the end of the thin film channel region (i-type Si layer 33) as shown in FIG.
The structure is such that the mold layer 34p is separated from the thin film channel region, and as shown in FIG. 25, the mold layer 34p is embedded in the p-type layer 34p thin film channel region 33. In any case, the same effect is obtained.

Further, FIG. 26 shows a modification of the eleventh embodiment of the present invention. 23 to 25, the thin film i-type MOSFET and the p-type Si layer 34p under the source / drain regions are realized by forming a recess in the i-type Si layer 33, but the same structure can be realized by other methods. .. FIG. 26 shows an example thereof.

First, a thin i-type Si layer 33 (thickness T) is formed, a gate electrode 8 is formed via the gate insulating film 6, and then an n ⁻ layer 4n and a p-type layer 34p are formed. At this time, increase in source / drain resistance (increased parasitic resistance)
To prevent this, the Si layer 35 is formed in the source / drain openings by selective epitaxial growth or the like to form the source / drain. With such a method, a structure having the same effect as in FIGS. 23 to 24 can be obtained. With this structure, it is not necessary to etch the i-type Si layer 33 as compared with FIGS. 23 to 25, so that the film thickness of the i-type Si layer 33 can be easily controlled.

Next, a twelfth embodiment of the present invention will be described.
FIG. 27 shows the structure of FIG. 23 as a p-channel thin film SOI MOS.
This is an example applied to a FET. In this case, p in FIG.
The n-type layer 36 is used instead of the mold layer 34. This structure has the effect of collecting the electrons generated by impact ionization in the n-type layer 36, and can improve the reliability of the MOSFET. 38 is a p ⁺ layer, and 37 is a p ⁻ layer.

Next, a manufacturing method of the eleventh embodiment shown in FIG. 23 will be described. 28, 29, 30, and 3
1 is a process sectional view.

First, a thin film having an i-type Si layer 33 of about 3000 Å formed on the insulating film 2 is prepared (FIG. 28).
After the n ⁻ type layer 4n is formed on the i type Si33 layer, it is processed using the mask layer 39, and p for field inversion prevention is formed.
After forming the mold layer 24, the element isolation-like insulating film 7 is embedded in the element isolation region (FIG. 29). Next, in order to form a thin channel region (film thickness T) of the MOSFET, for example, RI
Part of the i-type layer 33 and the n ⁻ layer 4 is etched by the E method to obtain a desired film thickness T (FIG. 30). Then, after removing the mask layer 39, the gate electrode 8 is formed via the gate insulating film 6, and the p-type layer 34p and the n ⁺ diffusion layer 5n to be the source / drain layer are sequentially formed by ion implantation or the like. Formed (FIG. 31). The range of the p-type layer 34p can be realized by adjusting the ion implantation conditions and the subsequent thermal process, and any structure shown in FIGS. 23, 24, and 25 can be applied.

Next, FIGS. 33 and 34 show the twelfth and thirteenth embodiments of the present invention. In this example, the source / drain n-type layers 4n, 4n,
Although the p-type layer 34p is formed under 5n, the i-type layer 40 is further formed under the p-type layer 34p. In this way, the formation of the p-type layer 34p is prevented by the n ^-- type layer 4n.
There is an advantage that it can be stably formed below. See also FIG.
3, FIG. 34 shows that the thin film channel region (thin film T) is the p-type layer 3
When it is thinner than the i-type layer 40 under 4p (FIG. 33)
And the case where the i-type layer 40 under the p-type layer 34p has the same thickness as the thin film channel region (film thickness T) (FIG. 34). Both have the same effect.

In this case, the threshold value can be determined by the p layer (34p) on the side wall of the groove.

Next, the manufacturing method of these examples will be described.

FIGS. 35, 36 and 37 are shown in FIGS.
4 is a process cross-sectional view for realizing the structure of FIG. First, as shown in FIG. 35, n ^{− is formed on} the entire surface of the i-type layer 40.
The type layer 4n and the p-type layer 34p are formed by, for example, an ion implantation method or the like, and the p-type layer 34p is stably formed on the entire surface below the n-type layer. This p-type layer 34p corresponds to a channel impurity layer for determining the threshold voltage of this MOSFET. Next, after processing each element formation region into an island shape using the mask layer 41,
The field inversion prevention impurity layer 24p and the insulating film 7 for element isolation are buried in the element isolation region. Next, a concave groove to be the thin film channel region is formed. At this time, the bottom of the groove has a film thickness T (FIG. 36). After that, the gate electrode 8 is formed via the gate insulating film 6, then the source / drain n ⁺ type diffusion layer 5n is formed, the interlayer insulating film 19 is deposited on the entire surface, the contact hole is opened, and the metal wiring is formed. 10
To form. Although the LDD structure is adopted here, a single drain structure of only n ⁺ may be adopted.

In the present embodiment described above, the gate electrode 8 is set to the threshold value Vth (for example, n-channel MOS).
FET + about 0.2 to 1.0V, p-channel MOSF
ET-0.2 to-1.00 V or so) from the n- channel p ⁺ poly-Si electrode is, in the p- channel using N ⁺ poly-Si electrode but, for example metal gate to the threshold to the desired value (W Etc.) or a back gate bias may be applied to the substrate 1.

Although the main part of the MOSFET has been described with reference to the drawings in the above embodiment, it may be shown in the perspective view of FIG. The parts corresponding to those in the above-described embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. As shown in the figure, the p layer 3p on the SiO ₂ layer 2 is a body contact region 42p formed of ap ⁺ layer provided separately from the transistor.
It is connected to the. The body contact region 42p is normally set to a ground potential or a negative potential, but in some cases, it is set to a negative potential for threshold adjustment or the like.

By providing such a body contact region 42p, as shown in the schematic view of FIG. 39, holes and the like generated during the operation of the element can be discharged very favorably, which adversely affects the element characteristics. Can be excluded.

FIG. 41 shows a C using the MOSFET of the present invention.
FIG. 47 is a cross-sectional view in the channel length direction when the MOS inverter circuit (FIG. 46) is configured.

In this embodiment, n-channel MOSFE is used.
The thresholds of the T and p-channel MOSFETs are determined by the p region 16p and the n region 16n at the bottom of the groove. N-channel MOSFET, p-channel MOSFET
A p-type impurity layer 24p and an n-type impurity layer 24n for preventing field inversion are formed below the element isolation insulating film 7 that electrically isolates the. Also, each M
In the OSFET, accumulated holes (n
-Channel) or accumulated electrons (p-channel) are escaped from the channel region, body contacts (bc) corresponding to so-called normal bulk MOSFET substrate contacts are formed as p ⁺ regions 42p and n ⁺ regions 42n. By adopting such a structure, holes, electrons, etc. generated during the operation of the device can be discharged extremely well to other than the channel region, and the adverse effect on the device characteristics can be eliminated.

At this time, the p-type impurity layer 24p for preventing field inversion and the n-type impurity layer 24n may be in contact with each other immediately below the element isolation insulating film 7, as shown in the figure.

Next, FIG. 42 shows a second embodiment of the present invention. 42 is an n-channel MOSFE in FIG.
This is for a structure in which an element isolation insulating film 7a for separating T and p-channel MOSFETs is formed so as to be in contact with the insulating film 2 in the substrate. In this way, it is necessary to increase the depth of the groove for burying the insulating film only in this portion, but it is certain that the n-channel MOSFET and the p-channel M are surely formed.
There is an advantage that the OSFET can be separated and the latch-up and the parasitic bipolar effect can be completely prevented.

Next, FIG. 43 shows a third embodiment of the present invention. 43 shows that all the element isolation insulating films 7 in FIG.
This is a structure in which a is formed in contact with the insulating film 2 in the substrate.

This has the advantage that the elements can be completely separated.

The structures common to FIGS. 41, 42 and 43 are the n-channel MOSFET and the p-channel M, respectively.
In the OSFET, the threshold value is determined by the p layer 16p and the n layer 16n at the bottom of the groove. Further, it is a common structure that the main regions (p layer 16p, n layer 16n) of each channel are set to a film thickness T ₁ so that they are completely depleted during operation. Back gate voltage (V
bg) is used for adjusting the threshold voltage of each MOSFET.

The gate electrode material 8 is an n-channel M.
A p ⁺ -type polycrystalline silicon film is generally used for the OSFET and an n ⁺ -type polycrystalline silicon film is used for the p − channel MOSFET, but a metal gate (W or the like) may be used to set the threshold value to a desired value.

Next, FIG. 44 shows a third embodiment of the present invention. In FIG. 44, the arrangement of impurities in the channel of the MOSFET in FIG. 41 is changed. That is, in the case of an n-channel MOSFET, the p-type layer 34p is formed below the source / drain n-type layers 4n and 5n, but the i-type layer 40 is further present below the p-type layer 34p. In the case of a MOSFET, the structure is such that the n-type layer 34n is present under the source / drain p-type layers 4p and 5p, and the i-type layer 40 is present underneath. These MOSF
Figure 4 shows the configuration of the CMOS inverter using ET.
It is 4.

In this way, the main channel region (bottom of the groove) becomes the i-type semiconductor layer and the impurity concentration is not high, so that the mobility of electrons and holes is increased and the device characteristics are improved. Further, since the thickness of T ₁ can be made relatively large, there is an advantage that the margin of process controllability is increased and the product yield is improved. Furthermore, such a MOSFET
Threshold value is p layer 34p in the case of n-channel on the side wall of the groove
(N layer 34n in the case of p-channel) determines the controllability of the threshold value. Further, the p-layer 34p near the source / drain is divided by the i-type layer 40 at the bottom of the concave groove, and the p-layer 34p on the source side has a structure that is not easily affected by the expansion of the air-deficient layer from the drain. The structure is strong against the short channel effect. Electrons and holes generated in the vicinity of the channel region due to ion-pact ionization do not affect the device characteristics.
It is possible to satisfactorily discharge by applying a normal ground potential, a negative potential (n-channel), or a positive potential (p-channel) to the t) region (42p, 42n).

Next, FIG. 45 shows a fourth embodiment of the present invention. 45 shows a structure in which the formation of the p-type layer 34p and the n-type layer 34n in FIG. 44 is realized by, for example, combining the ion implantation method and the thermal diffusion method after the gate electrode 8 is formed. In this structure, only i is formed in the channel region at the bottom of the groove.
There is no type layer 40, and the p-type layer 3 is provided below the sheath / drain layer.
4p (for n-channel) or n-type layer 34n (for p-channel) is formed.

By doing so, since the i-type layer is present in a part of the channel, the mobility of electrons or holes is improved,
Element characteristics are improved. Further, since the film thickness of T ₁ can be made relatively thick, the etching controllability at the time of forming the groove is improved. Further, the threshold value is p layer 34p (n-channel) on the sidewall of the groove, or n
The controllability is improved because it is determined by the concentration of the layer 34n (p-channel). It is also strong against the short channel effect, and has the advantage of being able to perform efficiently because it is possible to lower the resistance under the source / drain when releasing the accumulation holes and electrons.

Next, FIG. 47 shows a modification of FIG. 41 of the present invention. 41 to 45 show an example in which a buried insulating film is used as the element isolation insulating film, but a conventional selective oxidation method (so-called LOCOS method) may be used as shown in FIG. 47. In this example, the LOCOS oxide film is the insulating film 2 in the substrate.
Needless to say, it may be formed so as to come into contact with, though it is not in contact with.

By providing such a body contact region 42, holes and the like generated during the operation of the element can be discharged very well as shown in the schematic view of FIG. 39, which has a bad effect on the element characteristics. Can be excluded.

Although the present invention has been described with reference to various embodiments, the present invention is not limited to this. The structure can be variously modified. For example, the p-type impurity layer in the channel region does not need to exist only in the bottom of the groove, and may penetrate to the middle of the groove, for example. Further, a very low concentration channel impurity layer may be used.

Further, this embodiment is an n-channel MOSFE.
Although the impurity type was illustrated based on T, p-channel MOS
In the case of FET, it may be changed to impurities of the opposite conductivity type.

It should be noted that the impurity concentration of each region may be another one as exemplified, and the p-type semiconductor substrate 1 may have a concentration of 1 × 10 ^{15 to} 5 × 5.
× 10 ¹⁷ cm ^-3 , the p-type impurity of the channel is 1 × 10 ¹⁵ ~
5 × 10 ¹⁷ cm ⁻³ , the source / drain n ⁻ -type impurity layer 4 is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , the n ⁺ -type impurity layer 1
6 is selected from 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ .

Other various modifications can be implemented without departing from the spirit of the present invention.

[0094]

As described above, according to the present invention, the problems of the conventional thin film SOI-MOFET are improved, the drain withstand voltage is improved, the source / drain parasitic resistance is suppressed, the short channel effect is prevented, and ion pact ions are generated. Prevents the effects of holes and electrons on the transistor characteristics,
It is possible to obtain a MOSFET having high performance and high reliability such as realization of a high performance CMOS inverter circuit.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is an A-A ′ diagram of the first embodiment of the present invention.

FIG. 3 is a B-B ′ diagram of the first embodiment of the present invention.

FIG. 4 is a sectional view showing a modification of the first embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 6 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 7 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 8 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 9 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 10 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 11 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 12 is a process sectional view illustrating the manufacturing method according to the embodiment of the invention.

FIG. 13 is a cross-sectional view for explaining the third embodiment of the present invention.

FIG. 14 is a sectional view for explaining the fourth embodiment of the present invention.

FIG. 15 is a sectional view for explaining a modification of the fourth embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining the fifth embodiment of the present invention.

FIG. 17 is a sectional view illustrating a modification of the fifth embodiment of the present invention.

FIG. 18 is a cross-sectional view for explaining the sixth embodiment of the present invention.

FIG. 19 is a sectional view for explaining the seventh embodiment of the present invention.

FIG. 20 is a sectional view for explaining an eighth embodiment of the present invention.

FIG. 21 is a cross-sectional view for explaining the ninth embodiment of the present invention.

FIG. 22 is a sectional view for explaining the tenth embodiment of the present invention.

FIG. 23 is a sectional view for explaining the eleventh embodiment of the present invention.

FIG. 24 is a sectional view for explaining the 11th embodiment of the present invention.

FIG. 25 is a sectional view for explaining the eleventh embodiment of the present invention.

FIG. 26 is a sectional view for explaining a modification of the eleventh embodiment of the present invention.

FIG. 27 is a sectional view for explaining a twelfth embodiment of the present invention.

FIG. 28 is a process sectional view for explaining the twelfth embodiment of the present invention.

FIG. 29 is a process sectional view for explaining the twelfth embodiment of the present invention.

FIG. 30 is a process sectional view for explaining the twelfth embodiment of the present invention.

FIG. 31 is a process sectional view for explaining the twelfth embodiment of the present invention.

FIG. 32 is an explanatory diagram illustrating characteristics of the MOSFET according to the example of the present invention.

FIG. 33 is a sectional view for explaining the 13th embodiment of the present invention.

FIG. 34 is a sectional view for explaining the 14th embodiment of the present invention.

FIG. 35 is a process sectional view for explaining the embodiment of the present invention.

FIG. 36 is a process sectional view for explaining the embodiment of the present invention.

FIG. 37 is a process sectional view for explaining the embodiment of the present invention.

FIG. 38 is a perspective view for explaining the embodiment of the present invention.

FIG. 39 is a schematic diagram for explaining an example of the present invention.

FIG. 40 is an explanatory diagram for explaining a conventional problem.

FIG. 41 is a cross-sectional view in the channel direction of the CMOS inverter circuit according to the first embodiment of the present invention.

FIG. 42 is a cross-sectional view in the channel direction of the CMOS inverter circuit illustrating the second embodiment of the present invention.

FIG. 43 is a cross-sectional view in the channel direction of the CMOS inverter circuit illustrating the third embodiment of the present invention.

FIG. 44 is a cross-sectional view in the channel direction of the CMOS inverter circuit illustrating the fourth embodiment of the present invention.

FIG. 45 is a cross-sectional view in the channel direction of a CMOS inverter circuit illustrating a fifth embodiment of the present invention.

FIG. 46 is an equivalent circuit diagram of a CMOS inverter circuit.

FIG. 47 is a sectional view showing a modification of the first embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate (p-type or n-type Si substrate) 2 insulating film (SiO ₂ layer) 3 semiconductor layer (Si layer) 3p semiconductor layer (p ⁻ type Si layer) 3n semiconductor layer (n ⁻ type Si layer) 4n n ⁻ Type Si substrate source / drain diffusion layer 4p p ⁻ type Si substrate source / drain diffusion layer 5n n ⁺ type Si substrate source / drain diffusion layer 5p p ⁺ type Si substrate source / drain diffusion layer 6 gate insulating film (SiO ₂ film) 7 element isolation insulating film 7a element isolation insulating film in contact with insulating film 2 gate electrode 9 field oxide film 10 wiring layer 11 SiO ₂ layer 12 insulating film 13 resist layer 14 groove 15 insulating film 16p high concentration p layer (channel p layer) ) 16n high concentration n layer (channel portion n layer) 17 insulating layer 18 insulating film 19 interlayer insulating film 20 contact hole 22 n ⁺ layer 23 field insulating film 24p feel Reversal preventing p-type impurity layer 24n field inversion prevention n-type impurity layer 25 heavily doped p layer 26 doped polycrystalline silicon layer 27 electrode 28 epitaxial silicon layer 29 insulating film 30 gate electrode 31 n ⁺ layer 32 n ^- layer 33 i-type Semiconductor layer 34p p-type semiconductor layer (Vth determining region) 34n n-type semiconductor layer (Vth determining region) 35 Si layer 36 n layer 37 p ⁻ layer 38 p ⁺ layer 40 i layer 42p p ⁺ type body contact region 42n n ⁺ type Body contact area

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8225-4M H01L 29/78 301 H

Claims (3)

[Claims] 1. A MOS type in which a semiconductor layer is formed on a substrate via an insulating film, a gate electrode is formed on the semiconductor layer via a gate insulating film, and source / drain are formed on both sides of the gate electrode. In the semiconductor device, the film thickness T of the channel region of the semiconductor layer is such that the impurity concentration of the channel region of the semiconductor layer is Nsub (cm ⁻³ ), the dielectric constant is ε, the Fermi energy is φ _F (eV), and the basic charge of electrons Is expressed as q (clone), T ≦ [2εφ _F / (qNsub)] ^1/2 , and the source / drain and the insulating film on the substrate are separated by the semiconductor layer portion. A semiconductor device characterized by. 2. The semiconductor layer has a recess, and a gate electrode is formed in the recess, and the thickness T ₁ of the semiconductor layer in the channel region of the recess below the gate electrode is equal to that in the channel region of the semiconductor layer. Impurity concentration is Ns
ub (cm ⁻³ ), permittivity ε, Fermi energy φ
_F (eV), where the basic charge of electrons is q (clone), T ₁ ≦ [2εφ _F / (qNsub)] ^1/2 and the thickness of the semiconductor layer on which the source / drain is formed The semiconductor device according to claim 1, wherein T ₂ is T ₂ > T ₁ . 3. A MOS type in which a semiconductor layer is formed on a substrate via an insulating film, a gate electrode is formed on this semiconductor layer via a gate insulating film, and source / drain are formed on both sides of the gate electrode. In the semiconductor device, the film thickness T of the channel region of the semiconductor layer is such that the impurity concentration in the channel region of the semiconductor layer is Nsub (cm ⁻³ ), the dielectric constant is ε, the Fermi energy is φ _F (eV), and the basic charge of electrons is Is expressed as q (coulomb), T ≦ [2εφ _F / (qNsub)] ^1/2 , and at least the semiconductor layer between the source / drain diffusion layer region and the insulating film on the substrate has at least this A semiconductor device having a channel region having a higher impurity concentration than a semiconductor layer.