KR100259593B1 - A method of fabricating semiconductor device - Google Patents
A method of fabricating semiconductor device Download PDFInfo
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- KR100259593B1 KR100259593B1 KR1019980009613A KR19980009613A KR100259593B1 KR 100259593 B1 KR100259593 B1 KR 100259593B1 KR 1019980009613 A KR1019980009613 A KR 1019980009613A KR 19980009613 A KR19980009613 A KR 19980009613A KR 100259593 B1 KR100259593 B1 KR 100259593B1
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- semiconductor substrate
- buried insulating
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 110
- 239000010408 film Substances 0.000 description 24
- 238000005468 ion implantation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000011149 active material Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Abstract
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로서, 특히, SOI(Silicon On Insulator) 구조를 갖는 미세화된 반도체장치에서 플로팅 바디 효과(Floating Body Effect)를 제어할 수 있는 반도체장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of controlling a floating body effect in a miniaturized semiconductor device having a silicon on insulator (SOI) structure.
SOI(Silicon On Insulator) 구조는 매립절연층 상에 실리콘 단결정 박막을 형성하고 그 위에 트랜지스터를 포함하는 반도체소자를 형성한 구조이다. SOI 구조는 완전한 소자 분리구조를 실현할 수 있으므로 고속 동작이 가능하고, PN 접합 분리구조에서 나타나는 기생 MOS(Metal Oxide Semiconductor) 트랜지스터나 기생 바이폴러 트랜지스터 등의 능동적 기생 효과가 없으므로 래치 업(latch up) 현상이나 소프트 에러 현상이 없는 회로를 구성할 수 있는 이점이 있다.The silicon on insulator (SOI) structure is a structure in which a silicon single crystal thin film is formed on a buried insulating layer and a semiconductor device including a transistor is formed thereon. Since the SOI structure can realize a complete device isolation structure, high-speed operation is possible, and there is no active parasitic effect such as parasitic metal oxide semiconductor (MOS) transistor or parasitic bipolar transistor shown in the PN junction isolation structure. However, there is an advantage that the circuit can be configured without a soft error phenomenon.
SOI 구조를 형성하는 방법으로는 매립절연층인 산화실리콘 상에 다결정 또는 비정질 실리콘 박막을 퇴적하고 이 실리콘 박막을 가로방향으로 용융 재결정시키고 또한 고상성장시키는 퇴적막 재결정화법, 사파이어 등의 단결정 절연층 상에 단결정을 성장시키는 에피텍셜 퇴적법, 반도체 기판 중에 산화실리콘 등의 절연층을 매입하는 단결정 분리법 등이 있다.The SOI structure is formed by depositing a polycrystalline or amorphous silicon thin film on a silicon oxide, a buried insulating layer, and melting and recrystallization of the silicon thin film in a transverse direction, and solid phase growth. Epitaxial deposition for growing single crystals, and single crystal separation for embedding an insulating layer such as silicon oxide in a semiconductor substrate.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조 방법을 도시하는 단면 공정도이다.1A to 1F are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.
종래에는 도 1a에 나타낸 바와 같이 도전형을 띤 반도체기판(11), 예를 들어, p형의 반도체기판(11)에 SIMOX(Separation by IMplanted OXygen) 등과 같은 통상적인 SOI 형성 방법으로 매립절연층(12)을 형성한다. 상기에서 매립절연층(12)으로 분리된 반도체기판(11)에서 상기 매립절연층(12)의 상부가 활성층(13)이 된다. 그리고, 상기 활성층(13) 상에 버퍼산화막(15) 및 질화막(17)을 순차적으로 형성하고 상기 질화막(17), 버퍼산화막(15), 활성층(13) 및 매립절연층(12)을 순차적으로 패터닝하여 상기 반도체기판(11)의 소정 부분을 노출시킨다.Conventionally, as shown in FIG. 1A, the buried insulating layer 11 is formed on a conductive semiconductor substrate 11, for example, a p-type semiconductor substrate 11 by a conventional SOI forming method such as Separation by IMplanted OXygen (SIMOX). 12) form. In the semiconductor substrate 11 separated from the buried insulating layer 12, the upper portion of the buried insulating layer 12 becomes the active layer 13. A buffer oxide film 15 and a nitride film 17 are sequentially formed on the active layer 13, and the nitride film 17, the buffer oxide film 15, the active layer 13, and the buried insulating layer 12 are sequentially formed. Patterning is performed to expose a predetermined portion of the semiconductor substrate 11.
그런 다음, 도 1b와 같이 상기 노출된 반도체기판(11) 상에 상기 질화막(17)을 덮도록 비정질실리콘을 증착하고 상기 비정질실리콘에 상기 반도체기판(11)과 같은 보론(B)과 같은 p형의 불순물을 이온주입하고 어닐링하여 상기 비정질실리콘을 불순물이 도핑된 폴리실리콘층(polysilicon : 19)으로 형성한다.Next, as shown in FIG. 1B, amorphous silicon is deposited on the exposed semiconductor substrate 11 to cover the nitride film 17, and a p-type such as boron (B), such as the semiconductor substrate 11, is deposited on the amorphous silicon. The amorphous silicon is formed as a polysilicon layer (polysilicon 19) doped with impurities by ion implantation and annealing.
도 1c에 나타낸 바와 같이 상기 p형의 불순물이 도핑된 폴리실리콘층(19)을 오버 에치백(over etch-back)하여 상기 활성층(13) 및 매립절연층(12)의 측면에 상기 반도체기판(11)을 소정 깊이로 패터닝하면서 상기 활성층(13)과 반도체기판(11)을 연결하는 폴리 측벽(poly side-wall : 20)을 형성한다. 그리고, 상기 반도체기판(11) 상에 상기 질화막(17), 버퍼산화막(15), 활성층(13) 및 매립절연층(12)을 패터닝하여 생긴 홈을 채우도록 산화물을 증착하고 상기 질화막(17)이 드러날 때까지 상기 산화물을 화학기계연마(Chemical Mechanical Polishing : CMP)하여 필드산화막(21)을 형성한다.As illustrated in FIG. 1C, the semiconductor substrate may be formed on the side surfaces of the active layer 13 and the buried insulating layer 12 by over-etching back the polysilicon layer 19 doped with the p-type impurity. Patterning 11) to a predetermined depth to form a poly side wall (20) connecting the active layer 13 and the semiconductor substrate (11). An oxide is deposited on the semiconductor substrate 11 to fill a groove formed by patterning the nitride film 17, the buffer oxide film 15, the active layer 13, and the buried insulating layer 12. Until this is revealed, the oxide is chemical mechanical polished (CMP) to form a field oxide film 21.
그런 후에, 도 1d와 같이 상기 질화막(17)을 습식식각하여 제거하고, 상기 버퍼 산화막(15)을 제거하여 상기 활성층(13)을 노출시키고 상기 노출된 활성층(13)에 상기 반도체기판(11) 및 상기 폴리 측벽(20)과 같은 p형의 불순물을 이온주입하여 상기 활성층(13)을 p형으로 도핑한다.Thereafter, as shown in FIG. 1D, the nitride layer 17 is wet-etched and removed, the buffer oxide layer 15 is removed to expose the active layer 13, and the semiconductor substrate 11 is exposed to the exposed active layer 13. And implanting p-type impurities such as the poly sidewall 20 to dope the active layer 13 to p-type.
그리고, 도 1e에 나타낸 바와 같이 상기 p형으로 도핑된 활성층(13) 상의 소정 부분에 게이트산화막(22)을 개재시켜 게이트(23)를 형성하고, 상기 게이트(23)를 마스크로 사용하여 상기 p형의 활성층(13)에 상기 활성층(13)과 도전형이 다른 아세닉(As), 또는, 인(P)과 같은 n형의 불순물을 저농도로 이온주입하여 저도핑드레인(Lightly Doped Drain : 이하, LDD라 칭함) 구조를 형성하는 저농도 불순물영역(25)을 형성한다.As shown in FIG. 1E, a gate 23 is formed by interposing a gate oxide film 22 in a predetermined portion on the p-type doped active layer 13, and the gate 23 is used as a mask to form the gate 23. A lightly doped drain (hereinafter referred to as lightly doped drain) is formed by ion implantation of an active material 13 having a different conductivity type from the active layer 13 or an n-type impurity such as phosphorus (P) at a low concentration. A low concentration impurity region 25 forming a LDD) structure is formed.
그런 후에, 도 1f에 나타낸 바와 같이 상기 활성층(13) 상에 상기 게이트(23)를 덮도록 절연 물질을 증착한 후 에치백하여 상기 게이트(23)의 측면에 LDD 측벽(side wall : 27)을 형성하고 상기 게이트(23) 및 LDD 측벽(27)을 마스크로 사용하여 상기 활성층(13)에 아세닉(As), 또는, 인(P) 등과 같은 n형의 불순물을 고농도로 이온주입하여 소오스/드레인 영역(source/drain region)으로 사용되는 고농도 불순물영역(29)을 형성한다. 상기에서 고농도 불순물영역(29)을 형성할 때, 고농도의 이온주입을 하고 어닐링을하면 상기 매립절연층(12)이 형성된 부분까지 상기 고농도 불순물영역(29)이 형성된다.Then, as shown in FIG. 1F, an insulating material is deposited on the active layer 13 to cover the gate 23, and then etched back to form an LDD side wall 27 on the side of the gate 23. And n-type impurities such as acenic or phosphorous (P) are implanted into the active layer 13 at high concentration using the gate 23 and the LDD sidewall 27 as a mask. A high concentration impurity region 29 used as a drain region (source / drain region) is formed. When the high concentration impurity region 29 is formed, the high concentration impurity region 29 is formed up to a portion where the buried insulating layer 12 is formed by performing high concentration ion implantation and annealing.
상기와 같은 방법으로 형성된 반도체장치의 평면도를 살펴보면 도 2의 평면도와 같다.Looking at the plan view of the semiconductor device formed by the above method is the same as the plan view of FIG.
도 2에 나타낸 바와 같이, 반도체기판(도시되지 않음) 상에 매립절연층(도시되지 않음)이 있고 상기 매립절연층 상에 활성층을 한정하는 필드산화막(21)이 형성된다. 상기 활성층 및 필드산화막(21)을 가로지르는 게이트라인(23) 및 상기 게이트라인(23)의 양쪽 측면으로 LDD 측벽(27)이 형성되어 있다. 그리고, 상기 활성층에 상기 게이트라인(23)의 LDD 측벽(27) 양쪽으로 소오스/드레인 영역이 되는 불순물영역(29)이 형성되어 있고, 상기 활성층의 주위에 불순물이 도핑된 폴리 측벽(20)이 형성되어 상기 매립절연층으로 분리된 상기 활성층과 반도체기판을 연결하여 준다.As shown in FIG. 2, a buried insulating layer (not shown) is formed on a semiconductor substrate (not shown), and a field oxide film 21 defining an active layer is formed on the buried insulating layer. LDD sidewalls 27 are formed on both sides of the gate line 23 crossing the active layer and the field oxide layer 21 and the gate line 23. In addition, an impurity region 29 that becomes a source / drain region is formed in both sides of the LDD sidewall 27 of the gate line 23 in the active layer, and the poly sidewall 20 doped with impurities is formed around the active layer. The semiconductor substrate is formed by connecting the active layer separated by the buried insulating layer.
상기와 같은 방법으로 제조된 반도체장치의 동작시에 nMOS 활성층의 채널 아래에 발생하는 홀(Hole)들은 상기 불순물영역을 통과하지 못하고 상기 불순물영역이 형성되지 않은 채널 부분을 통해, 즉, 게이트의 길이 방향으로 이동하여 상기 p형으로 도핑된 폴리 측벽을 통해 상기 반도체기판으로 이동시켰다. 상술한 바와 같은 메카니즘으로 pMOS의 채널 아래 활성층에 축적되는 전자(Electron)들도 반도체기판으로 이동시켜 플로팅 바디 효과를 제어할 수 있다.Holes generated under the channel of the nMOS active layer during the operation of the semiconductor device fabricated as described above may not pass through the impurity region and pass through the channel portion where the impurity region is not formed, that is, the length of the gate. And moved to the semiconductor substrate through the p-type doped poly sidewall. As described above, the electrons accumulated in the active layer under the channel of the pMOS may also move to the semiconductor substrate to control the floating body effect.
그러나, 반도체장치의 집적화에 따라 상기 게이트의 폭이 좁아지는 경우에는 폴리 측벽의 저항이 커져서 발생한 홀, 또는, 전자를 신속히 제거하기 어렵게되고, 도핑된 복수 개의 폴리 측벽 사이에 기생 캐패시턴스가 발생하는 문제가 있다.However, when the width of the gate is narrowed due to the integration of semiconductor devices, it is difficult to quickly remove holes or electrons generated by the resistance of the poly sidewalls, and parasitic capacitance is generated between the plurality of doped poly sidewalls. There is.
따라서, 본 발명의 목적은 미세화된 SOI 소자에서 플로팅 바디 효과를 제어할 수 있는 반도체장치의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of controlling floating body effects in a refined SOI device.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조 방법은 제 1 도전형의 반도체기판 상에 매립절연층으로 인해 전기적으로 분리된 제 1 도전형의 활성층 상에 에피방지층을 형성하고 상기 에피방지층, 활성층 및 매립절연층을 패터닝하여 상기 반도체기판의 소정 부분을 노출시키는 바디 콘택홀을 형성하는 공정과, 상기 바디 콘택홀의 내부에 제 1 도전형을 에피시켜 바디층을 형성하는 공정과, 상기 에피방지층을 제거하고 상기 활성층의 소정부분에 필드산화막을 형성하는 공정과, 상기 바디층과 대응하는 부분 및 활성층 상의 소정 부분에 게이트산화막을 개제시킨 게이트를 형성하고 상기 게이트를 마스크로 사용하여 상기 제 1 도전형의 활성층에 제 2 도전형의 불순물영역을 형성하는 공정을 구비한다.A semiconductor device manufacturing method according to the present invention for achieving the above object is to form an epitaxial layer on the active layer of the first conductivity type electrically separated by a buried insulating layer on the semiconductor substrate of the first conductivity type and the epitaxial layer Forming a body contact hole exposing a predetermined portion of the semiconductor substrate by patterning an active layer and a buried insulating layer; forming a body layer by epitaxially forming a first conductive type in the body contact hole; Removing the protective layer and forming a field oxide film on a predetermined portion of the active layer; forming a gate having a gate oxide film interposed on a portion corresponding to the body layer and a predetermined portion on the active layer and using the gate as a mask; And forming a second conductive impurity region in the conductive active layer.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조 방법을 도시하는 단면 공정도.1A to 1F are cross sectional process views showing a method for manufacturing a semiconductor device according to the prior art.
도 2는 종래의 기술에 따라 제조 된 반도체장치의 평면도.2 is a plan view of a semiconductor device manufactured according to the prior art.
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 반도체장치의 제조 방법을 도시하는 공정도.3A to 3F are flowcharts illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 4는 본 발명의 실시예에 따라 제조 된 반도체장치의 평면도.4 is a plan view of a semiconductor device manufactured in accordance with an embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 간단한 설명〉<Brief description of symbols for the main parts of the drawings>
31 : 반도체기판 32 : 매립절연층31 semiconductor substrate 32 buried insulating layer
33 : 활성층 37 : 바디층33: active layer 37: body layer
41 : 필드산화막 43 : 게이트41: field oxide film 43: gate
47 : LDD 측벽 49 : 불순물영역47: LDD side wall 49: impurity region
이하, 첨부된 도면을 참조하여 본 발명을 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 반도체장치의 제조 방법을 도시하는 공정도이다.3A to 3F are process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 방법은 도 3a에 나타낸 바와 같이 도전형의 띤 반도체기판(31), 예를 들어, p형의 반도체기판(31) 상에 SIMOX 등과 같은 통상적인 SOI 형성 방법으로 매립절연층(32)을 형성한다. 상기에서 매립절연층(32)으로 분리된 반도체기판(31)에서 상기 매립절연층(32)의 상부가 활성층(33)이 된다. 그리고, 상기 활성층(33) 상에 산화물질, 또는, 질화물질 등을 사용하여 에피방지층(35)을 형성하고, 상기 에피방지층(35), 활성층(33) 및 매립절연층(32)을 패터닝하여 상기 반도체기판(31)의 소정 부분을 노출시키는 바디 콘택홀(body contact hole)을 형성한다.3A, the buried insulating layer 32 is formed by a conventional SOI formation method such as SIMOX on the conductive type semiconductor substrate 31, for example, the p-type semiconductor substrate 31, as shown in FIG. do. In the semiconductor substrate 31 separated from the buried insulating layer 32, the upper portion of the buried insulating layer 32 becomes the active layer 33. The epitaxial layer 35 is formed on the active layer 33 using an oxide material or a nitride material, and the epitaxial layer 35, the active layer 33, and the buried insulating layer 32 are patterned. A body contact hole exposing a predetermined portion of the semiconductor substrate 31 is formed.
그런 후에, 도 3b와 같이 상기 노출된 반도체기판(31) 상에 선택적 에피택셜 성장(Selective Epitaxial Growth) 방법으로 실리콘을 증착하여 상기 바디 콘택홀을 채우는 바디층(37)을 형성하고, 상기 바디층(37)에 상기 반도체기판(31)과 같은 도전형을 도핑하기 위해 보론(B)과 같은 p형의 불순물을 이온주입하여 상기 바디층(37) 및 상기 활성층(33)을 도핑한다. 상기에서 선택적 에피택셜 성장시에 노출된 반도체기판(31) 부분을 제외한 부분에는 에피방지층(35)이 형성되어 상기 바디 콘택홀의 내부에만 실리콘이 성장하여 상기 바디 콘택홀의 내부에 바디층(37)을 형성한다.Thereafter, as illustrated in FIG. 3B, silicon is deposited on the exposed semiconductor substrate 31 by a selective epitaxial growth method to form a body layer 37 filling the body contact hole, and the body layer P-type impurities such as boron (B) are ion-implanted to dope the conductive type such as the semiconductor substrate 31 in the 37 to dope the body layer 37 and the active layer 33. An epitaxial layer 35 is formed on a portion of the body contact hole except for the portion of the semiconductor substrate 31 that is exposed during selective epitaxial growth. Thus, the body layer 37 is formed inside the body contact hole. Form.
그리고, 도 3c에 나타낸 바와 같이 상기 p형으로 도핑하기 위한 이온주입으로 손상된 바디층(37)의 표면을 열산화시켜 산화층(도시하지 않음)을 형성한 후 상기 활성층(33) 상의 에피방지층(35)과 함께 제거하고, 다시 상기 활성층(33) 및 상기 바디층(37)을 산화시켜 버퍼산화막(38)을 형성하고 상기 버퍼산화막(38) 상에 질화막(39)을 CVD 방법으로 형성한다. 그런 후에, 상기 질화막(39), 버퍼산화막(38) 및 활성층(33)을 포토리쏘그래피(Photolithograpy) 방법으로 패터닝하여 상기 매립절연층(32)의 소정 부분을 노출시켜 활성층(33)을 한정한다.As shown in FIG. 3C, the surface of the body layer 37 damaged by ion implantation for the p-type doping is thermally oxidized to form an oxide layer (not shown), and then the epitaxial layer 35 on the active layer 33 is formed. ), And then the active layer 33 and the body layer 37 are oxidized to form a buffer oxide film 38 and a nitride film 39 is formed on the buffer oxide film 38 by a CVD method. Thereafter, the nitride layer 39, the buffer oxide layer 38, and the active layer 33 are patterned by a photolithography method to expose a predetermined portion of the buried insulating layer 32 to define the active layer 33. .
그런 다음에 도 3d와 같이 상기 질화막(39), 버퍼산화막(38) 및 활성층(33)의 패터닝으로 소정 부분 노출된 상기 매립절연층(32) 상에 상기 질화막(39)을 덮도록 산화물질을 증착하고, 상기 산화물질을 CMP방법으로 에치백하여 상기 질화막(39)을 노출시키는 필드산화막(41)을 형성한다.Then, as shown in FIG. 3D, an oxide material is formed to cover the nitride film 39 on the buried insulating layer 32 partially exposed by patterning the nitride film 39, the buffer oxide film 38, and the active layer 33. After the deposition, the oxide is etched back by a CMP method to form a field oxide film 41 exposing the nitride film 39.
그리고, 도 3e에 나타낸 바와 같이 상기 질화막(39)을 습식식각하여 제거하고 상기 버퍼산화막(38)을 제거하여 상기 활성층(33) 및 바디층(37)을 노출시킨다. 그리고, 상기 바디층(37)과 대응하는 부분 및 활성층(33) 상의 소정 부분에 게이트산화막(42)을 개재시킨 게이트(43)를 형성하고 상기 게이트(43)를 마스크로 사용하여 상기 p도핑된 활성층(33)에 상기 활성층(33)과 도전형이 다른 아세닉(As), 또는, 인(P) 등을 저농도로 이온주입하여 LDD 구조를 형성하기 위한 n형의 저농도 불순물영역(45)을 형성한다.As shown in FIG. 3E, the nitride layer 39 is wet-etched and removed, and the buffer oxide layer 38 is removed to expose the active layer 33 and the body layer 37. In addition, a gate 43 having a gate oxide layer 42 interposed therebetween is formed in a portion corresponding to the body layer 37 and an active layer 33, and the p-doped layer is formed using the gate 43 as a mask. An n-type low concentration impurity region 45 is formed in the active layer 33 to form an LDD structure by ion implantation of an ascetic (As) having a different conductivity type from the active layer 33 or phosphorus (P) or the like at low concentration. Form.
그런 후에, 도 3f에 나타낸 바와 같이 상기 활성층(33) 상에 상기 게이트(43)를 덮도록 절연 물질을 증착한 후 에치백하여 상기 게이트(43)의 측면에 LDD 측벽(47)을 형성하고 상기 게이트(43) 및 LDD 측벽(47)을 마스크로 사용하여 상기 p형의 활성층(33)에 아세닉(As), 또는, 인(P) 등과 같은 n형의 불순물을 고농도로 이온주입하여 소오스/드레인 영역으로 사용되는 고농도 불순물영역(49)을 형성한다. 상기에서 고농도 불순물영역(49)을 형성할 때, 고농도의 이온주입을 하고 어닐링을하면 상기 매립절연층(32)이 형성된 부분까지 상기 고농도 불순물영역(49)이 형성된다.Thereafter, as shown in FIG. 3F, an insulating material is deposited on the active layer 33 to cover the gate 43, and then etched back to form an LDD sidewall 47 on the side of the gate 43. Using the gate 43 and the LDD sidewalls 47 as a mask, ion implantation of high concentrations of n-type impurities such as acenic or phosphorous (P) into the p-type active layer 33 results in source / A high concentration impurity region 49 used as the drain region is formed. When the high concentration impurity region 49 is formed, the high concentration impurity region 49 is formed up to a portion where the buried insulating layer 32 is formed by performing ion implantation and annealing at a high concentration.
상기와 같은 방법으로 형성된 반도체장치의 평면도를 살펴보면 도 4의 평면도와 같다.Looking at the top view of the semiconductor device formed by the above method is the same as the top view of FIG.
도 4에 나타낸 바와 같이, 반도체기판(도시되지 않음)에 매립절연층(도시되지 않음으로 활성층(도시되지 않음)이 분리되어 있고 상기 매립절연층 상에 활성층을 한정하는 필드산화막(41)이 형성된다. 그리고, 상기 필드산화막(41)으로 한정된 활성층의 내부에는 반도체기판과 도전형이 같은 바디층(37)이 형성되어 있고 상기 바디층(37)과 대응하는 부분 및 필드산화막을 가로지르는 부분에 게이트라인(43) 및 상기 게이트라인(43)의 양쪽 측면으로 LDD 측벽(47)이 형성된다. 상기 활성층에는 상기 게이트라인(43)의 LDD 측벽(47) 양쪽으로 소오스/드레인 영역으로 사용되는 불순물영역(49)이 형성되어 있다. 상기에서 바디층(37)은 상기 활성층과 반도체기판을 연결하도록 형성되고, 상기 바디층(37)을 활성층에 다수 개의 바디 콘택을 형성하여 반도체기판과 상기 활성층을 연결하는 방법도 있다.As shown in FIG. 4, a buried insulating layer (not shown) is formed on a semiconductor substrate (not shown), and a field oxide film 41 is formed on the buried insulating layer to define an active layer. In the active layer defined by the field oxide film 41, a body layer 37 having the same conductivity type as that of the semiconductor substrate is formed, and a portion corresponding to the body layer 37 and a portion crossing the field oxide film are formed. LDD sidewalls 47 are formed on both sides of the gate line 43 and the gate line 43. Impurities used as source / drain regions on both sides of the LDD sidewall 47 of the gate line 43 are formed in the active layer. A region 49 is formed, wherein the body layer 37 is formed to connect the active layer and the semiconductor substrate, and the body layer 37 forms a plurality of body contacts in the active layer to form the semiconductor substrate and the bow. There is also a method for connecting layers.
상술한 바와 같이 본 발명에 의해 제조된 반도체소자의 동작을 살펴보면 nMOS의 채널 아래 발생한 홀(Hole)들이 상기 바디층을 통해 p형의 반도체기판으로 이동하도록 형성되어있다. pMOS의 채널 아래에 축적되는 전자(Electron)들도 상술한바와 같은 메카니즘으로 상기 게이트산화막 하부에 형성된 상기 활성층과 반도체기판을 연결하는 바디층을 통해 반도체기판으로 이동시켜 제거할 수 있다.Referring to the operation of the semiconductor device manufactured by the present invention as described above, holes generated under the channel of the nMOS are formed to move to the p-type semiconductor substrate through the body layer. Electrons accumulated under the channel of the pMOS may also be removed by moving to the semiconductor substrate through the body layer connecting the active layer and the semiconductor substrate formed under the gate oxide layer using the same mechanism as described above.
따라서, 본 발명에 따른 SOI 구조를 갖는 반도체장치는 게이트의 하부에 임의의 면적을 갖는 바디층을 형성하여 미세화된 반도체장치의 플로팅 바디 효과의 제어가 가능하고, 도핑된 측벽을 사용하지 않으므로 기생 캐패시턴스의 발생을 방지할 수 있는 이점이 있다.Accordingly, in the semiconductor device having the SOI structure according to the present invention, a body layer having an arbitrary area can be formed under the gate to control the floating body effect of the semiconductor device, and the parasitic capacitance is not used because doped sidewalls are not used. There is an advantage that can prevent the occurrence of.
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| KR100372645B1 (en) * | 2000-06-30 | 2003-02-17 | 주식회사 하이닉스반도체 | Method for manufacturing soi device |
| KR100876830B1 (en) * | 2002-07-18 | 2009-01-07 | 주식회사 하이닉스반도체 | A method for forming a semiconductor device |
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