KR100958631B1 - Method for manufacturing ?????? - Google Patents
Method for manufacturing ?????? Download PDFInfo
- Publication number
- KR100958631B1 KR100958631B1 KR1020070141483A KR20070141483A KR100958631B1 KR 100958631 B1 KR100958631 B1 KR 100958631B1 KR 1020070141483 A KR1020070141483 A KR 1020070141483A KR 20070141483 A KR20070141483 A KR 20070141483A KR 100958631 B1 KR100958631 B1 KR 100958631B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- oxide layer
- isolation
- gate
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 238000009279 wet oxidation reaction Methods 0.000 claims abstract description 4
- 230000003213 activating effect Effects 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명에 따른 MOSFET 제조 방법의 일 예는, 웰이 형성된 반도체 기판의 소정 영역에 소정 크기로 슬릿 트렌치 아이솔레이션을 형성한 후, 상기 형성된 슬릿 트렌치 산화막과 반도체 기판상에 습식 산화공정을 수행하여 아이솔레이션 산화막을 형성하고, 상기 슬릿 트렌치 아이솔레이션과 아이솔레이션 산화막은 T-형 구조로 형성하는 단계와, 상기 형성된 아이솔레이션 산화막 하부에 이온을 주입하여 소스-드레인을 형성하고, 상기 주입한 이온을 활성화한 후 식각하여 상기 형성된 아이솔레이션 산화막 일부를 제거하는 단계와, 상기 일부 제거된 아이솔레이션 산화막 상부에 채널 형성을 위한 에피층을 형성하고, 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 형성 후, 폴리 게이트를 형성하고 이온을 주입하여 쉘로우 정션을 형성하는 단계 및 상기 쉘로우 정션 형성 후 상기 형성된 폴리 게이트에 스페이서 구조를 형성하고, 상기 소스-드레인이 형성된 상기 반도체 기판에 실리사이드 층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다. 따라서, 본 발명에 따르면, 65 nm 이하 MOSFET의 집적도를 향상시키고, 고 집적회로에서도 성능을 개선할 수 있으며, 폴리 게이트의 높이를 감소시켜 MOSFET의 채널 및 익스텐션 수행을 용이하게 할 수 있다.An example of the MOSFET fabrication method according to the present invention is to form a slit trench isolation in a predetermined region of a semiconductor substrate in which a well is formed, and then perform a wet oxidation process on the formed slit trench oxide film and the semiconductor substrate to form an isolation oxide film. And forming the slit trench isolation and isolation oxide layer in a T-type structure, implanting ions into the formed isolation oxide layer to form a source-drain, activating the implanted ions, and etching the ions. Removing a portion of the formed isolation oxide, forming an epitaxial layer for forming a channel on the partially removed isolation oxide layer, forming a gate oxide layer, and forming a poly gate after implanting the gate oxide layer, and implanting ions Forming a shallow junction It characterized in that comprises a step of forming a silicide layer on the semiconductor substrate, a drain formed - after the shallow junction to form the source, to form the spacer structure formed on the gate poly. Therefore, according to the present invention, it is possible to improve the integration of the MOSFET of 65 nm or less, improve the performance even in a high integrated circuit, and reduce the height of the poly gate to facilitate the channel and extension of the MOSFET.
반도체, MOSFET, 슬릿 트렌치 아이솔레이션, 아이솔레이션 산화막, 스페이서 Semiconductors, MOSFETs, Slit Trench Isolation, Isolation Oxides, Spacers
Description
본 발명은 MOSFET에 관한 것으로, 특히 T-형 아이솔레이션 산화막 구조를 이용하여 소스-드레인 구조를 형성하는 MOSFET 제조 방법에 관한 것이다.The present invention relates to a MOSFET, and more particularly, to a MOSFET manufacturing method for forming a source-drain structure using a T-type isolation oxide structure.
종래 실리콘(Si) MOSFET을 사용하는 제품의 집적도가 증가함에 따라 디자인 규칙(design rule)의 감소가 급격히 진행됐다.As the degree of integration of products using silicon (Si) MOSFETs increases, the design rule decreases rapidly.
이에 따라 MOSFET 구조의 개선으로 집적도 및 성능 개선이 요구되어 진다.As a result, the improvement of the structure of the MOSFET is required to improve the integration and performance.
그러나 종래 기술에 따른 65nm 이하 MOSFET의 디자인 규칙에서는 스페이서(spacer) 구조로 인해 집적도에 문제가 있었다.However, in the design rules of the MOSFET of 65 nm or less according to the prior art, there is a problem in integration due to the spacer structure.
또한, 종래에는 MOSFET의 성능(performance)을 개선하기 위해 SOI 구조와 유사한 채널(channel) 구조가 요구되었으나, 상기 SOI 구조는 기판 열 방출 문제가 있었다.In addition, although a channel structure similar to the SOI structure is required in order to improve the performance of the MOSFET, the SOI structure has a problem of substrate heat dissipation.
이와 함께 종래에는 MOSFET의 폴리 게이트(poly gate) 높이에 대한 공정 마진(margin)이 작아 디바이스(device) 공정 적용에 문제가 있었다.In addition, in the related art, a process margin with respect to a poly gate height of a MOSFET is small, and thus there is a problem in applying a device process.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 본 발명에서는 T-형 아이솔레이션 산화막(isolation oxide)를 이용하여 소스-드레인(source-drain) 구조를 형성시키는 것을 목적으로 한다.The present invention is to solve the above problems, it is an object of the present invention to form a source-drain structure using a T-type isolation oxide (isolation oxide).
상기와 같은 목적을 달성하기 위한 본 발명에 따른 MOSFET 제조 방법의 일 예는, 웰이 형성된 반도체 기판의 소정 영역에 소정 크기로 슬릿 트렌치 아이솔레이션을 형성한 후, 상기 형성된 슬릿 트렌치 산화막과 반도체 기판상에 습식 산화공정을 수행하여 아이솔레이션 산화막을 형성하고, 상기 슬릿 트렌치 아이솔레이션과 아이솔레이션 산화막은 T-형 구조로 형성하는 단계와, 상기 형성된 아이솔레이션 산화막 하부에 이온을 주입하여 소스-드레인을 형성하고, 상기 주입한 이온을 활성화한 후 식각하여 상기 형성된 아이솔레이션 산화막 일부를 제거하는 단계와, 상기 일부 제거된 아이솔레이션 산화막 상부에 채널 형성을 위한 에피층을 형성하고, 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 형성 후, 폴리 게이트를 형성하고 이온을 주입하여 쉘로우 정션을 형성하는 단계 및 상기 쉘로우 정션 형성 후 상기 형성된 폴리 게이트에 스페이서 구조를 형성하고, 상기 소스-드레인이 형성된 상기 반도체 기판에 실리사이드 층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.An example of a method for fabricating a MOSFET according to the present invention for achieving the above object is to form a slit trench isolation in a predetermined size in a predetermined region of a semiconductor substrate on which a well is formed, and then, on the formed slit trench oxide film and the semiconductor substrate. Performing a wet oxidation process to form an isolation oxide layer, and forming the slit trench isolation and isolation oxide layer in a T-type structure, implanting ions into the formed isolation oxide layer to form a source-drain, and implanting the implanted oxide layer. Activating and then etching ions to remove a portion of the formed isolation oxide layer, forming an epitaxial layer for channel formation on the partially removed isolation oxide layer, forming a gate oxide layer, and forming the gate oxide layer, Form poly gates and implant ions W to form a shallow junction and after the shallow junction formation to form a spacer structure formed on the poly gate and the source - is characterized in that comprises a step of forming a silicide layer on the semiconductor substrate, a drain formed.
삭제delete
삭제delete
삭제delete
상술한 본 발명에 따른 MOSFET 제조 방법에 의하면, According to the MOSFET manufacturing method according to the present invention described above,
첫째, 65 nm 이하 MOSFET의 집적도를 향상시킬 수 있는 효과가 있다.First, there is an effect to improve the integration of the MOSFET below 65 nm.
둘째, 고 집적회로에서도 성능(performance)을 개선할 수 있는 효과가 있다.Second, there is an effect that can improve the performance (high) even in a high integrated circuit.
셋째, 폴리 게이트의 높이를 감소시켜 MOSFET의 채널 및 익스텐션 수행을 용이하게 할 수 있는 효과가 있다.Third, there is an effect that can reduce the height of the poly gate to facilitate the channel and extension of the MOSFET.
이하 상기와 같은 목적을 달성하기 위한 본 발명의 구체적인 실시 예를 첨부된 도면을 참조하여 상세하게 설명하면, 다음과 같다.Hereinafter, specific embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
본 발명은 MOSFET에 관한 것으로, 특히 T-형 아이솔레이션 산화막(isolation oxide)를 이용하여 소스-드레인(source-drain) 구조를 형성시키는 것을 특징으로 한다.The present invention relates to a MOSFET, and in particular, to form a source-drain structure using a T-type isolation oxide.
도 1a 내지 1i는 본 발명에 따른 MOSFET 제조 공정의 일 예를 순차적 도시한 것이다.1A to 1I sequentially illustrate an example of a MOSFET manufacturing process according to the present invention.
이하 본 발명에 따른 MOSFET 제조 공정을 설명함에 있어, 첨부된 도면과 함 께 순차적으로 그 제조 공정을 설명하면, 다음과 같다.Hereinafter, in describing the MOSFET manufacturing process according to the present invention, the manufacturing process will be described sequentially with the accompanying drawings.
먼저 도 1a에서, 반도체 기판(1) 상에 웰 이식(well implant) 공정을 수행하여, 웰(well)을 형성한다.First, in FIG. 1A, a well implant process is performed on the
상기 웰을 형성한 후, 상기 반도체 기판(1)의 소정 영역에 소정 크기로 슬릿 트렌치 아이솔레이션(slit trench isolation)(2)을 형성한다.After the well is formed, a slit trench isolation 2 is formed in a predetermined region of the
도 1b에서, 상기 슬릿 트렌치 아이솔레이션(2)을 형성한 후, 상기 형성된 슬릿 트렌치 산화막(2)과 반도체 기판(1) 상에 습식 산화 공정을 수행하여 아이솔레이션 산화막(isolation oxide)(3)를 형성한다.In FIG. 1B, after forming the slit trench isolation 2, a wet oxidation process is performed on the formed slit trench oxide layer 2 and the
또한, 상기 형성되는 슬릿 트렌치 아이솔레이션(2)과 아이솔레이션 산화막(3)은 T-형 구조를 가진다.In addition, the slit trench isolation 2 and the
도 1c에서, 상기 T-형 구조 하부에 이온을 주입하여 소스-드레인(4)을 형성한다. 그리고 상기 이온 주입 후 RTP를 사용하여 상기 주입한 이온을 활성화시킨다.In FIG. 1C, ions are implanted under the T-type structure to form the source-
도 1d에서, 상기 이온 주입 후 포토 리쏘그래피(photo lithography) 및 식각. 공정으로 상기 형성한 아이솔레이션 산화막(3)의 일부를 제거한다.1D, photo lithography and etching after the ion implantation. A part of the formed
도 1e에서, 상기 일부 제거된 아이솔레이션 산화막(3a) 상부에 채널 형성을 위ㅎ하여 에피-실리콘(epi-Si)층(5)을 형성한다.In FIG. 1E, an epi-
도 1f에서, 게이트 산화(gate oxidation) 공정을 적용하여 게이트 산화막(gate oxide)(6)을 형성한다.In FIG. 1F, a gate oxidation process is applied to form a
상기 게이트 산화막(6) 형성 후, 폴리 게이트(7)를 형성시키기 위하여 CVD 폴리 실리콘(poly silicon) 막을 도포한다.After the
그리고 상기 도포된 폴리 실리콘 막을 이용하여 폴리 게이트(7)을 형성한다.Then, the poly gate 7 is formed using the coated polysilicon film.
도 1g에서, 상기 폴리 게이트(7) 형성 후, LDD 영역에 이온을 주입하여 쉘로우 정션(shallow junction)(8)을 형성한다.In FIG. 1G, after the poly gate 7 is formed, ions are implanted into the LDD region to form a
도 1h에서 실리사이드(silicide) 공정을 위하여 TEOS 및 실리콘 질화(SiN) 막을 사용하여 상기 폴리 게이트(7)에 스페이서(spacer)(9) 구조를 형성한다.In FIG. 1H, a
도 1i에서, 상기 스페이서(9) 구조를 형성한 후, 실리사이드 층(10)을 형성한다. 이때, 상기 형성되는 실리사이드층(10)은 상기 형성한 소스-드레인(4a)까지 도달 되도록 충분한 두께의 금속층을 사용할 수 있다. 이때, 상기 금속층은 코발트(Co)나 또는 니켈(Ni)이 사용될 수 있다.In FIG. 1I, after forming the
따라서, 상술한 본 발명에 따르면, 65 nm 이하 MOSFET의 집적도를 향상시킬 수 있으며, 고 집적회로에서도 성능(performance)을 개선할 수 있게 된다.Therefore, according to the present invention described above, the integration degree of the MOSFET of 65 nm or less can be improved, and the performance can be improved even in a high integrated circuit.
또한, 상술한 바와 같이, 폴리 게이트(7)의 높이를 종래 기술에 따른 공정보다 감소시킴으로써, MOSFET의 채널(channel) 및 익스텐션(extension) 수행이 용이해진다.In addition, as described above, by reducing the height of the poly gate 7 compared to the process according to the prior art, it is easy to perform the channel (channel) and extension of the MOSFET.
이상 상술한 본 발명에 따른 기술 사상은, 상술한 실시 예에 한정되는 것은 아니며, 슬릿 트렌치 아이솔레이션과 아이솔레이션 산화막 층을 이용하여 구성한 T-형 구조가 반도체 내부에 삽입되는 경우에 모두 적용 가능하다.The technical idea according to the present invention described above is not limited to the above-described embodiment, and is applicable to both the case where the T-type structure formed by using the slit trench isolation and the isolation oxide layer is inserted into the semiconductor.
또한, 익스텐션 하부에 소스-드레인을 형성시켜 제작되는 모든 MOSFET에 응용 가능하며, 반도체 기판에 형성된 아이솔레이션 산화막 하부에 소스-드레인을 형 성시키는 모든 MOSFET에 적용 가능하다.In addition, it is applicable to all MOSFETs fabricated by forming source-drain under the extension, and applicable to all MOSFETs forming source-drain under the isolation oxide formed on the semiconductor substrate.
이상에서는 본 발명의 기술 사상을 설명함에 있어서, 특정 실시 예를 첨부된 도면과 함께 도시하고 설명하였다. 다만, 본 발명은 상술한 실시 예에 한정되는 것은 아니며, 본 발명의 기술 사상을 벗어나지 않는 범위 즉, 당해 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 다양한 수정 및 변경을 가능하다.In the above description of the technical idea of the present invention, specific embodiments have been shown and described with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and various modifications and changes may be made by those skilled in the art without departing from the spirit of the present invention, that is, the technical field to which the present invention belongs.
도 1a 내지 1i는 본 발명에 따른 MOSFET 제조 공정의 일 예를 순차적 도시한 것1A to 1I sequentially illustrate an example of a MOSFET manufacturing process according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1; 반도체 기판 2; 슬릿 트렌치 아이솔레이션One; Semiconductor substrate 2; Slit Trench Isolation
3,3a; 아이솔레이션 산화막 4,4a; 소스-드레인3,3a;
5; 에피-실리콘층 6; 게이트 산화막5; Epi-
7; 폴리 게이트 8; 쉘로우 정션7; Poly gate 8; Shallow Junction
9; 스페이서 10; 실리사이드 층9;
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070141483A KR100958631B1 (en) | 2007-12-31 | 2007-12-31 | Method for manufacturing ?????? |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070141483A KR100958631B1 (en) | 2007-12-31 | 2007-12-31 | Method for manufacturing ?????? |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20090073517A KR20090073517A (en) | 2009-07-03 |
| KR100958631B1 true KR100958631B1 (en) | 2010-05-19 |
Family
ID=41330661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020070141483A KR100958631B1 (en) | 2007-12-31 | 2007-12-31 | Method for manufacturing ?????? |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100958631B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990075417A (en) * | 1998-03-20 | 1999-10-15 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR100620642B1 (en) * | 2005-06-30 | 2006-09-06 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
-
2007
- 2007-12-31 KR KR1020070141483A patent/KR100958631B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990075417A (en) * | 1998-03-20 | 1999-10-15 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR100620642B1 (en) * | 2005-06-30 | 2006-09-06 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090073517A (en) | 2009-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8329566B2 (en) | Method of manufacturing a high-performance semiconductor device | |
| US8193586B2 (en) | Sealing structure for high-K metal gate | |
| US20060151808A1 (en) | MOSFET device with localized stressor | |
| KR970054397A (en) | MOS field effect transistor manufacturing method | |
| JP2006278974A (en) | Semiconductor device and manufacturing method thereof | |
| CN107452627B (en) | Method for manufacturing semiconductor device | |
| US20090294807A1 (en) | Methods of Fabricating Transistors and Structures Thereof | |
| US20090011561A1 (en) | Method of fabricating high-voltage mos having doubled-diffused drain | |
| KR20020003028A (en) | Method for making an soi metal oxide fet | |
| US20140167110A1 (en) | Partial poly amorphization for channeling prevention | |
| KR100588035B1 (en) | Method of enhanced oxidation of mos transistor gate corners | |
| US8202782B2 (en) | Method of manufacturing transistor | |
| KR100707590B1 (en) | Multiple LDD-Type MOS Transistor and Manufacturing Method Thereof | |
| KR20090037055A (en) | Method for manufacturing of semiconductor device | |
| KR100799111B1 (en) | Transistor in semiconductor device and method for manufacturing the same | |
| US7217625B2 (en) | Method of fabricating a semiconductor device having a shallow source/drain region | |
| CN102915971B (en) | Manufacturing method of semiconductor device | |
| KR100958631B1 (en) | Method for manufacturing ?????? | |
| US7915128B2 (en) | High voltage semiconductor devices | |
| US7400013B1 (en) | High-voltage transistor having a U-shaped gate and method for forming same | |
| CN107437533B (en) | Semiconductor structure and manufacturing method thereof | |
| KR100562309B1 (en) | Transistor having reverse spacer and fabrication method thereof | |
| US8557668B2 (en) | Method for forming N-shaped bottom stress liner | |
| KR101004807B1 (en) | High voltage transistor provided with bended channel for increasing channel punch immunity and method for manufacturing the same | |
| KR20060005556A (en) | Method for manufacturing an integrated semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |