KR100876830B1 - A method for forming a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, a bottom gate is formed below a channel when fabricating a silicon on insulator (SOI) substrate, thereby controlling a difference in work function between the bottom gate and the channel or an external power supply. It eliminates the floating body effect and kink effect caused by the body not being grounded in the partially depleted device of the device.The silicon layer of the source / drain junction region can be formed thicker than the channel side. This technology improves the characteristics and reliability of semiconductor devices by reducing spikes and parasitic series resistance when forming contacts. Technology.

Description

A method for forming a semiconductor device

1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the prior art.

2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a second embodiment of the prior art.

3A to 3L are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

11,41,71: silicon substrate 13,43: buried oxide film

15: upper silicon layer 17: pad oxide film

19,47,77,83: nitride film 21,29: nitride film spacer

23: LOCOS 25: Gate region

27,79 trench 31 Source / drain regions

45: conductive layer for floor gate, floor gate

49: gate oxide film of bottom gate 51: upper silicon layer

53: gate oxide film of upper gate 55: upper gate

57,93: low concentration impurity junction region 59,95: insulating film spacer                 

61,97: high concentration impurity junction region 73: undoped polysilicon film

75: doped polysilicon film 81: device isolation film

85 bottom gate oxide 87 selective epitaxial oxide

89: pad oxide film 90: gate oxide film

91: upper gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, a bottom gate is formed under a channel when fabricating a silicon on insulator (SOI) substrate, thereby controlling a difference in work function or external power supply between the bottom gate and the channel, and thereby controlling the SOI device It eliminates the floating body effect and kink effect caused by the body not being grounded in the partially depleted device of the device.The silicon layer of the source / drain junction region can be formed thicker than the channel side. A technique for forming an SOI device that reduces spikes and parasitic series resistance in contact formation of / drains.

In recent years, as semiconductor devices become more integrated, the process is simplified, the capacitive coupling between the circuit elements of the overall IC chip and the latchup of the CMOS circuit is reduced, and the packing density is increased to increase the driving speed of the circuit. As a result, SOI devices are formed that reduce parasitic capacitance and reduce chip size.

In addition, the SOI device may easily perform a device separation process having improved characteristics.

1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the prior art.

Referring to FIG. 1A, a buried oxide film 13 and an upper silicon layer 15 are stacked on the silicon substrate 11.

The pad oxide layer 17 and the nitride layer 19 are stacked on the upper silicon layer 15.

Referring to FIG. 1B, the nitride layer 19 and the pad oxide layer 17 are etched to expose the upper silicon layer 15 by a photolithography process using an exposure mask that exposes a central portion of the active region of the silicon substrate 11. Let's do it.

Next, an insulating film spacer 21 is formed on sidewalls of the nitride film 19 and the pad oxide film 17.

In this case, the insulating film spacer 21 is formed of a nitride film.

Referring to FIG. 1C, the exposed upper silicon layer 15 is thermally oxidized to form a field oxide layer 23 having a LOCal oxide of silicon (LOCOS) type.

Referring to FIG. 1D, the trench oxide region 25 is formed by etching the field oxide layer 23 using the nitride layer 19 and the insulating layer spacer 21 as a mask.

At this time, the gate electrode 25 has a field oxide film 23 having a predetermined thickness at the bottom thereof.

The impurity for adjusting the threshold voltage is implanted into the bottom of the gate region 25 using the nitride film 19 and the insulating film spacer 21 as a mask.                         

Referring to FIG. 1E, a thermal oxide film (not shown) is formed over the entire surface, and a gate 27 filling the gate region 25 is formed.

Referring to FIG. 1F, the insulating film spacer 21 and the nitride film 19 are removed, and the insulating film spacer 29 is formed on sidewalls of the gate 27 and the field oxide film 23, and then the insulating film spacer 29 and A source / drain impurity is implanted into the upper silicon layer 15 using the gate 27 as a mask to form a source / drain junction region 31.

2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a second embodiment of the prior art.

Referring to FIG. 2A, a buried oxide film 43, a bottom gate conductive layer 45, and a nitride film 47 are deposited to a predetermined thickness on the silicon substrate 41.

Referring to FIG. 2B, the nitride layer 47 and the bottom gate conductive layer 45 are etched by a photolithography process using a gate electrode mask (not shown).

Referring to FIG. 2C, the nitride film 47 is removed to form a bottom gate formed of a conductive layer (not shown) for the bottom gate.

Then, an oxide film 48 for applying the bottom gate is deposited.

Referring to FIG. 2D, the oxide layer 48 is planarized and etched to expose the bottom gate 45.

In this case, the planarization etching process may be performed by using an etching selectivity difference between the bottom gate 45 and the oxide layer 48.

Referring to FIG. 2E, a gate oxide film 49 of the bottom gate 45 is formed on the entire surface.

Referring to FIG. 2F, an upper silicon layer 51 is formed on the gate oxide layer 49, and a gate oxide layer 53 is formed on the gate oxide layer 49.

A gate 55 is formed on the gate oxide layer 53, and a low concentration impurity junction region 57 is formed in the upper silicon layer 51 using the gate 55 as a mask.

Next, an insulating film spacer 59 is formed on the sidewall of the gate 55 and a high concentration of impurities are implanted into the upper silicon layer 51 by using the insulating film spacer 59 and the gate 55 as a mask. The impurity junction region 61 is formed to form a source / drain region having an LDD structure.

The first embodiment of the related art has a problem in that a junction spiking phenomenon may be caused when a contact of a source / drain junction is formed. In the second embodiment, the characteristics of parasitic series resistance reduction of the source / drain region are deteriorated. There is a problem.

In order to solve the problems of the related art, the bottom gate is formed during fabrication of the substrate to remove the floating body effect and to secure the silicon film of the source / drain junction region, and the device isolation region is formed using the bottom gate as a mask. After etching, after forming the device isolation layer, the height of the device isolation layer is adjusted to be lower than that of the bottom gate. Then, the upper silicon layer is grown by using the selective epitaxial growth method and the upper silicon layer is planarized again. To form a fully depleted SOI device where all channel regions are depleted to less than Å, to fabricate a double gate device with a bottom gate, and to keep the silicon film at least twice as thick as the source / drain regions. To optimize parasitic series resistance by The purpose of the present invention is to provide a method of forming a semiconductor device.

In order to achieve the above object, a method of forming a semiconductor device according to the present invention,

Forming a trench by laminating an undoped polysilicon film, a doped polysilicon film, and a nitride film on a semiconductor substrate, and etching the semiconductor substrate having a predetermined thickness and the stacked structure by a photolithography process using a gate electrode mask;

Forming a device isolation film over the entire surface including the trench and planarizing etching to expose the nitride film;

Etching the device isolation film to a predetermined thickness using the nitride film as a mask, removing the nitride film to form a bottom gate, and then forming insulating film spacers on sidewalls;

Forming a bottom gate oxide film over the entire surface and forming a selective epitaxially grown polysilicon film to planarize the entire surface;

Ion implanting a threshold voltage impurity into the selective epitaxially grown polysilicon film;

Forming an upper gate oxide film and an upper gate on the selective epitaxially grown polysilicon film and ion implanting impurities of low concentration into the selective epitaxially grown polysilicon film;

Forming an insulating film spacer on the sidewall of the upper gate, and implanting a high concentration of impurities into the selective epitaxially grown polysilicon film to form a source / drain region of an LDD structure;

The undoped polysilicon film is used as a gate insulating film of the bottom gate, the gate insulating film may be formed of a nitride film,

The undoped polysilicon film is formed to a thickness of 300 to 500 mm 3,

The doped polysilicon film is formed to a thickness of 500 to 1000 GPa, the nitride film is formed to a thickness of 1500 to 10000 GPa,

Forming the trench at a depth of 3000 to 3500 mm from the surface of the semiconductor substrate;

The device isolation film is formed to a thickness of 4500 ~ 15000 ,,

The predetermined thickness of the isolation film etching process is carried out at a depth of 1000 ~ 1500 Å from the top of the doped polysilicon film which is the upper layer of the bottom gate,

The insulating film spacers on the sidewalls of the bottom gate are formed by depositing and anisotropically etching a nitride film having a thickness of 1000 to 1500 Å,

Forming a selective epitaxially grown polysilicon film formed in the channel region under the upper gate at a thickness of 500 to 1000 Å,

Forming a selective epitaxially grown polysilicon film formed in the source / drain regions of the upper gate to a thickness of 2000 to 2500 mm 3;                     

The insulating film spacer is formed in a single layer of an oxide film or a nitride film, or a stacked structure of an oxide film and a nitride film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3L are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, an undoped polysilicon film 73, a doped polysilicon film 75, and a nitride film 77 are stacked on the semiconductor substrate 71.

In this case, the undoped polysilicon film 73 may be formed to a thickness of 300 to 500 Å, and may be formed of a nitride film.

The doped polysilicon film 75 is formed to a thickness of 500 to 1000 GPa, and the nitride film is formed to a thickness of 1500 to 10000 GPa.

Referring to FIG. 3B, the nitride layer 77, the doped polysilicon layer 75, and the undoped polysilicon layer 73 are etched by a photolithography process using a gate electrode mask (not shown). , A bottom gate region having a laminated structure of the doped polysilicon film 75 and the undoped polysilicon film 73 is defined. Here, the undoped polysilicon film 73 and the doped polysilicon film 75 form a bottom gate.

Referring to FIG. 3C, the trench 79 is formed by etching the semiconductor substrate 71 using the nitride film 77 of the bottom gate region as a mask.

At this time, the trench 79 is formed to a depth of 3000 ~ 3500Å from the surface of the semiconductor substrate 71.                     

Referring to FIG. 3D, an isolation layer 81 is formed over the entire surface.

In this case, the device isolation layer 81 is formed to a thickness of 4500 ~ 15000 Å.

Referring to FIG. 3E, the device isolation film 81 is planarized and etched, and the device isolation film 81 is etched using the CMP method to expose the nitride film 77 and the nitride film 77 is a mask. Tooth back or anisotropic etching is carried out to a depth of 1000 ~ 1500 Å from the top of the doped polysilicon film 75 which is the upper layer of the bottom gate.
Next, the nitride film 77 is removed.

Referring to FIG. 3F, a nitride film 83 is deposited on the entire surface.

The nitride film 83 is formed to have a thickness of 1000 to 1500 mm 3.

Referring to FIG. 3G, the nitride layer 83 is anisotropically etched to form a nitride layer 83 spacer on sidewalls of the bottom gate, that is, the undoped polysilicon layer 73 and the doped polysilicon layer 75. .

Referring to FIG. 3H, a bottom gate oxide film 85 is formed over the entire surface.

In this case, the bottom gate oxide film 85 is formed by a thermal oxidation process.

Referring to FIG. 3I, a planarized selective growth epitaxial polysilicon film 87 is formed over the entire surface. In this case, the selective growth epitaxial polysilicon film 87 is formed by the SEG method.

The upper portion is flattened and etched by the CMP method or the etch back method.

At this time, the selective epitaxially grown polysilicon film 87 above the bottom gate is formed to have a thickness of 500 to 1000 GPa and the other part is formed to have a thickness of 2000 to 2500 GPa.                     

Referring to FIG. 3J, a pad oxide film 89 is formed over the entire surface and ion implanted impurities for a threshold voltage.

Referring to FIG. 3K, the pad oxide layer 89 is removed, the gate oxide layer 90 is grown, and an upper gate 91 is formed thereon.

Next, a low concentration of impurity junction regions 93 are formed by ion implanting low concentrations of impurities into the selective growth epitaxial polysilicon layer 87 using the upper gate 91 as a mask.

In addition, an insulating spacer 95 is formed on sidewalls of the upper gate 91, and a high concentration of impurities are added to the selective growth epitaxial polysilicon layer 87 using the insulating layer spacer 95 and the upper gate 91 as a mask. Ion implantation forms a high concentration impurity junction region 97 to form a source / drain region of LDD structure.

The insulating film spacer 95 may be formed of a single layer of an oxide film or a nitride film, or may be formed in a stacked structure of the oxide film and the nitride film.

As described above, the method of forming the semiconductor device according to the present invention will be described in comparison with the related art.

First, in the case of the conventional double gate structure, it is difficult to simultaneously remove the parasitic series resistance reduction and the floating body effect because the thickness of the silicon layer of the channel region and the source / drain region is the same. A large thickness difference can be formed to effectively reduce source / drain parasitic series resistance and prevent spiking during contact formation.

Second, in the case of the conventional double gate structure, a circuit for controlling the potential of the bottom gate is necessary to eliminate the floating body effect, but the present invention is not necessarily required.

Third, in the conventional double gate structure, the parasitic capacitance is large because there is only a bottom gate oxide layer between the source / drain region and the bottom gate, but the present invention is advantageous in terms of parasitic capacitance by additionally forming a thick nitride sidewall.

Fourth, in the case of the conventional recessed gate structure, the lithography margin is reduced by recessing the channel region to reduce the lithography margin. However, the lithography margin is relatively advantageous because the upper gate is formed after the silicon film is planarized.

Fifth, in the case of the conventional recessed gate structure, the thickness of the silicon film of the channel region depends on the thickness of the LOCOS oxide film, which is a device isolation film, but the present invention is determined in the process of depositing and planarizing the polysilicon film by a selective epitaxial growth method. It is advantageous to secure a margin for the thickness of the channel region silicon film.

Sixth, the present invention provides the effect of dynamically adjusting the threshold voltage of the device by connecting the power supply circuit of the bottom gate when the off-leakage current characteristics are important, without connecting the bottom gate power circuit in the device to be used for general purposes.

Claims (12)

Forming a trench by laminating an undoped polysilicon film, a doped polysilicon film, and a nitride film on a semiconductor substrate, and etching the semiconductor substrate having a predetermined thickness and the stacked structure by a photolithography process using a gate electrode mask; Forming a device isolation film over the entire surface including the trench and planarizing etching to expose the nitride film; Etching the device isolation film to a predetermined thickness using the nitride film as a mask, removing the nitride film to form a bottom gate, and forming a nitride film spacer on sidewalls; Forming a bottom gate oxide film over the entire surface and forming a selective epitaxially grown polysilicon film to planarize the entire surface; Ion implanting a threshold voltage impurity into the selective epitaxially grown polysilicon film; Forming an upper gate oxide film and an upper gate on the selective epitaxially grown polysilicon film and ion implanting impurities of low concentration into the selective epitaxially grown polysilicon film; Forming an insulating film spacer on the sidewall of the upper gate, and implanting a high concentration of impurities into the selective epitaxially grown polysilicon film to form a source / drain region of an LDD structure. The method of claim 1, And the undoped polysilicon film is used as a gate insulating film of the bottom gate. The method of claim 2, And the gate insulating film is formed of a nitride film. The method of claim 1, The undoped polysilicon film is a method of forming a semiconductor device, characterized in that formed to a thickness of 300 to 500 kHz. The method of claim 1, The doped polysilicon film is formed to a thickness of 500 to 1000 GPa, and the nitride film is formed to a thickness of 1500 to 10000 GPa. The method of claim 1, And the trench is formed at a depth of 3000 to 3500 GPa from the surface of the semiconductor substrate. The method of claim 1, The device isolation film is a method of forming a semiconductor device, characterized in that formed to a thickness of 4500-15000 Å. The method of claim 1, And etching the device isolation film having a predetermined thickness to a depth of 1000 to 1500 kHz from an upper portion of the doped polysilicon film, which is an upper layer of the bottom gate. The method of claim 1, The nitride film spacer of the bottom gate sidewall is formed by depositing and anisotropically etching the nitride film to a thickness of 1000 ~ 1500 Å. The method of claim 1, And forming a selective epitaxially grown polysilicon film formed in the channel region under the upper gate at a thickness of 500 to 1000 Å. The method of claim 1, And forming a selective epitaxially grown polysilicon film formed in the source / drain regions of the upper gate to a thickness of 2000 to 2500 Å. The method of claim 1, And the insulating film spacer is formed of a single layer of an oxide film or a nitride film, or a stacked structure of an oxide film and a nitride film.

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