JP2007266390A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, capable of preventing etching residue of a semiconductor layer, when forming a back gate structure or a double gate structure on a semiconductor substrate by the SBSI method. <P>SOLUTION: By having the germanium concentration of a first SiGe layer 12a, formed on a semiconductor substrate 11, set up lower than the germanium concentration of a second SiGe layer 13a formed in the upper part, the etching rates of the first SiGe layer 12a and the second SiGe layer 13a are made almost the same. With such a composition, while high-speed etching of Si layer is prevented, the etching residue of the SiGe layer 13a and the like, selective etching is made possible in the SiGe layers 12a and 13a of multilayer structure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique capable of preventing an etching residue of a semiconductor layer when a back gate structure or a double gate structure is formed on a semiconductor substrate by an SBSI method.

Semiconductor devices that support a ubiquitous society are required to achieve higher speed, higher functionality, and lower power consumption. Although both are generally in a trade-off relationship and it is difficult to achieve both of them, SOI has long been expected as a device capable of realizing higher speed and lower power consumption than Bulk-Si.
On the other hand, an SOI element having a back gate structure (that is, an element such as an MIS transistor formed on an SOI substrate) controls a threshold voltage by a back gate bias, thereby reducing power consumption during standby and ensuring operation speed. Is attracting attention as a technology to achieve both. In addition, it is known that an SOI element having a double gate electrode can realize an ideal S value (inclination of the subthreshold region) in addition to the suppression of the short channel effect. It is attracting attention as a means.

However, such an SOI element is actually more expensive than an Bulk-Si substrate, and has not yet been fully spread.
That is, as an SOI substrate manufacturing method, a buried insulating film layer (Box layer) is formed by oxygen ion implantation or by bonding two Si substrates (for example, refer to Patent Document 1). . The conventional oxygen ion implantation method requires high-concentration oxygen ion implantation, has a long implantation time, is not economical, and has problems in the quality of both the Box layer and the SOI layer. Further, the conventional method of bonding two Si substrates requires two Si substrates. Although a device such as reusing one Si substrate several times can be seen, the actual situation is that it is inevitably more expensive than a Bulk-Si substrate in terms of material costs and processing costs.
Therefore, a method of manufacturing a low-cost SOI substrate using one Bulk-Si substrate has been proposed (see, for example, Non-Patent Document 1). This method is also called the SBSI method, in which a Si / SiGe / Si substrate is stacked, only the SiGe layer is selectively etched away, and the upper and lower exposed Si layers are filled with thermally oxidized SiO2 layers to form a box layer. Technology.
Japanese Patent Application Laid-Open No. 2000-124092 T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

In the SBSI method, by stacking a plurality of Si / SiGe layers on a Si substrate, the upper Si layer is used as a semiconductor layer for forming an SOI element, and the lower Si layer is used as a back gate electrode or a double gate electrode. It can be used.
However, when the present inventors have stacked a plurality of Si / SiGe layers in the SBSI method, the etching rate of the upper SiGe layer is smaller than the etching rate of the lower SiGe layer during selective etching of the SiGe layer, and the upper SiGe layer I noticed a problem that etching residue was likely to occur. If etching residue occurs in the upper SiGe layer, there may be a problem in the thickness and quality of the BOX layer formed there, and the Si layer forming the transistor is contaminated by Ge. .

  Therefore, the present invention has been made in view of such circumstances, and it is possible to prevent etching residue of a semiconductor layer when a back gate structure or a double gate structure is formed on a semiconductor substrate by an SBSI method. An object is to provide a method for manufacturing a semiconductor device.

[Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor device of Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor having an etching rate smaller than that of the first semiconductor layer. Forming a layer on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer having an etching rate that is the same as or higher than that of the first semiconductor layer. A step of forming on the third semiconductor layer a fourth semiconductor having an etching rate smaller than that of the first semiconductor layer, the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer. And forming a first groove through the first semiconductor layer to expose the semiconductor substrate, and a support for supporting the second semiconductor layer and the fourth semiconductor layer in the first groove. Forming process and Forming a second groove exposing the third semiconductor layer from under the fourth semiconductor layer after forming the support and exposing the first semiconductor layer from under the second semiconductor layer; A first cavity is formed between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer and the third semiconductor layer through a second groove, and the second semiconductor Forming a second cavity between the first semiconductor layer and the fourth semiconductor layer; forming a first insulating layer in the first cavity and forming a second insulating layer in the second cavity; It is characterized by including these.

  With such a configuration, the first cavity and the second cavity can be completed almost simultaneously, so that the remaining etching of the third semiconductor layer can be prevented. Therefore, the first and second insulating layers having good film quality and desired thickness can be formed in the first and second cavities, respectively. Thereby, for example, the threshold controllability of an element in which the second semiconductor layer is used as a back gate electrode or a double gate electrode can be improved.

[Invention 2] The semiconductor device manufacturing method of Invention 2 is the semiconductor device manufacturing method of Invention 1, wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed thicker than the third semiconductor layer. It is characterized by doing.
With such a configuration, the first insulating layer can be formed thick and the second insulating layer can be formed thin. Accordingly, the coupling capacitance (ie, parasitic capacitance) between the second semiconductor layer and the semiconductor substrate can be reduced. For example, when the second semiconductor layer is used as a back gate electrode or a double gate electrode, the threshold value of an element formed thereon can be controlled with a low voltage.

[Invention 3] The manufacturing method of a semiconductor device of Invention 3 is the manufacturing method of the semiconductor device of Invention 1 or Invention 2, wherein each of the first semiconductor layer and the third semiconductor layer is silicon germanium (SiGe), The second semiconductor layer and the fourth semiconductor layer are each made of silicon (Si), and the germanium (Ge) concentration of the first semiconductor layer is lower than the Ge concentration of the third semiconductor layer. .

  In such a configuration, the higher the Ge concentration, the higher the etching rate of the SiGe layer. Therefore, the etching of the second SiGe layer (ie, the upper SiGe layer) having the higher Ge concentration proceeds faster, resulting in the remaining etching. Can be prevented. In particular, when the etching of the first semiconductor layer is finished first, the etching of the third semiconductor layer in the previous period becomes extremely slow, so that the above configuration increases the etching rate of the third semiconductor layer, It is important that the etching is finished first. As a result, the first and second insulating layers having good film quality and desired thickness can be formed in the first and second cavities, respectively. Thereby, for example, the threshold controllability of an SOI element in which the first Si layer (that is, the lower Si layer) is used as a back gate electrode or a double gate electrode can be improved.

[Invention 4] The method for manufacturing a semiconductor device according to Invention 4 is the method for manufacturing a semiconductor device according to Invention 1 to Invention 3, before etching the first semiconductor layer and the third semiconductor layer through the second groove. And a step of introducing a p-type impurity into the second semiconductor layer.
With such a configuration, since holes are supplied from the second semiconductor layer to the third semiconductor layer, the third semiconductor layer can be easily etched (that is, the etching rate can be increased).

[Invention 5] A manufacturing method of a semiconductor device of Invention 5 includes a step of forming a first silicon germanium (SiGe) layer on a silicon (Si) substrate, a step of forming a first Si layer on the first SiGe layer, Forming a second SiGe layer having a germanium (Ge) concentration higher than the first SiGe layer on the first Si layer; forming a second Si layer on the second SiGe layer; and the second Si layer; Forming a second SiGe layer, a first groove penetrating the first Si layer and the first SiGe layer to expose the Si substrate, and a support for supporting the first Si layer and the second Si layer. Forming the first groove in the first groove, exposing the second SiGe layer from under the second Si layer after forming the support, and exposing the first SiGe layer from under the first Si layer. Forming a second groove, and etching the first SiGe layer and the second SiGe layer through the second groove, thereby forming a first cavity between the Si substrate and the first Si layer. Forming a second cavity between the first Si layer and the second Si layer, forming a first insulating layer in the first cavity, and forming a second cavity in the second cavity. And a step of forming an insulating layer.

With such a configuration, the etching rate of the second SiGe layer can be made equal to or higher than that of the first SiGe layer, so that the first cavity and the second cavity are completed almost simultaneously. be able to.
Therefore, the etching residue of the second SiGe layer and the accelerated etching of Si (the accelerated etching of the Si layer means that when Si is immersed in an etching solution, the etching rate of Si rapidly increases after a predetermined time has elapsed. It is possible to etch the SiGe layer having a multilayer structure while preventing the phenomenon). Thereby, for example, it is possible to improve the threshold controllability of an SOI element in which the first Si layer is used as a back gate electrode or a double gate electrode.

[Invention 6] A method for manufacturing a semiconductor device according to Invention 6 is the method for manufacturing a semiconductor device according to Invention 5, wherein the Ge concentration of the first SiGe layer is set within a range of 20% to 40% of SiGe by composition ratio. It is characterized by doing.
With such a configuration, the first SiGe layer can be hardly etched (that is, the etching rate can be reduced).

[Invention 7] The semiconductor device manufacturing method according to Invention 7 is the semiconductor device manufacturing method according to Invention 5, wherein the Ge concentration of the second SiGe layer is set within a range of 30% or more and 70% or less of SiGe by composition ratio. It is characterized by doing.
With such a configuration, the etching rate of the second SiGe layer can be increased with respect to the first SiGe layer, and the etching residue of the etching of the second SiGe layer can be prevented.

[Invention 8] A method for manufacturing a semiconductor device of Invention 8 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer on the first semiconductor layer. Forming a third semiconductor layer on the second semiconductor layer having a higher etching rate than the second semiconductor layer, and etching more than both the first semiconductor layer and the third semiconductor layer. Forming a fourth semiconductor having a low rate on the third semiconductor layer; penetrating the fourth semiconductor layer, the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; Forming a first groove exposing the semiconductor substrate, forming a support in the first groove to support the second semiconductor layer and the fourth semiconductor layer, and after forming the support From below the fourth semiconductor layer Exposing the third semiconductor layer and forming a second groove exposing the first semiconductor layer from below the second semiconductor layer; introducing a p-type impurity into the second semiconductor layer; After introducing the p-type impurity, the first semiconductor layer and the third semiconductor layer are etched through the second trench, whereby a first cavity is formed between the semiconductor substrate and the second semiconductor layer. Forming a second cavity, forming a second cavity between the second semiconductor layer and the fourth semiconductor layer, forming a first insulating layer in the first cavity, and forming the second cavity And a step of forming a second insulating layer in the portion.

  With such a configuration, since holes are supplied from the second semiconductor layer to the third semiconductor layer, the third semiconductor layer can be easily etched (that is, the etching rate can be increased). Accordingly, even when the first semiconductor layer is formed thick and the third semiconductor layer is formed thin, it is possible to prevent the remaining etching of the third semiconductor layer.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment Hereinafter, a semiconductor device manufacturing method according to a first embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 11A are plan views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 1B to 11B are FIGS. FIG. 11A is a cross-sectional view taken along lines A1-A1 ′ to A11-A11 ′, and FIGS. 1C to 11C are FIGS. 1A to 11A, respectively. It is sectional drawing when each is cut | disconnected by B1-B1'-B11-B11 'line | wire. In FIG. 11A, illustration of the interlayer insulating film 32 is omitted.

  As shown in FIGS. 1A to 1C, first, on a semiconductor substrate 11, a first semiconductor layer 12a, a second semiconductor layer 12b, a third semiconductor layer 13a, and a fourth semiconductor layer 13b. Are sequentially formed by epitaxial growth. The first semiconductor layer 12a and the third semiconductor layer 13a are made of a material having an etching rate (that is, an etching rate) larger than that of the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b. Here, the etching rate is an etching amount per unit time when the cavities 20a and 20b shown in FIGS. 6A to 6C are formed.

  1A to 1C, the materials of the semiconductor substrate 11, the first semiconductor layer 12a, the second semiconductor layer 12b, the third semiconductor layer 13a, and the fourth semiconductor layer 13b are, for example, Si, Ge, SiGe A combination selected from SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used. For example, the material of the semiconductor substrate 11 is Si, the material of the first semiconductor layer 12a and the third semiconductor layer 13a is SiGe, and the material of the second semiconductor layer 12b and the fourth semiconductor layer 13b is Si.

In the present invention, whether the etching rate of the third semiconductor layer 13a is the same as the etching rate of the first semiconductor layer 12a by changing one of the material or composition ratio of the first semiconductor layer 12a and the third semiconductor layer 13a. Alternatively, the etching rate is higher than the etching rate of the first semiconductor layer 12a.
For example, when the material of both the first semiconductor layer 12a and the third semiconductor layer 13a is SiGe, the germanium (Ge) concentration of the first semiconductor layer 12a is set lower than the Ge concentration of the third semiconductor layer 13a. Thereby, the etching rate of the third semiconductor layer 13a can be the same as the etching rate of the first semiconductor layer 12a or higher than the etching rate of the first semiconductor layer 12a. At this time, the Ge concentration of the third semiconductor layer 13a is preferably set in a range of 30% or more and 70% or less of SiGe as a composition ratio (at%). Furthermore, the Ge concentration of the first semiconductor layer 12a is more preferably set within a range of 20% or more and 40% or less of SiGe as a composition ratio (at%). The etching rate can be reduced by adjusting the Ge concentration of SiGe to be low.

The Ge concentration is adjusted by, for example, changing the gas mixing ratio when epitaxially growing the SiGe layer. The film thicknesses of the first semiconductor layer 12a, the second semiconductor layer 12b, the third semiconductor layer 13a, and the fourth semiconductor layer 13b are, for example, about 1 to 200 nm.
Next, as shown in FIGS. 1A to 1C, a base oxide film 14 is formed on the surface of the fourth semiconductor layer 13b by thermal oxidation of the fourth semiconductor layer 13b. Then, an antioxidant film 15 is formed on the entire surface of the base oxide film 14 by a method such as CVD. The antioxidant film 15 is, for example, a silicon nitride film. When the antioxidant film 15 is a silicon nitride film, in addition to the function of preventing the fourth semiconductor layer 13b, it can also function as a stopper layer for a planarization process by CMP (chemical mechanical polishing).

  Next, as shown in FIGS. 2A to 2C, the anti-oxidation film 15, the base oxide film 14, the fourth semiconductor layer 13 b, the first semiconductor layer 12 a, The groove 16 exposing the surface of the semiconductor substrate 11 is formed by patterning the second semiconductor layer 12b, the third semiconductor layer 13a, and the fourth semiconductor layer 13b. In the etching step for forming the groove 16, the etching may be stopped on the surface of the semiconductor substrate 11, or the semiconductor substrate 11 may be over-etched to form a recess in the semiconductor substrate 1. Further, the position of the trench 16 is made to correspond to a part of the element isolation region of the fourth semiconductor layer 13b.

  Next, as shown in FIGS. 3A to 3C, the first semiconductor layer 12 a and the third semiconductor layer 13 a are etched through the groove 16 to form a recess 51 on the inner wall of the groove 16. . When the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b are Si, and the first semiconductor layer 12a and the third semiconductor layer 13a are SiGe, an etching solution for the first semiconductor layer 12a and the third semiconductor layer 13a. For example, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used. Accordingly, it is possible to cut the first semiconductor layer 12a and the third semiconductor layer 13a while suppressing overetching of the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b.

  Next, as shown in FIGS. 4A to 4C, a support 18 embedded in the groove 16 is formed so as to cover the entire surface of the substrate by a method such as CVD. Here, the support 18 is also formed on the side walls of the first semiconductor layer 12 a, the second semiconductor layer 12 b, the third semiconductor layer 13 a, and the fourth semiconductor layer 13 b in the groove 16, and faces the inner wall of the groove 16. The recess 51 is embedded. That is, the second semiconductor layer 12b and the fourth semiconductor layer 13b are supported by the support 18 so as to be sandwiched not only from the side surfaces but also from the vertical direction. Thereby, the support 18 can support the second semiconductor layer 12b and the fourth semiconductor layer 13b on the semiconductor substrate 11 when the first semiconductor layer 12a and the third semiconductor layer 13a are removed.

  The support 18 formed so as to cover the entire substrate needs to support the fourth semiconductor layer 13b while maintaining flatness by suppressing the bending of the second semiconductor layer 12b and the fourth semiconductor layer 13b. There is. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength. In addition, as a material of the support 18, for example, an insulator such as a silicon oxide film is used.

  Next, as shown in FIGS. 5A to 5C, the support 18, the antioxidant film 15, the base oxide film 14, the first semiconductor layer 12 a, and the second semiconductor layer using a photolithography technique and an etching technique. By patterning 12b, the third semiconductor layer 13a, and the fourth semiconductor layer 13b, a groove 19 exposing the surface of the semiconductor substrate 11 is formed. In the etching process for forming the groove 19, the etching may be stopped on the surface of the semiconductor substrate 11, or the semiconductor substrate 11 may be over-etched to form a recess in the semiconductor substrate 1. Further, the position of the groove 19 corresponds to a part of the element isolation region of the fourth semiconductor layer 13b, and the direction thereof is, for example, a direction substantially orthogonal to the formation direction of the groove 16 in plan view.

  Next, as shown in FIGS. 6A to 6C, an etching gas or an etching solution is brought into contact with the first semiconductor layer 12a and the third semiconductor layer 13a through the groove 19 to thereby form the first semiconductor layer 12a. The third semiconductor layer 13a is etched away to form a cavity 20a between the semiconductor substrate 11 and the second semiconductor layer 12b, and a cavity 20b between the second semiconductor layer 12b and the fourth semiconductor layer 13b. Form.

  Here, since the support 18 is provided in the groove 16, even when the first semiconductor layer 12a and the third semiconductor layer 13a are removed, the second semiconductor layer 12b and the fourth semiconductor layer 13b are made semiconductor. It can be supported on the substrate 11. Further, since the groove 19 is provided separately from the groove 16, an etching gas or an etching solution is brought into contact with the first semiconductor layer 12a and the third semiconductor layer 13a under the second semiconductor layer 12b and the fourth semiconductor layer 13b. It becomes possible. Therefore, the cavity 20a is formed between the semiconductor substrate 11 and the second semiconductor layer 12b without deteriorating the quality of the second semiconductor layer 12b and the fourth semiconductor layer 13b, and the second semiconductor layer 12b and the fourth semiconductor layer 12b are formed. A cavity 20b can be formed between the semiconductor layer 13b and the semiconductor layer 13b.

  When the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b are Si, and the first semiconductor layer 12a and the third semiconductor layer 13a are SiGe, an etching solution for the first semiconductor layer 12a and the third semiconductor layer 13a. For example, hydrofluoric acid is used. Thereby, it is possible to remove the first semiconductor layer 12a and the third semiconductor layer 13a while suppressing over-etching of the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b.

  Next, as shown in FIGS. 7A to 7C, the semiconductor substrate 11 is thermally oxidized to form insulating films 21a and 21b on at least the wall surfaces of the cavities 20a and 20b, respectively. Then, as shown in FIGS. 8A to 8C, an insulating film is formed on the entire surface of the substrate by a method such as CVD to fill the groove 19. The formation of the insulating film 22 complements the filling of the cavity with the insulating films 21a and 21b. The insulating films 21a and 21b are made of silicon oxide when the semiconductor substrate 11, the second semiconductor layer 12b, and the fourth semiconductor layer 13b are Si. Further, as the material of the insulating film 22 formed by a method such as CVD, for example, a silicon nitride film or the like may be used in addition to the silicon oxide film.

Next, the insulating film 22 covering the entire surface of the substrate is planarized by CMP, for example, and the insulating film 22 is removed from the antioxidant film 15. As described above, when the antioxidant film 15 is a silicon nitride film, the antioxidant film 15 functions as a stopper layer for the planarization process by CMP.
Next, the antioxidant film 15 and the base oxide film 14 are removed by etching. When the antioxidant film 15 is a silicon nitride film, for example, hot phosphoric acid is used as an etchant, and when the base oxide film 14 is a silicon oxide film, for example, dilute hydrofluoric acid is used as an etchant. Thereby, as shown in FIGS. 9A to 9C, the surface of the fourth semiconductor layer 13b is exposed.

  Further, here, after removing the antioxidant film 15, an impurity such as phosphorus or boron is ion-implanted into the second semiconductor layer 12b. Thereby, the second semiconductor layer 12b can be made conductive, and the second semiconductor layer 12b can be used as one of the back gate electrode and the double gate electrode. When a p-type layer and an n-type layer are separately formed in the second semiconductor layer 12b, ion implantation is selectively performed using a resist pattern or the like. In the case where the p-type layer and the n-type layer are not separately formed (that is, only the p-type layer or the n-type layer is formed on the second semiconductor layer 12b over the entire substrate), the resist pattern Without being formed, phosphorus or boron ions are implanted into the entire surface of the substrate.

  This ion implantation step is preferably performed before the base oxide film 14 is removed. Thereby, crystal defects near the surface of the fourth semiconductor layer 14b can be reduced as much as possible. Further, in this ion implantation step, it is preferable to adjust the implantation energy so that the impurity implantation peak is at the interface between the insulating film 21a and the second semiconductor layer 12b. Thereby, the amount of impurities introduced into the insulating film 21b can be reduced as much as possible.

Next, as shown in FIGS. 10A to 10C, the fourth semiconductor layer 13 b is patterned by using a photolithography technique and an etching technique, so that the opening 31 exposing the insulating film 21 b is formed in the fourth semiconductor. Formed on layer 13b.
Next, the surface of the fourth semiconductor layer 13b is thermally oxidized to form the gate insulating film 23 on the surface of the fourth semiconductor layer 13b. Then, a polycrystalline silicon layer is formed on the fourth semiconductor layer 13b on which the gate insulating film 23 is formed by a method such as CVD. Furthermore, the gate electrode 24 is formed on the fourth semiconductor layer 13b by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, using the gate electrode 24 as a mask, impurities such as As, P, and B are ion-implanted into the fourth semiconductor layer 13b, thereby forming LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 24. A layer is formed on the fourth semiconductor layer 13b. Then, an insulating layer is formed on the fourth semiconductor layer 13b on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 25 are formed on the side walls. Further, impurities such as As, P, and B are ion-implanted into the fourth semiconductor layer 13b using the gate electrode 24 and the sidewall 25 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 25. A source layer 26a and a drain layer 26b made of layers are formed on the fourth semiconductor layer 13b.

  Thereafter, as shown in FIGS. 11A to 11C, an interlayer insulating layer 32 is deposited on the gate electrode 24 by a method such as CVD. Then, using the photolithography technique and the etching technique, the interlayer insulating film 32 and the insulating film 31b immediately below the opening 31 are removed by etching, the source layer 26a, the drain layer 26b, and the second semiconductor layer 12b. Contact holes are formed respectively on the top and the bottom. Then, a source contact electrode 33a, a drain contact electrode 33b, a gate contact electrode 33c, and a back gate contact electrode 33d are formed through metal film formation and patterning. The source contact electrode 33a, the drain contact electrode 33, and the gate contact electrode 33c are electrodes that are buried in the interlayer insulating layer 32 and connected to the source layer 26a, the drain layer 26b, and the gate electrode 24, respectively. The back gate contact electrode 33d is an electrode embedded in the interlayer insulating layer 32 and the insulating film 21b and connected to the second semiconductor layer (that is, the back gate electrode) 12b through the opening 31.

  As described above, according to the first embodiment of the present invention, since the cavity 20a and the cavity 20b can be completed almost simultaneously, the etching residue of the third semiconductor layer 13a can be prevented. Therefore, insulating films 21a and 21b having good film quality and a desired thickness can be formed in the cavities 20a and 20b, respectively. Thereby, for example, the threshold controllability of the MIS transistor in which the second semiconductor layer is used as the back gate electrode can be improved.

  That is, by setting the Ge concentration of the upper SiGe layer 13a higher than the Ge concentration of the lower SiGe layer 12a, the etching rates of the upper SiGe layer 13a and the lower SiGe layer 12a can be made substantially the same. As a result, the SiGe layers 12a and 13a having a multilayer structure can be selectively etched while preventing the Si layer from being accelerated and the remaining etching of the SiGe layer 13a. Therefore, an SOI element having a back gate structure or a double gate structure can be realized at low cost.

In the first embodiment, the gate electrode 24 and the second semiconductor layer 12b may be electrically connected via the back gate contact electrode 33d (that is, a double gate electrode is configured). As a result, the second semiconductor layer 12b and the gate electrode 24 can be controlled to have the same potential, and it is possible to suppress the short channel effect and improve the rising characteristics of the drain current in the subthreshold region, This is effective for miniaturization of transistors and reduction of leakage current during off-state.
(2) Second Embodiment FIGS. 12A and 13A are plan views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS. 12B and 13B. FIG. 12A and FIG. 13A are cross-sectional views taken along lines A12-A12 ′ and A13-A13 ′, respectively, and FIG. 12C and FIG. It is sectional drawing when a and FIG. 13 (a) are cut | disconnected by the B12-B12 'and B13-B13' line, respectively. 12 (a) to 13 (c), parts having the same configurations as those in FIGS. 1 (a) to 11 (c) are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 12A, illustration of the interlayer insulating film 32 is omitted.

In the second embodiment, as shown in FIGS. 1A to 1C, the first semiconductor layer 112a is formed thicker than the third semiconductor layer 113a. The material of the first semiconductor layer 112a and the third semiconductor layer 113a is, for example, SiGe. Further, the germanium (Ge) concentration of the first semiconductor layer 12a is set lower than the Ge concentration of the third semiconductor layer 13a.
With such a configuration, a large cavity can be formed between the semiconductor substrate 11 and the second semiconductor layer 12b, and a high cavity can be formed between the second semiconductor layer 12b and the fourth semiconductor layer 13b. A small cavity can be formed. Therefore, as shown in FIGS. 13A to 13C, the insulating film 121a can be formed thick, and the insulating film 121c can be formed thin.

Thereby, the coupling capacitance (that is, parasitic capacitance) between the second semiconductor layer 12b and the semiconductor substrate 11 can be reduced. Further, when the second semiconductor layer 12b is used as a back gate electrode or a double gate electrode, it is possible to control the threshold value of the MIS transistor formed thereon with a low voltage.
It has been confirmed that when the first semiconductor layer 12a is formed thick, the first semiconductor layer 12a is easily etched. Regarding this phenomenon, the inventor found that when the thickness of the semiconductor layer is large, the cavity formed by etching the semiconductor layer also increases, and as a result, the etchant can easily enter the cavity. I believe that. Further, it has been confirmed that when the third semiconductor layer 13a is formed thin, the third semiconductor layer 13a is hardly etched. Regarding this phenomenon, the present inventor has found that when the film thickness of the semiconductor layer is small, the cavity formed by etching the semiconductor layer also becomes small, and as a result, it becomes difficult for the etchant to enter the cavity. I think there is.

From the above, when the first semiconductor layer is formed thick and the third semiconductor layer is formed thin, the etching rate of the first semiconductor layer increases and the etching rate of the third semiconductor layer decreases.
For such a phenomenon, as described in the first embodiment, by adjusting the composition ratio (that is, Ge concentration) of the first semiconductor layer and the third semiconductor layer, it is possible to bring the respective etching rates closer. Is possible. That is, by setting the Ge concentration of the third semiconductor layer to be higher than the Ge concentration of the first semiconductor layer, the third semiconductor layer has an etching rate equal to or higher than that of the first semiconductor layer having a large film thickness and a high etching rate. Can be etched.

  On the other hand, the inventor prepares an n-type silicon substrate and a p-type silicon substrate as the semiconductor substrate 11 used in the first embodiment, and the third semiconductor layer 13a when the respective substrates are used. I compared the etching rates. As a result, it was confirmed that the third semiconductor layer 13a formed on the p-type silicon substrate has a higher etching rate than the third semiconductor layer 13a formed on the n-type silicon substrate. Regarding this phenomenon, the present inventor considers that the p-type silicon substrate is caused by holes being supplied from the substrate side to the third semiconductor layer 13a via the first and second semiconductor layers. Yes.

  Therefore, when the etching rates of the third semiconductor layer and the first semiconductor layer cannot be substantially equal only by adjusting the Ge concentration, the p-type impurity (for example, boron) is added to the second semiconductor layer 13a as an additional treatment, for example. It is possible to introduce a low concentration. With such a configuration, holes are supplied from the second semiconductor layer 12b to the third semiconductor layer 13a, so that the etching rate of the third semiconductor layer 13a can be increased.

  Note that the p-type impurity may be introduced into the second semiconductor layer 13a by, for example, epitaxially growing the second semiconductor layer 13a in an atmosphere containing diborane gas and doping with boron while performing epitaxy. Such a configuration is convenient because not only can p-type impurities be introduced into the second semiconductor layer, but also the doping target position (ie, peak) can be changed by time adjustment.

  The dope target position is preferably, for example, in the vicinity of the interface between the second semiconductor layer 12b and the third semiconductor layer 13a, that is, the upper portion of the second semiconductor layer 12b. With such a configuration, holes can be efficiently supplied from the second semiconductor layer 12b to the third semiconductor layer 13a.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment.

Explanation of symbols

  11 semiconductor substrate, 12a first semiconductor layer (first SiGe layer), 12b second semiconductor layer (first Si layer), 13a third semiconductor layer (second SiGe layer), 13b fourth semiconductor layer (second Si layer), 14 base Oxide film, 15 Antioxidation film, 16, 19 Groove, 18 Support, 20 Cavity, 21a, 21b Insulating film, 22 Insulating film, 23 Gate insulating film, 24 Gate electrode, 25 Side wall, 26a Source layer, 26b Drain Layer, 31 opening, 32 interlayer insulating film, 33a source contact, 33b drain contact, 33c gate contact, 33d back gate contact

Claims (8)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer on the second semiconductor layer having the same etching rate as that of the first semiconductor layer or having a higher etching rate than that of the first semiconductor layer;
Forming a fourth semiconductor having a lower etching rate on the third semiconductor layer than the first semiconductor layer;
Forming a first groove through the fourth semiconductor layer, the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer to expose the semiconductor substrate;
Forming a support in the first groove to support the second semiconductor layer and the fourth semiconductor layer;
Forming a second groove exposing the third semiconductor layer from below the fourth semiconductor layer and exposing the first semiconductor layer from below the second semiconductor layer after forming the support;
A first cavity is formed between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer and the third semiconductor layer through the second groove, and the second cavity Forming a second cavity between a semiconductor layer and the fourth semiconductor layer;
Forming a first insulating layer in the first cavity, and forming a second insulating layer in the second cavity. A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed thicker than the third semiconductor layer. The first semiconductor layer and the third semiconductor layer are each silicon germanium (SiGe), and the second semiconductor layer and the fourth semiconductor layer are each silicon (Si),
3. The method of manufacturing a semiconductor device according to claim 1, wherein a germanium (Ge) concentration of the first semiconductor layer is lower than a Ge concentration of the third semiconductor layer.   The method includes a step of introducing a p-type impurity into the second semiconductor layer before etching the first semiconductor layer and the third semiconductor layer through the second trench. The method for manufacturing a semiconductor device according to claim 3. Forming a first silicon germanium (SiGe) layer on a silicon (Si) substrate;
Forming a first Si layer on the first SiGe layer;
Forming a second SiGe layer having a germanium (Ge) concentration higher than the first SiGe layer on the first Si layer;
Forming a second Si layer on the second SiGe layer;
Forming a second groove that exposes the Si substrate through the second Si layer, the second SiGe layer, the first Si layer, and the first SiGe layer;
Forming a support in the first groove to support the first Si layer and the second Si layer;
Forming a second groove exposing the second SiGe layer from under the second Si layer after forming the support and exposing the first SiGe layer from under the first Si layer;
The first SiGe layer and the second SiGe layer are etched through the second groove to form a first cavity between the Si substrate and the first Si layer, and the first Si layer and the Forming a second cavity between the second Si layer;
Forming a first insulating layer in the first cavity, and forming a second insulating layer in the second cavity. A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the Ge concentration of the first SiGe layer is set in a range of 20% to 40% of SiGe by composition ratio.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the Ge concentration of the second SiGe layer is set in a range of 30% to 70% of SiGe by composition ratio. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer having a higher etching rate on the second semiconductor layer than the second semiconductor layer;
Forming a fourth semiconductor on the third semiconductor layer having a lower etching rate than both the first semiconductor layer and the third semiconductor layer;
Forming a first groove through the fourth semiconductor layer, the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer to expose the semiconductor substrate;
Forming a support in the first groove to support the second semiconductor layer and the fourth semiconductor layer;
Forming a second groove exposing the third semiconductor layer from below the fourth semiconductor layer and exposing the first semiconductor layer from below the second semiconductor layer after forming the support;
Introducing a p-type impurity into the second semiconductor layer;
After the p-type impurity is introduced, the first semiconductor layer and the third semiconductor layer are etched through the second trench, whereby a first gap is formed between the semiconductor substrate and the second semiconductor layer. Forming a cavity and forming a second cavity between the second semiconductor layer and the fourth semiconductor layer;
Forming a first insulating layer in the first cavity, and forming a second insulating layer in the second cavity. A method for manufacturing a semiconductor device, comprising:

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