JP2006041417A - Semiconductor substrate, semiconductor device, process for manufacturing the semiconductor substrate and process for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a semiconductor layer on insulating layers having film thicknesses that differ from each other. <P>SOLUTION: After a cavity 17 is formed between second single-crystal semiconductor layers 13a and 13b by removing first single-crystal semiconductor layers 12a and 12b between the second single-crystal semiconductor layers 13a and 13b and before the second single-crystal semiconductor layer 13a in a thickened BOX layer region R2 disappears, a semiconductor substrate 11, the second single-crystal semiconductor layers 13a and 13b and a support 16 are thermally oxidized to form an insulating layer 18 beneath the second single-crystal semiconductor layer 13b. The thickness of the insulating layer 18, beneath the second single crystal semiconductor layer 13b, is made to differ in the thickened BOX layer regions R2 and R3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor substrate, a semiconductor device, a method for manufacturing a semiconductor substrate, and a method for manufacturing a semiconductor device, and is particularly suitable for application to a field effect transistor formed on an SOI (Silicon On Insulator) substrate.

Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance.
For example, Patent Document 1 discloses a method of forming a high breakdown voltage field effect transistor having a drain breakdown voltage of about several hundred volts on an SOI substrate. Patent Document 2 discloses a method of forming a field effect transistor miniaturized to about submicron on an SOI substrate.

  Here, in the semiconductor elements having different applications, the optimum film thickness of the SOI layer and the film thickness of the BOX layer are different. That is, in a high breakdown voltage field effect transistor having a drain breakdown voltage of about several hundred volts, it is necessary to increase the thickness of the BOX layer in order to ensure the breakdown breakdown voltage and the back channel threshold breakdown voltage of the BOX layer. It is on the order of μm. For example, in a high withstand voltage field effect transistor having a drain withstand voltage of 50 V, the film thickness of the BOX layer is about several hundred nm, and in a high withstand voltage field effect transistor having a drain withstand voltage of 500 V, the film thickness of the BOX layer is only about several μm. It becomes.

  On the other hand, in a field effect transistor miniaturized to about submicron, it is necessary to reduce the thickness of the BOX layer in order to suppress a threshold drop due to the short channel effect, and the thickness of the BOX layer is on the order of several hundred angstroms. For example, when the execution channel length is 0.1 μm or less, it is necessary to set the film thickness of the SOI layer to 50 nm or less and set the film thickness of the BOX layer to 50 to 100 nm.

On the other hand, with the advent of the ubiquitous society, in order to further promote the downsizing, low power consumption, multi-functionality, and large capacity of portable information devices, devices with various withstand voltages and digital and analog devices have been added. Attention has been focused on SOC (System On Chip) technology that can be mounted on a chip.
Further, in Patent Document 3, in order to realize SOC on an SOI substrate, an insulating film is embedded at different depths from the main surface of the semiconductor substrate, so that different thicknesses of semiconductor elements suitable for the application can be obtained. Disclosed is a method of forming in an active layer having.
JP-A-7-211917 JP 2003-158091 A JP 2002-299951 A

However, in the methods disclosed in Patent Documents 1 to 3, the thickness of the BOX layer is kept constant on the SOI substrate. For this reason, in order to form semiconductor elements having different applications on the SOI substrate, it is necessary to make the semiconductor elements on different SOI substrates for each application, which is an obstacle to realizing the SOC. It was.
Accordingly, an object of the present invention is to provide a semiconductor substrate, a semiconductor device, a semiconductor substrate manufacturing method, and a semiconductor device manufacturing method capable of forming a semiconductor layer on insulating layers having different film thicknesses. .

In order to solve the above-described problems, according to a semiconductor substrate according to an aspect of the present invention, a semiconductor base material, insulating layers formed on the semiconductor base material and having different film thicknesses, and the insulating layer are provided. And a semiconductor layer formed thereon.
Thereby, while making it possible to set the film thickness of the BOX layer so as to be suitable for the use of the semiconductor element, semiconductor elements having different uses can be formed on the same SOI substrate. Therefore, the field effect transistor can be miniaturized while the short channel effect can be suppressed, and the breakdown voltage of the BOX layer and the back channel threshold voltage can be secured, and the high breakdown voltage can be secured. Field effect transistors can be formed on the same SOI substrate. Therefore, it becomes possible to realize a system-on-chip on the same SOI substrate, and it is possible to promote downsizing, low power consumption, multiple functions, and large capacity of a semiconductor device.

According to the semiconductor substrate of one embodiment of the present invention, the semiconductor layer is a single crystal semiconductor layer having the same thickness.
As a result, semiconductor elements having different uses can be formed on the single crystal semiconductor layer, and the system-on-chip can be realized on the same SOI substrate while improving the characteristics of the semiconductor elements. It becomes possible.

According to the semiconductor device of one embodiment of the present invention, a semiconductor substrate, insulating layers formed on the semiconductor substrate and having different thicknesses, a semiconductor layer formed on the insulating layer, And a semiconductor element having a different use formed in the semiconductor layer.
As a result, it is possible to form different semiconductor elements on the BOX layer having the optimum film thickness without making the semiconductor elements on different SOI substrates for each application. High performance can be achieved.

In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor substrate, the insulating layers formed in partial regions on the semiconductor substrate and having different thicknesses, and the semiconductor formed over the insulating layer And a semiconductor element formed on the semiconductor substrate and the semiconductor layer and having different uses.
The semiconductor device according to one aspect of the present invention further includes an element isolation region that isolates the semiconductor layer in the horizontal direction, and the insulating layer is disposed in a self-aligned manner between the element isolation regions. It is characterized by that.

This makes it possible to vary the film thickness of the BOX layer for each application of the semiconductor element while preventing the missing or overlapping of the BOX layer. Therefore, high integration and high reliability of the semiconductor elements can be achieved while enabling the semiconductor elements having different uses to be formed on the same SOI substrate.
Further, according to the semiconductor device of one embodiment of the present invention, the semiconductor layer formed over the thinner insulating layer among the insulating layers having different thicknesses is driven at a low voltage. A field effect transistor is disposed, and a high voltage driven field effect transistor is disposed in the semiconductor layer formed on the thicker insulating layer, and there is no insulating layer between the semiconductor substrate. A protective diode or a bipolar transistor is arranged in the semiconductor layer.

  As a result, in the high-speed / low-power semiconductor device, when the execution channel length is 0.1 μm or less, the thickness of the semiconductor layer can be reduced to 50 nm or less and the thickness of the BOX layer can be reduced to 10-100 nm. As a result, it is possible to provide a fine transistor with high performance and high reliability while suppressing the short channel effect. In addition, in a transistor with a high voltage load, the thickness of the BOX layer can be increased, and the breakdown voltage and back channel threshold voltage resistance of the BOX layer can be secured. An improved high voltage transistor can be provided. Further, in a semiconductor element in which a large current flows, the BOX layer can be omitted, and the performance and reliability of the semiconductor element in which a large current flows can be maintained.

  In addition, according to the method for manufacturing a semiconductor substrate according to one embodiment of the present invention, a semiconductor has a stacked structure in which a second semiconductor layer having a lower selectivity at the time of etching than the first semiconductor layer is stacked on the first semiconductor layer. Forming a plurality of layers on the substrate, forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate, and forming the first groove on the semiconductor substrate. Forming a support for supporting the two semiconductor layers on the side walls of the first and second semiconductor layers in the first groove; and at least one of the first semiconductor layers having the support formed on the side walls. Forming a second groove that exposes the portion from the second semiconductor layer in the first region partitioned by the first groove, and a layer higher than the first semiconductor layer exposed in the second groove Whether at least part of the first semiconductor layer is the second semiconductor layer Forming a third groove to be exposed in a second region partitioned by the first groove, and selectively etching the first semiconductor layer through the second groove and the third groove, A step of forming a cavity between the second semiconductor layers, and thermal oxidation of the second semiconductor layer until the second semiconductor layer sandwiched between the upper and lower portions disappears, whereby the second layer of the uppermost layer is formed. And a step of forming insulating layers having different film thicknesses disposed below the semiconductor layer.

  Thus, the second semiconductor layer can be supported on the semiconductor substrate via the support formed in the first groove, and the number of first semiconductor layers exposed from the second semiconductor layer Can be made different between the first region and the second region, and an etching gas or an etchant can be brought into contact with the first semiconductor layer through the second groove and the third groove. As a result, the first semiconductor layer sandwiched between the second semiconductor layers can be removed while the second semiconductor layer can be stably supported on the semiconductor substrate, and the second semiconductor layer can be removed. The number of first semiconductor layers removed in step 1 can be made different between the first region and the second region. As a result, the number of layers of the second semiconductor layer thermally oxidized after removing the first semiconductor layer sandwiched between the second semiconductor layers can be made different between the first region and the second region. Without degrading the quality of the second semiconductor layer, the thickness of the insulating layer disposed under the uppermost second semiconductor layer can be varied.

According to the method for manufacturing a semiconductor substrate of one embodiment of the present invention, the second semiconductor layer and the support are single crystal Si, and the first semiconductor layer is single crystal SiGe.
This makes it possible to achieve lattice matching between the second semiconductor layer, the support and the first semiconductor layer, and to increase the selection ratio during etching of the first semiconductor layer compared to the second semiconductor layer and the support. It becomes possible. For this reason, it is possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and it is possible to stably form the support in the first groove. BOX layers having different film thicknesses can be formed on the same semiconductor substrate without degrading quality.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor device has a stacked structure in which a second semiconductor layer having a lower selectivity at the time of etching than the first semiconductor layer is stacked on the first semiconductor layer. Forming a plurality of layers on the substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate; and the second semiconductor layer on the semiconductor substrate. Forming a support on the side walls of the first semiconductor layer and the second semiconductor layer in the first groove, and at least part of the first semiconductor layer on which the support is formed on the side wall. Forming a second groove exposed from the second semiconductor layer in a first region divided by the first groove; and a first semiconductor layer above the first semiconductor layer exposed by the second groove At least part of the layer is the second semiconductor layer Forming a third groove to be exposed in a second region partitioned by the first groove, and selectively etching the first semiconductor layer through the second groove and the third groove, A step of forming a cavity between the second semiconductor layers, and thermal oxidation of the second semiconductor layer until the second semiconductor layer sandwiched between the upper and lower portions disappears, whereby the second layer of the uppermost layer is formed. The method includes a step of forming insulating layers having different film thicknesses disposed under the semiconductor layer, and a step of forming semiconductor elements having different uses in the second semiconductor layer as the uppermost layer.

  As a result, the thickness of the insulating layer disposed under the uppermost second semiconductor layer can be varied without deteriorating the quality of the uppermost second semiconductor layer, and insulation between the element isolation regions can be achieved. The layers can be arranged in a self-aligning manner. For this reason, while making it possible to prevent the BOX layer from being missing or overlapping, it is possible to vary the film thickness of the BOX layer for each application of the semiconductor element, and to separate the semiconductor elements having different uses from each other into the single crystal semiconductor layer Thus, the system-on-chip can be reduced in size, reduced in power consumption, multifunctional, large capacity, and high in reliability.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 to 18 are a plan view and a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
1 and 2, on the semiconductor substrate 11, the first single crystal semiconductor layers 12a and 12b and the second single crystal semiconductor layers 13a and 13b are alternately stacked. For example, Si, Ge, SiGe, GaAs, InP, GaP, GaN, SiC, or the like is used as the material of the semiconductor substrate 11, the first single crystal semiconductor layers 12a, 12b, and the second single crystal semiconductor layers 13a, 13b. be able to.

  Here, the first single crystal semiconductor layers 12a and 12b can be made of a material having a higher selectivity during etching than the semiconductor substrate 11 and the second single crystal semiconductor layers 13a and 13b. In particular, when the semiconductor substrate 11 is Si, it is preferable to use SiGe as the first single crystal semiconductor layers 12a and 12b and Si as the second single crystal semiconductor layers 13a and 13b. Accordingly, the first single crystal semiconductor layers 12a and 12b and the second single crystal can be lattice-matched between the first single crystal semiconductor layers 12a and 12b and the second single crystal semiconductor layers 13a and 13b. A selection ratio between the semiconductor layers 13a and 13b can be ensured.

  The semiconductor substrate 11 can be provided with a non-BOX layer region R1, a thickened BOX layer region R2, and a thinned BOX layer region R3. A protective diode or a bipolar transistor is formed in the non-BOX layer region R1, a field-effect transistor driven at a high voltage is formed in the thick BOX layer region R2, and the thin BOX layer region R3 is formed in the thin BOX layer region R3. Can form a field effect transistor driven at a low voltage.

Then, a sacrificial oxide film 14 is formed on the surface of the second single crystal semiconductor layer 13b by thermal oxidation of the second single crystal semiconductor layer 13b. Then, an antioxidant film 15 is formed on the entire surface of the sacrificial oxide film 14 by a method such as CVD. For example, a silicon nitride film can be used as the antioxidant film 15.
Next, as shown in FIG. 3 and FIG. 4, using the photolithography technique and the etching technique, the antioxidant film 15, the sacrificial oxide film 14, the first single crystal semiconductor layers 12a and 12b, and the second single crystal semiconductor layer 13a. , 13b is patterned to form a groove M1 exposing the semiconductor substrate 11 along a predetermined direction.

  When the semiconductor substrate 11 is exposed, the etching may be stopped on the surface of the semiconductor substrate 11 or the semiconductor substrate 11 may be over-etched to form a recess in the semiconductor substrate 11. The arrangement position of the groove M1 can correspond to a part of the element isolation region that separates the non-BOX layer region R1, the thick BOX layer region R2, and the thin BOX layer region R3 from each other. Further, the non-BOX layer region R1, the thick BOX layer region R2, and the thin BOX layer region R3 are separated from each other, and the groove M1 is arranged so that the inside of the non-BOX layer region R1 is further finely divided. May be.

  Next, as shown in FIGS. 5 and 6, films are formed on the side walls of the first single crystal semiconductor layers 12a and 12b and the second single crystal semiconductor layers 13a and 13b, and the second single crystal semiconductor layers 13a and 13b are formed as semiconductors. A support 16 that is supported on the substrate 11 is formed in the groove M1. Note that when the support 16 formed on the sidewalls of the first single crystal semiconductor layers 12a and 12b and the second single crystal semiconductor layers 13a and 13b is formed, semiconductor epitaxial growth can be used. Here, the support 16 can be selectively formed on the sidewalls of the first single crystal semiconductor layers 12 a and 12 b and the second single crystal semiconductor layers 13 a and 13 b and the surface of the semiconductor substrate 11 by using semiconductor epitaxial growth. it can. The material of the support 16 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe. In particular, when the semiconductor substrate 11 and the second single crystal semiconductor layers 13a and 13b are Si and the first single crystal semiconductor layers 12a and 12b are SiGe, it is preferable to use Si as the material of the support 16.

  Thus, the lattice ratio between the support 16 and the first single crystal semiconductor layers 12a and 12b can be obtained, and the selection ratio between the support 16 and the first single crystal semiconductor layers 12a and 12b can be increased. Can be secured. Further, by using a semiconductor such as Si as the material of the support 16, it is possible to maintain a three-dimensional solid structure by the semiconductor even when the first single crystal semiconductor layers 12 a and 12 b are removed. Become. For this reason, chemical resistance and mechanical stress resistance can be improved, and a stable element isolation process with good reproducibility can be realized. In addition, as a material of the support body 16, you may make it use insulators, such as a silicon oxide film, besides a semiconductor.

  Next, as shown in FIGS. 7 and 8, using the photolithography technique and the etching technique, the antioxidant film 15, the sacrificial oxide film 14, the first single crystal semiconductor layers 12a and 12b, and the second single crystal semiconductor layer 13a, By patterning 13b, a groove M2 exposing the semiconductor substrate 11 is formed in the thickened BOX layer region R2 along a direction orthogonal to the groove M1. When the semiconductor substrate 11 is exposed, the etching may be stopped on the surface of the semiconductor substrate 11 or the semiconductor substrate 11 may be over-etched to form a recess in the semiconductor substrate 11. The arrangement position of the trench M2 can correspond to the element isolation region of the single crystal semiconductor layer 13b.

  Next, as shown in FIGS. 9 and 10, the antioxidant film 15, the sacrificial oxide film 14, the first single crystal semiconductor layer 12b, and the second single crystal semiconductor layer 13b are patterned by using a photolithography technique and an etching technique. Thus, the groove M3 exposing the second single crystal semiconductor layer 13a is formed in the thinned BOX layer region R3 along the direction orthogonal to the groove M1. In the case where the second single crystal semiconductor layer 13a is exposed, the etching may be stopped at the surface of the second single crystal semiconductor layer 13a, or the second single crystal semiconductor layer 13a may be over-etched to form the second single crystal semiconductor layer 13a. A recess may be formed in the semiconductor layer 13a. The arrangement position of the groove M3 can correspond to the element isolation region of the single crystal semiconductor layer 13b.

  Further, instead of exposing the surface of the second single crystal semiconductor layer 13a, the etching may be stopped at the surface of the first single crystal semiconductor layer 12b, or the first single crystal semiconductor layer 12b may be over-etched. Etching may be performed halfway through the single crystal semiconductor layer 12b. Here, by stopping the etching of the first single crystal semiconductor layer 12b, it is possible to prevent the surface of the second single crystal semiconductor layer 13a in the groove M3 from being exposed. Therefore, when the first single crystal semiconductor layers 12a and 12b are removed by etching, it is possible to reduce the time during which the second single crystal semiconductor layer 13a in the groove M3 is exposed to the etching solution or the etching gas. Overetching of the second single crystal semiconductor layer 13a can be suppressed.

  Next, as shown in FIGS. 11 and 12, the etching gas or the etching solution is brought into contact with the first single crystal semiconductor layers 12a and 12b through the groove M2, and the etching gas or the etching solution is supplied through the groove M3. The first single crystal semiconductor layers 12a and 12b in the thickened BOX layer region R2 are removed by etching by contacting the single single crystal semiconductor layer 12b, and the first single crystal semiconductor layer 12b in the thinned BOX layer region R3 is removed. Etch away. In the thickened BOX layer region R2, the cavity 17 is formed between the semiconductor substrate 11 and the second single crystal semiconductor layer 13a and between the second single crystal semiconductor layers 13a and 13b, and the thinned BOX layer region. In R3, the cavity 17 is formed between the second single crystal semiconductor layers 13a and 13b.

  Here, by providing the support 16 in the groove M1, the second single crystal semiconductor layers 13a and 13b are supported on the semiconductor substrate 11 even when the first single crystal semiconductor layers 12a and 12b are removed. In addition, by providing the grooves M2 and M3 in addition to the groove M1, the etching gas or the etching liquid is applied to the first single crystal semiconductor layers 12a and 12b respectively disposed below the second single crystal semiconductor layers 13a and 13b. Can be brought into contact with each other. Therefore, the cavity 17 is formed between the semiconductor substrate 11 and the second single crystal semiconductor layer 13a and between the second single crystal semiconductor layers 13a and 13b without deteriorating the crystal quality of the second single crystal semiconductor layers 13a and 13b. Can be formed.

  Further, in the thinned BOX layer region R3, the first single crystal semiconductor layer 12a is etched by setting the depth of the groove M3 so that the second single crystal semiconductor layer 13a remains on the first single crystal semiconductor layer 12a. It can be prevented from being removed, and the cavity 17 can be prevented from being formed between the semiconductor substrate 11 and the second single crystal semiconductor layer 13a. For this reason, when the second single crystal semiconductor layers 13a and 13b are thermally oxidized, the second single crystal semiconductor layer 13a in the thickened BOX layer region R2 is thermally oxidized from above and below, and the second single crystal semiconductor layers 13a and 13b in the thinned BOX layer region R3. The two single crystal semiconductor layers 13a can be thermally oxidized from above. As a result, the second single crystal semiconductor layer 13a in the thickened BOX layer region R2 can be eliminated while leaving the second single crystal semiconductor layer 13a in the thinned BOX layer region R3, and the thickened BOX layer The thickness of the BOX layer can be made different between the region R2 and the thinned BOX layer region R3.

  Note that when the semiconductor substrate 11, the second single crystal semiconductor layers 13a and 13b, and the support 16 are Si and the first single crystal semiconductor layers 12a and 12b are SiGe, the first single crystal semiconductor layers 12a and 12b are used as an etchant. Nitric acid is preferably used. Thus, a Si / SiGe selection ratio of about 1: 1000 to 10000 can be obtained, and the first single crystal can be suppressed while over-etching of the semiconductor substrate 11, the second single crystal semiconductor layers 13a and 13b, and the support 16 is suppressed. The crystal semiconductor layers 12a and 12b can be removed.

  Next, as shown in FIGS. 13 and 14, the semiconductor substrate 11, the second single crystal semiconductor layers 13 a and 13 b, and the support body 16 until the second single crystal semiconductor layer 13 a in the thickened BOX layer region R <b> 2 disappears. By performing the thermal oxidation, the insulating layer 18 is formed under the second single crystal semiconductor layer 13b. Here, by eliminating the second single crystal semiconductor layer 13a in the thickened BOX layer region R2, in the thickened BOX layer region R2, an insulating layer is formed between the second single crystal semiconductor layer 13a and the semiconductor substrate 11. 18 can be filled. On the other hand, in the thinned BOX layer region R3, even when thermal oxidation is performed until the second single crystal semiconductor layer 13a in the thickened BOX layer region R2 disappears, the first single crystal semiconductor layer 12a and the second single crystal semiconductor layer 12a A part of the semiconductor layer 13a can be left.

  Therefore, while maintaining the crystal quality of the second single crystal semiconductor layer 13b, the thickness of the insulating layer 18 below the second single crystal semiconductor layer 13b is increased in the thickened BOX layer region R2 and the thinned BOX layer region R3. Can be different. For this reason, while making it possible to set the film thickness of the BOX layer so as to be suitable for the use of the semiconductor element, semiconductor elements having different uses can be formed on the same semiconductor substrate 11.

  Further, depending on the film thickness of the second single crystal semiconductor layer 13b during epitaxial growth and the film thickness of the insulating layer 18 formed during thermal oxidation of the second single crystal semiconductor layer 13b, The film thickness can be defined. For this reason, the film thickness of the second single crystal semiconductor layer 13b can be accurately controlled, and the variation in the film thickness of the second single crystal semiconductor layer 13b can be reduced, and the thickened BOX layer region R2 can be reduced. The film thickness of the insulating layer 18 under the second single crystal semiconductor layer 13b can be made different between the thinned BOX layer region R3. In addition, by providing the antioxidant film 15 on the second single crystal semiconductor layer 13b, the surface of the second single crystal semiconductor layer 13b is prevented from being thermally oxidized and insulated under the second single crystal semiconductor layer 13b. The layer 18 can be formed.

  Further, by forming the insulating layer 18 so that the cavity portion 17 is embedded, the insulating layer 18 can be disposed in a self-aligned manner between the element isolation regions. For this reason, it is possible to prevent the BOX layer from being lost or overlapped between the thickened BOX layer region R2 and the thinned BOX layer region R3, and the thickness of the BOX layer is made different for each application of the semiconductor element. Therefore, high integration and high reliability of the semiconductor element can be achieved.

Note that after the insulating layer 18 is formed, high-temperature annealing is performed. Thereby, the insulating layer 18 can be reflowed, the stress of the insulating layer 18 can be relieved, and the interface state can be reduced.
Next, as shown in FIGS. 15 and 16, an insulating layer is formed on the second single crystal semiconductor layer by filling the trenches M1 to M3 in which the insulating layer 18 is formed on the sidewalls by a method such as CVD. To deposit. Then, the insulating layer is planarized using a method such as CMP (Chemical Mechanical Polishing) to expose the surface of the second single crystal semiconductor layer, and the buried insulating layer 19 is formed in the trenches M1 to M3. . For example, SiO ₂ or Si ₃ N ₄ can be used as the buried insulating layer 19.

Next, as shown in FIGS. 17 and 18, the impurity diffusion layer 22c is formed by selectively implanting ions into the second single crystal semiconductor layer 13b in the non-BOX layer region R1, thereby forming the non-BOX layer region R1. A protective diode is formed.
Further, in the thickened BOX layer region R2 and the thinned BOX layer region R3, the surface of the second single crystal semiconductor layer 13b is thermally oxidized to thereby form the gate insulating films 20a and 20b on the second single crystal semiconductor layer 13b. Respectively. Then, a polycrystalline silicon layer is formed on the second single crystal semiconductor layer 13b on which the gate insulating films 20a and 20b are formed by a method such as CVD. Then, by patterning the polycrystalline silicon film using photolithography technology and etching technology, gate electrodes 21a and 21b are formed on the second single crystal semiconductor layer 13b. Then, by ion implantation of impurities into the second single crystal semiconductor layer 13b using the gate electrodes 21a and 21b as a mask, the source / drain layers 22a and 22b respectively disposed on the sides of the gate electrodes 21a and 21b Two single crystal semiconductor layers 13b are formed.

Thereby, in the thinned BOX layer region R3, when the effective channel length of the high-speed / low-power semiconductor element is 0.1 μm or less, the thickness of the second single crystal semiconductor layer 13b is 50 nm or less, and the film of the BOX layer The thickness can be reduced to 10-100 nm, and a fully depleted SOI transistor in which the short channel effect is suppressed can be formed.
Further, in the thickened BOX layer region R2, it is possible to increase the film thickness of the BOX layer, and it is possible to secure the breakdown voltage and back channel threshold voltage resistance of the BOX layer, so that high performance and high reliability are achieved. Thus, a high-voltage transistor can be formed.

  Furthermore, in the non-BOX layer region R1, the BOX layer can be omitted, and a semiconductor element in which a large current flows can be formed while maintaining the performance and reliability of the semiconductor element. In addition, it is preferable to form a bipolar transistor in addition to the protective diode in the non-BOX layer region R1.

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Explanation of symbols

  R1 non-BOX layer region, R2 thick BOX layer region, R3 thin BOX layer region, 11 semiconductor substrate, 12a, 12b first single crystal semiconductor layer, 13a, 13b second single crystal semiconductor layer, 14 sacrificial oxide film, 15 Antioxidation film, M1, M2, M3 Element isolation groove, 16 support, 17 cavity, 18 oxide film, 19 buried insulating layer, 20a, 20b gate insulating film, 21a, 21b gate electrode, 22a, 22b source / Drain layer, 22c Impurity diffusion layer

Claims (9)

A semiconductor substrate;
Insulating layers having different film thicknesses formed on the semiconductor substrate;
A semiconductor substrate comprising: a semiconductor layer formed on the insulating layer.   2. The semiconductor substrate according to claim 1, wherein the semiconductor layer is a single crystal semiconductor layer having the same film thickness. A semiconductor substrate;
Insulating layers having different film thicknesses formed on the semiconductor substrate;
A semiconductor layer formed on the insulating layer;
A semiconductor device comprising: semiconductor elements having different uses formed in the semiconductor layer. A semiconductor substrate;
Insulating layers having different film thicknesses formed in partial regions on the semiconductor substrate;
A semiconductor layer formed on the insulating layer;
A semiconductor device comprising: semiconductor elements having different uses formed on the semiconductor substrate and the semiconductor layer. An element isolation region for isolating the semiconductor layer in the horizontal direction;
The semiconductor device according to claim 3, wherein the insulating layer is disposed in a self-aligned manner between the element isolation regions.   Of the insulating layers having different thicknesses, a field effect transistor driven at a low voltage is disposed in the semiconductor layer formed on the thinner insulating layer, and the thicker insulating layer is provided. A field effect transistor driven at a high voltage is disposed in a semiconductor layer formed on the layer, and a protective diode or a bipolar transistor is disposed in a semiconductor layer without an insulating layer between the semiconductor substrate and the semiconductor substrate. The semiconductor device according to claim 3, wherein the semiconductor device is provided. Forming a plurality of stacked structures on a semiconductor substrate, wherein a second semiconductor layer having a lower selectivity at the time of etching than the first semiconductor layer is stacked on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on side walls of the first semiconductor layer and the second semiconductor layer in the first groove;
Forming a second groove that exposes at least a part of the first semiconductor layer formed on the side wall of the support from the second semiconductor layer in a first region partitioned by the first groove;
A third groove that exposes at least a part of the first semiconductor layer above the first semiconductor layer exposed in the second groove from the second semiconductor layer is divided by the first groove. Forming in the region;
Forming a cavity between the second semiconductor layers by selectively etching the first semiconductor layer through the second grooves and the third grooves;
Insulating layers having different film thicknesses disposed under the uppermost second semiconductor layer by thermally oxidizing the second semiconductor layer until the second semiconductor layer sandwiched between the upper and lower sides of the cavity disappears And a step of forming the semiconductor substrate.   8. The method of manufacturing a semiconductor substrate according to claim 7, wherein the second semiconductor layer and the support are single crystal Si, and the first semiconductor layer is single crystal SiGe. Forming a plurality of stacked structures on a semiconductor substrate, wherein a second semiconductor layer having a smaller selectivity at the time of etching than the first semiconductor layer is stacked on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on sidewalls of the first semiconductor layer and the second semiconductor layer in the first groove;
Forming a second groove that exposes at least a part of the first semiconductor layer formed on the side wall of the support from the second semiconductor layer in a first region partitioned by the first groove;
A third groove that exposes at least a part of the first semiconductor layer above the first semiconductor layer that is exposed in the second groove from the second semiconductor layer is a second groove that is divided by the first groove. Forming in the region;
Forming a cavity between the second semiconductor layers by selectively etching the first semiconductor layer through the second and third grooves;
Insulating layers having different film thicknesses disposed under the uppermost second semiconductor layer by performing thermal oxidation of the second semiconductor layer until the second semiconductor layer sandwiched between the upper and lower sides of the cavity disappears Forming a step;
Forming a semiconductor element having a different use in the second semiconductor layer as the uppermost layer, and a method for manufacturing a semiconductor device.

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