JP2007201006A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ease restrictions on an arrangement direction of a gate electrode, in a semiconductor device in which an SOI structure is formed by applying thermal oxidation to semiconductor layers on upper and lower parts of a gap formed by laminating a first semiconductor layer 3 and a second semiconductor layer 4 on a semiconductor substrate 1 and by selectively removing the first semiconductor layer 3. <P>SOLUTION: An opening portion 7 for exposing one part of the semiconductor substrate 1 is formed so as to be provided on four corners on an active region of the second semiconductor layer 4, a supporter 8 embedded in the opening portion 7 is film-formed, an embedded insulation layer 11 is formed in a cavity portion 10 between the semiconductor substrate 1 and the second semiconductor layer 4, and then, the upper end of the second semiconductor layer 4 is thermally oxidized. In this way, the upper end of the second semiconductor layer 4 is rounded along a groove 9, and gate electrodes 15, 25 arranged so as to cross with each other at right angles so that their ends come over the groove 9, are formed on the second semiconductor layers 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a field effect transistor formed on a (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxygen) substrate or a bonded substrate is used.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at a low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in selectivity between Si and SiGe. A cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.

  Here, when the SOI transistor is formed in the SOI layer, there is a method using an STI (Shallow Trench Isolation) method for element isolation. This STI method has many advantages, such as a transistor being formed in an island-shaped semiconductor layer that is completely isolated from the surrounding semiconductor layers, so that no latch-up occurs between the transistors in the adjacent semiconductor layers. Has been reported. However, when element isolation is performed by the STI method, problems such as deterioration of the breakdown voltage and reliability of the gate insulating film at the corner portion of the isolated SOI layer and formation of a parasitic transistor having a low threshold voltage may occur. .

For this reason, when element isolation is performed by the STI method, problems such as deterioration of breakdown voltage and reliability of the gate insulating film in the corner portion of the SOI layer where element isolation is performed and formation of a parasitic transistor having a low threshold voltage are prevented. In order to achieve this, there is a method of rounding the upper end portion of the isolated SOI layer by performing high-temperature oxidation at about 1100 ° C.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 T.A. Sakai et al. “Separation by BondingSi Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstracts, p. 230-231, May (2004)

However, in order to manufacture a SIMOX substrate, it is necessary to ion-implant high concentration oxygen into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to bond two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.
In addition, in ion implantation and bonding, there is a large variation in the thickness of the SOI layer, and when the SOI layer is thinned to produce a fully depleted SOI transistor, there are problems such as a large variation in characteristics of the field effect transistor. there were.

  On the other hand, in the method disclosed in Non-Patent Document 1, when high-temperature oxidation at about 1100 ° C. is performed to round the upper end of the SOI layer that has been subjected to element isolation, Ge in the SiGe layer diffuses into the Si layer, There has been a problem that the leakage current is increased and the reliability of the gate insulating film is deteriorated. On the other hand, if the SiGe layer under the Si layer is removed and then subjected to high-temperature oxidation at about 1100 ° C. in order to round the upper end of the SOI layer that has been separated, the Si layer is formed at the end of the Si layer. Since the support for supporting on the Si substrate is embedded along a predetermined direction, it is difficult to round the upper end of the Si layer at the portion where the support is embedded. There was a problem of restrictions.

  Accordingly, an object of the present invention is to form a semiconductor layer on an insulator while suppressing manufacturing costs, and to relieve restrictions on the arrangement direction of the gate electrode, and to round the upper end portion of the semiconductor layer separated from the element A semiconductor device and a method for manufacturing the semiconductor device capable of performing the above are provided.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor layer formed by epitaxial growth on a semiconductor substrate and separated in a mesa shape, the semiconductor substrate and the semiconductor layer, Embedded in a buried insulating layer, disposed at a corner of the active region of the semiconductor layer, and formed to round the upper end of the semiconductor layer, a support that supports the semiconductor layer on the semiconductor substrate, and And a rounding part.

  As a result, it is possible to round the upper end of the semiconductor layer after embedding the buried insulating layer under the semiconductor layer, and the semiconductor layer even when the support for supporting the semiconductor layer on the semiconductor substrate is formed. It is possible to prevent the formation of the rounded portion from being hindered along the side. Further, even when semiconductor layers having different etching rates are formed on a semiconductor substrate in order to embed a buried insulating layer under the semiconductor layer, high-temperature oxidation can be performed after removing the semiconductor layers having different etching rates by etching. From this, it is possible to alleviate the electric field concentration applied to the end of the semiconductor layer under the gate electrode while preventing contamination by components contained in the semiconductor layers having different etching rates. In addition, it is possible to prevent the formation of a parasitic transistor, and it is possible to prevent the breakdown voltage and reliability of the gate insulating film from being deteriorated. As a result, it is possible to form an SOI transistor on a semiconductor layer without using an SOI substrate, to realize a reduction in the price of the SOI transistor, and to ease restrictions on the arrangement direction of the gate electrode. However, it became possible to prevent the breakdown voltage and reliability of the gate insulating film from being deteriorated, to reduce the interface state, and to suppress current leakage due to a parasitic transistor or the like. That is, the SOI transistor can be stably operated while ensuring the flexibility of the layout of the SOI transistor.

Further, according to the semiconductor device of one embodiment of the present invention, the support is disposed at the four corners of the semiconductor layer, and the rounded portions are the four sides of the upper end portion excluding the four corners of the active region of the semiconductor layer. It is characterized by being formed.
Accordingly, it is possible to form a buried insulating layer under the semiconductor layer while stably holding the semiconductor layer on the semiconductor substrate, and to form a rounded portion along the four sides of the semiconductor layer. It becomes. For this reason, it is possible to form the SOI transistor on the semiconductor layer while allowing the gate electrodes to be arranged in directions orthogonal to each other so as to straddle the rounded portion, and to ensure the flexibility of the layout of the SOI transistor. However, the SOI transistor can be operated stably.

The semiconductor device according to one aspect of the present invention further includes a gate electrode formed on the semiconductor layer so as to intersect with an upper end portion of the semiconductor layer in which the rounded portion is formed. And
Thereby, it is possible to alleviate the electric field concentration applied to the end portion of the semiconductor layer under the gate electrode, and it is possible to prevent a parasitic transistor from being formed on the end face of the semiconductor layer that is element-isolated, The breakdown voltage and reliability of the gate insulating film can be improved.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming on one semiconductor layer, forming an opening through the first and second semiconductor layers to expose the semiconductor substrate at a corner of an active region of the first and second semiconductor layers; Forming a support in the opening for supporting the second semiconductor layer on the semiconductor substrate, and exposing at least a portion of the first semiconductor layer from the second semiconductor layer after the support is formed; Forming a groove to be formed, and forming a cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the groove, under the second semiconductor layer; Through the groove Forming a buried insulating layer buried in the cavity, forming a rounded portion along the groove so as to round the upper end of the second semiconductor layer, and embedding in the groove Forming a buried insulator.

  Thus, even when the second semiconductor layer is stacked on the first semiconductor layer, the etching gas or the etchant can be brought into contact with the first semiconductor layer through the side wall exposed from the support. The first semiconductor layer can be removed using the difference in selectivity between the first and second semiconductor layers while leaving the two semiconductor layers, and embedded in the cavity under the second semiconductor layer. A buried insulating layer can be formed. Further, even when the first semiconductor layer under the second semiconductor layer is removed, the corners of the second semiconductor layer can be supported on the semiconductor substrate, and are arranged along the four sides of the second semiconductor layer. The upper end portion of the second semiconductor layer can be rounded through the groove. Therefore, it is possible to dispose the second semiconductor layer on the buried insulating layer without degrading the quality of the second semiconductor layer, and even when the gate electrode is disposed so as to intersect the trench, 2 Concentration of the electric field applied to the upper end of the semiconductor layer can be alleviated, and a parasitic transistor is formed at the corner of the semiconductor layer where the elements are isolated while ensuring the breakdown voltage of the gate insulating film and preventing the deterioration of reliability. This can be prevented. Further, a transistor can be formed in the island-shaped second semiconductor layer that is completely isolated from the surrounding semiconductor layers. As a result, an SOI transistor can be formed on the second semiconductor layer without using an SOI substrate, and the arrangement direction of the gate electrode even when the second semiconductor layer is separated by the STI method or the like. It is possible to reduce current leakage due to parasitic transistors, to ensure the breakdown voltage and reliability of the gate insulating film, and to reduce the cost of SOI transistors, while reducing the restrictions on the SOI transistors. The SOI transistor can be stably operated while ensuring the flexibility of layout.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, after forming the buried insulating layer buried in the cavity, the rounding is performed by high-temperature dry oxidation of the second semiconductor layer at 1050 ° C. or higher. Forming a portion.
Accordingly, the upper end portion of the second semiconductor layer can be rounded without impairing the embedding property of the buried insulating layer, and even when the gate electrode is disposed on the second semiconductor layer, the second semiconductor under the gate electrode. Since it is possible to alleviate the electric field concentration applied to the end of the layer, the breakdown voltage and reliability of the insulating film at the corner between the side surface and the surface of the second semiconductor layer are improved, and a low threshold transistor Can be prevented from being formed.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.
As a result, it is possible to increase the etching rate of the first semiconductor layer compared to the semiconductor substrate and the second semiconductor layer while allowing lattice matching between the semiconductor substrate, the second semiconductor layer, and the first semiconductor layer. . For this reason, it becomes possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and insulation between the second semiconductor layer and the semiconductor substrate is achieved without impairing the quality of the second semiconductor layer. It becomes possible.

The method for manufacturing a semiconductor device according to one aspect of the present invention further includes a step of forming a gate electrode on the second semiconductor layer so as to intersect the groove in which the rounded portion is formed. Features.
As a result, it is possible to reduce the electric field concentration applied to the end of the semiconductor layer under the gate electrode, and it is possible to prevent the formation of a parasitic transistor at the corner of the semiconductor layer where the elements are separated. The breakdown voltage and reliability of the gate insulating film can be improved.

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
1A to 11A are plan views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 1B to 11B are FIGS. Sectional views cut along lines A1-A1 ′ to A11-A11 ′ in FIG. 11A, and FIGS. 1C to 11C show B1- in FIG. 1A to FIG. It is sectional drawing cut | disconnected by the B1'-B11-B11 'line | wire, respectively.

  In FIG. 1, a first semiconductor layer 2 is formed on a semiconductor substrate 1 by epitaxial growth, and a second semiconductor layer 3 is formed on the first semiconductor layer 2 by epitaxial growth. The first semiconductor layer 2 can be made of a material having an etching rate larger than that of the semiconductor substrate 1 and the second semiconductor layer 3, and the material of the semiconductor substrate 1, the first semiconductor layer 2 and the second semiconductor layer 3 can be used. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can.

  As the first semiconductor layer 2, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used in addition to the single crystal semiconductor layer. Instead of the first semiconductor layer 2, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 1-200 nm, for example.

  Then, a base oxide film 4 is formed on the surface of the second semiconductor layer 3 by thermal oxidation of the second semiconductor layer 3. Then, an antioxidant film 5 is formed on the entire surface of the base oxide film 4 by a method such as CVD. As the antioxidant film 5, for example, a silicon nitride film can be used. In addition to the function of preventing the second semiconductor layer 3 from being oxidized, as a stopper layer for a planarization process by CMP (Chemical Mechanical Polishing). It can also function.

  Next, as shown in FIG. 2, by using the photolithography technique and the etching technique, the antioxidant film 6, the base oxide film 5, the second semiconductor layer 4 and the first semiconductor layer 3 are patterned, thereby the semiconductor substrate 1 An opening 7 that exposes a portion of is formed. Here, the openings 7 can be arranged so as to be at the four corners of the active region of the second semiconductor layer 3. When a part of the semiconductor substrate 1 is exposed, the etching may be stopped on the surface of the semiconductor substrate 1 or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. . Further, the position of the opening 7 can correspond to a part of the element isolation region of the second semiconductor layer 4.

  Next, as shown in FIG. 3, a support 8 embedded in the opening 7 is formed so as to cover the entire surface of the substrate by a method such as CVD. The support 8 is also formed on the side walls of the first semiconductor layer 3 and the second semiconductor layer 4 in the opening 7 so that the second semiconductor layer 4 can be supported on the semiconductor substrate 1. Further, the support 8 formed so as to cover the entire substrate needs to support the second semiconductor layer 4 while suppressing the bending of the second semiconductor layer 4 and maintaining flatness. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength. Moreover, as a material of the support 8, an insulator such as a silicon oxide film can be used.

  Next, as shown in FIG. 4, by patterning the support 8, the antioxidant film 6, the base oxide film 5, the second semiconductor layer 4 and the first semiconductor layer 3 using a photolithography technique and an etching technique, A groove 9 exposing a part of the first semiconductor layer 3 is formed. Here, the groove 9 can be disposed so as to surround the periphery of the active region of the second semiconductor layer 4 in which the opening 7 is disposed at the four corners, and is formed in a part of the element isolation region of the second semiconductor layer 4. Can be matched. For example, the grooves 9 can be arranged on the four sides of the second semiconductor layer 4 except for the openings 7 arranged at the four corners of the second semiconductor layer 4. When a part of the first semiconductor layer 3 is exposed, the etching may be stopped on the surface of the first semiconductor layer 3, or the first semiconductor layer 3 is over-etched to form a recess in the first semiconductor layer 3. May be formed. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first semiconductor layer 3 in the groove 9. Here, by stopping the etching of the first semiconductor layer 3 halfway, it is possible to prevent the surface of the semiconductor substrate 1 in the groove 9 from being exposed. For this reason, when the first semiconductor layer 3 is removed by etching, it is possible to reduce the time during which the semiconductor substrate 1 in the groove 9 is exposed to the etching solution or the etching gas. Can be suppressed.

Next, as shown in FIG. 5, the first semiconductor layer 3 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 3 through the groove 9, and the semiconductor substrate 1 and the second semiconductor layer are removed. And the cavity 10 is formed between the two.
Here, by providing the support 8 in the opening 7, the second semiconductor layer 4 can be supported on the semiconductor substrate 1 even when the first semiconductor layer 3 is removed, and the opening By providing the groove 9 separately from the portion 7, it becomes possible to bring the etching gas or the etching solution into contact with the first semiconductor layer 3 below the second semiconductor layer 4. For this reason, it is possible to achieve insulation between the second semiconductor layer 4 and the semiconductor substrate 1 without impairing the quality of the second semiconductor layer 4.

  When the semiconductor substrate 1 and the second semiconductor layer 4 are Si and the first semiconductor layer 3 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 3. preferable. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 3 can be removed while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 4. It becomes. Further, as the etchant for the first semiconductor layer 3, hydrofluoric acid overwater, ammonia overwater, or hydrofluoric acid overwater may be used.

  Further, before the first semiconductor layer 3 is etched away, the first semiconductor layer 3 may be made porous by a method such as anodic oxidation, or by ion implantation into the first semiconductor layer 3, The first semiconductor layer 3 may be made amorphous, or a P-type semiconductor substrate may be used as the semiconductor substrate 1. Thereby, the etching rate of the first semiconductor layer 3 can be increased, and the etching area of the first semiconductor layer 3 can be expanded.

Next, as shown in FIG. 6, a buried insulating layer 11 is formed in the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 4 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 4. To do. At this time, the sidewall of the second semiconductor layer 4 is also oxidized, and an oxide film 12 is formed on the sidewall of the second semiconductor layer 4.
In the case where the buried insulating layer 11 is formed by thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 4, it is preferable to use low-temperature wet oxidation that is reaction-controlled in order to improve the embedding property. Further, the buried insulating layer 11 may be formed so as to fill the entire cavity 10 or may be formed so that a part of the cavity 10 remains.

  In the method of FIG. 6, the buried insulating layer 11 is formed in the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 4 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 4. The cavity portion between the semiconductor substrate 1 and the second semiconductor layer 4 is formed by forming an insulating film in the cavity portion 10 between the semiconductor substrate 1 and the second semiconductor layer 4 by the CVD method. 10 may be embedded in the embedded insulating layer 11.

  As a result, it is possible to fill the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 4 with a material other than the oxide film while preventing the second semiconductor layer 4 from being reduced. Therefore, it is possible to increase the thickness of the buried insulating layer 11 disposed on the back surface side of the second semiconductor layer 4 and to reduce the dielectric constant, so that the back surface side of the second semiconductor layer 4 can be reduced. Parasitic capacitance can be reduced.

Further, by providing the antioxidant film 6 on the second semiconductor layer 4, the embedded insulating layer 11 is formed on the back surface side of the second semiconductor layer 4 while preventing the surface of the second semiconductor layer 4 from being thermally oxidized. Thus, the second semiconductor layer 4 can be prevented from being reduced.
Further, by making the arrangement positions of the openings 7 and 9 correspond to the element isolation regions of the second semiconductor layer 4, it is possible to collectively perform the element isolation in the horizontal direction and the vertical direction of the second semiconductor layer 4. At the same time, by embedding the support 8 in the opening 7, it is not necessary to secure the support 8 for supporting the second semiconductor layer 4 on the semiconductor substrate 1 in the active region. Therefore, an SOI transistor can be formed while suppressing an increase in the number of processes, and an increase in chip size can be suppressed, so that the cost of the SOI transistor can be reduced.

  Next, as shown in FIG. 7, the upper end portion of the second semiconductor layer 4 is rounded along the groove 9 by thermally oxidizing the semiconductor substrate 1 and the second semiconductor layer 4. Here, when the upper end portion of the second semiconductor layer 4 is thermally oxidized, dry oxidation is performed at a high temperature of around 1100 ° C., preferably 1050 ° C. to 1150 ° C. Thereby, the upper end portion of the second semiconductor layer 4 can be efficiently rounded, and even when the gate electrode 15 of FIG. 10 is disposed on the second semiconductor layer 4, the second semiconductor layer 4 below the gate electrode 15 The concentration of the electric field applied to the end portion can be reduced, the breakdown voltage and reliability of the insulating film at the corner portion on the side surface of the second semiconductor layer 4 are improved, and the formation of a parasitic transistor having a low threshold is prevented. Is possible.

  Here, the second semiconductor layer 4 is thermally oxidized before the trench 9 is filled with the buried insulator 13 of FIG. 8, so that an oxidizing gas is efficiently passed through the trench 9 to the upper end portion of the second semiconductor layer 4. The upper end portion of the second semiconductor layer 4 can be efficiently rounded. In addition, after the buried insulating layer 11 is formed by wet oxidation, high temperature dry oxidation is performed on the upper end portion of the second semiconductor layer 4, thereby ensuring the embeddability of the buried insulating layer 11 and the second semiconductor layer 4. Can be efficiently rounded.

  In addition, by arranging the openings 7 at the four corners of the active region of the second semiconductor layer 4, even when the support 8 is embedded in the openings 7, after removing the first semiconductor layer 3, The upper end portion of the second semiconductor layer 4 can be rounded along the four sides of the active region of the second semiconductor layer 4. For this reason, it is possible to prevent contamination due to components contained in the first semiconductor layer 3 and to arrange the gate electrodes in directions orthogonal to each other so as to straddle the rounded portion at the upper end of the second semiconductor layer 4. In addition, an SOI transistor can be formed over the semiconductor layer, and the SOI transistor can be stably operated while ensuring the flexibility of the layout of the SOI transistor.

  In the method of FIG. 7, the method of rounding the upper end portion of the second semiconductor layer 4 by thermally oxidizing the upper end portion of the second semiconductor layer 4 has been described. The upper end portion of the second semiconductor layer 4 may be rounded by etching the upper end portion. Here, when the end of the second semiconductor layer 4 made of Si is rounded, hydrofluoric acid or heated ammonia having a higher mixture ratio of hydrofluoric acid than the hydrofluoric acid used to remove the first semiconductor layer 3 By performing wet etching using excess water or the like, it is possible to process the support 8 and the base oxide film 5 with a high selectivity.

Next, as shown in FIG. 8, a buried insulator 13 embedded in the groove 9 is formed so as to cover the entire surface of the support 8 by a method such as CVD. As the buried insulator 13, for example, an insulator such as a silicon oxide film can be used.
Next, as shown in FIG. 9, the buried insulator 13 and the support 8 are thinned by a method such as CMP, and planarization by CMP is stopped using the antioxidant film 6 as a stopper layer. Subsequently, the surface of the second semiconductor layer 4 is exposed by removing the base oxide film 5 and the antioxidant film 6.

  Next, as shown in FIGS. 10 and 11, gate insulating films 14 and 24 are formed on the surface of the second semiconductor layer 4 by performing thermal oxidation of the surface of the second semiconductor layer 4, respectively. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 4 on which the gate insulating films 14 and 24 are formed by a method such as CVD. Then, by patterning the polycrystalline silicon layer using the photolithography technique and the etching technique, the gate electrodes 15 and 25 arranged so as to be orthogonal to each other so that the end portions are applied to the grooves 9 are formed in the second semiconductor layer 4. Form on each.

  Next, by using the gate electrodes 15 and 25 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 4, so that low-concentration impurities respectively disposed on the sides of the gate electrodes 15 and 25. An LDD layer made of the introduction layer is formed on the second semiconductor layer 4. Then, an insulating layer is formed on the second semiconductor layer 4 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 16 and 26 are formed on 25 side walls, respectively. Then, by using the gate electrodes 15 and 25 and the sidewalls 16 and 26 as masks, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 4 to be arranged on the sides of the sidewalls 16 and 26, respectively. Source layers 17 a and 27 a and drain layers 17 b and 27 b made of the high-concentration impurity introduced layer are formed on the second semiconductor layer 4, respectively.

  This makes it possible to form an SOI transistor on the second semiconductor layer 4 without using an SOI substrate, and the gate electrode 15 even when the second semiconductor layer 4 is separated by the STI method or the like. , 25 can be relaxed, current leakage due to parasitic transistors can be suppressed, the breakdown voltage and reliability of the gate insulating films 14 and 24 can be secured, and the SOI transistor can be reduced in price. In addition, the SOI transistor can be stably operated while ensuring the flexibility of the layout of the SOI transistor.

The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Oxide film, 3 1st semiconductor layer, 4 2nd semiconductor layer, 5 Base oxide film, 6 Antioxidation film, 7, 9 Groove, 8 Support body, 10 Cavity part, 11 Embedded insulating layer, 12 Oxidation Film, 13 buried insulator, 14, 24 gate insulating film, 15, 25 gate electrode, 16, 26 sidewall, 17a, 27a source layer, 17b, 27b drain layer

Claims (7)

A semiconductor layer formed by epitaxial growth on a semiconductor substrate and separated in a mesa shape;
A buried insulating layer buried between the semiconductor substrate and the semiconductor layer;
A support disposed in a corner of an active region of the semiconductor layer and supporting the semiconductor layer on the semiconductor substrate;
A semiconductor device comprising: a rounded portion formed so as to round an upper end portion of the semiconductor layer.   The said support body is arrange | positioned at the four corners of the active area | region of the said semiconductor layer, The said rounding part is formed in four sides of the upper end part except the four corners of the said semiconductor layer. Semiconductor device.   The semiconductor device according to claim 1, further comprising a gate electrode formed on the semiconductor layer so as to intersect with an upper end portion of the semiconductor layer in which the rounded portion is formed. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming an opening through the first and second semiconductor layers to expose the semiconductor substrate at a corner of the active region of the first and second semiconductor layers;
Forming a support in the opening for supporting the second semiconductor layer on the semiconductor substrate;
Forming a groove exposing at least a part of the first semiconductor layer from the second semiconductor layer after the support is formed;
Forming a cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the groove, under the second semiconductor layer;
Forming a buried insulating layer embedded in the cavity through the groove;
Forming a rounded portion formed to round the upper end portion of the second semiconductor layer along the groove;
Forming a buried insulator buried in the trench. A method for manufacturing a semiconductor device, comprising:   The semiconductor device manufacturing method according to claim 4, wherein the rounded portion is formed by high-temperature dry oxidation of the second semiconductor layer at 1050 ° C. or higher after forming the buried insulating layer buried in the cavity. Method.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.   The semiconductor device according to claim 4, further comprising a step of forming a gate electrode on the second semiconductor layer so as to intersect the groove in which the rounded portion is formed. Production method.

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