JP4862253B2 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor substrate, a semiconductor device, a method for manufacturing a semiconductor substrate, and a method for manufacturing a semiconductor device, and is particularly suitable for application to a field effect transistor formed on an SOI (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Further, for example, Non-Patent Document 1 discloses a method of forming a gate electrode on a SON (Silicon On Noting) substrate. That is, in this method, a gate electrode is formed on a semiconductor substrate having a stacked structure of Si / SiGe / Si. Then, the SiGe layers on both sides of the gate electrode are exposed by etching the Si / SiGe / Si layers on both sides of the gate electrode. Then, the cavity is formed under the Si layer where the gate electrode is disposed by selectively removing the SiGe layer by wet etching. Then, after epitaxial growth is selectively performed on both sides of the gate electrode, ion implantation is performed to form source / drain layers on both sides of the gate electrode.
M.M. Jurczak, T .; Scotnicki, M .; Paoli, B.M. Tormen, J-L. Regolini, C.I. Morin, A.M. Schitzz, J. et al. Martins, R.A. Pantel, J. et al. Galvier. “SON (Silicon On Nothing) -A NEW DEVICE ARCHITECTUR FOR THE ULSI ERA.” 1999 Symposium on VLSI Technology of Papers. 29-30

  However, in order to manufacture a SIMOX substrate, high-concentration oxygen ions must be implanted into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

Also, in ion implantation and polishing, the variation in the thickness of the SOI layer is large, and it is difficult to stabilize the characteristics of the field effect transistor when the SOI layer is thinned in order to produce a fully depleted SOI transistor. There was a problem.
In the method disclosed in Non-Patent Document 1, since the SON structure is formed only under the gate electrode and the SON structure cannot be formed in the source / drain region, the parasitic capacitance of the source / drain region is reduced. There was a problem that could not. Further, since the cavity under the Si layer in which the gate electrode is disposed is an air layer, there is a problem that mechanical strength, thermal conductivity, and the like are inferior to that of a bulk semiconductor and lack reliability.

  Accordingly, an object of the present invention is to provide a semiconductor substrate and a semiconductor capable of forming a highly reliable semiconductor layer on an insulator at low cost without any restriction on the position of the semiconductor layer formed on the insulator. An apparatus, a method for manufacturing a semiconductor substrate, and a method for manufacturing a semiconductor device are provided.

According to the method for manufacturing a semiconductor substrate according to one embodiment of the present invention, a step of forming a single crystal SiGe layer on a base material made of single crystal Si, and forming a single crystal Si layer on the single crystal SiGe layer A step of performing ion implantation of Ge into the first region of the single crystal SiGe layer after forming the single crystal Si layer, and a step of performing ion implantation of the single crystal SiGe layer after performing the ion implantation. Forming an opening exposing a portion of one region, and selectively processing the first region of the single crystal SiGe layer by treating the single crystal SiGe layer with hydrofluoric acid through the opening. Etching to form a cavity under the single crystal Si layer and filling the cavity with a thermal oxide film, wherein the opening is disposed in the element isolation region, To do.

Thus, even in the case of forming a cavity below the single-crystal Si layer, it becomes possible to support the single-crystal Si layer by a single-crystal SiGe layer, through the opening, the single-crystal Si layer under By bringing hydrofluoric acid into contact with the single crystal SiGe layer, a cavity can be formed under the single crystal Si layer. As a result, without impairing the quality of the single-crystal Si layer, along with it it becomes possible to achieve insulation between the substrate made of single-crystal Si layer and the single crystal Si, by thermal oxidation of the single crystal Si layer, a single A thermal oxide film can be formed on the back side of the crystalline Si layer, and a highly reliable single crystal Si layer can be formed on the insulator at low cost. In addition, it is not necessary to provide an opening for removing the single crystal SiGe layer under the single crystal Si layer in the element formation region, and it is possible to reduce the cost of the SOI transistor while suppressing an increase in chip size. .

This also allows lattice matching between the single crystal Si substrate , the single crystal Si layer and the single crystal SiGe layer, while making the single crystal SiGe more monocrystalline SiGe than the single crystal Si substrate and single crystal Si layer. It is possible to increase the selectivity during etching of the layer. Therefore, it is possible to stably form a good crystal quality single-crystal Si layer on a monocrystalline SiGe layer, without impairing the quality of the single-crystal Si layer, between the monocrystalline Si layer and the semiconductor substrate Insulation can be achieved.

A method for manufacturing a semiconductor device of one embodiment of the present invention includes the method for manufacturing a semiconductor substrate described above,
The method further includes a step of forming a gate electrode on the single crystal Si layer and a step of forming a source and a drain on the single crystal Si layer .

This makes it possible to dispose the single crystal Si layer on the insulating film while suppressing an increase in the number of steps, and to suppress an increase in defects in the single crystal Si layer. For this reason,
Without compromising the quality of the single-crystal Si layer, it is possible to achieve insulation between the substrate made of single-crystal Si layer and the single crystal Si, while suppressing the increase in cost, to improve the quality of the SOI transistor Is possible.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIGS. 1A to 5A are plan views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 1B to 5B are FIGS. Sectional views cut along lines A1-A1 ′ to A5-A5 ′ in FIG. 5A, FIGS. 1C to 5C are B1 in FIGS. 1A to 5A, respectively. It is sectional drawing cut | disconnected by the -B1'-B5-B5 'line | wire, respectively.

  In FIG. 1, a first semiconductor layer 2 is formed on a semiconductor substrate 1 by an epitaxial growth method, and a second semiconductor layer 3 is formed on the first semiconductor layer 2 by an epitaxial growth method. The first semiconductor layer 2 can be made of a material having a higher selection ratio during etching than the semiconductor substrate 1 and the second semiconductor layer 3, and the semiconductor substrate 1, the first semiconductor layer 2, and the second semiconductor layer 3 can be used. As the material, for example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. Further, when SiGe is used as the first semiconductor layer 2 and Si is used as the second semiconductor layer 3, the Ge concentration distribution in the first semiconductor layer 2 is the interface between the semiconductor substrate 1 and the first semiconductor layer 2 and the first semiconductor. In order to eliminate stacking faults generated at the interface between the layer 2 and the second semiconductor layer 3 as much as possible, the Ge concentration of the lowermost surface and the uppermost surface of the first semiconductor layer 2 is set to 20% or less, while the first semiconductor The Ge concentration of the intermediate layer of the layer 2 is preferably set to 20% or more in order to enhance the selectivity in the subsequent selective etching. The first semiconductor layer 2 and the second semiconductor layer 3 are preferably single crystal semiconductors. The first semiconductor layer 2 and the second semiconductor layer 3 are preferably single crystal semiconductors. The first semiconductor layer 2 and the second semiconductor layer 3 may be an amorphous semiconductor, a polycrystalline semiconductor, or a porous semiconductor. For example, the film thickness of the first semiconductor layer 2 can be about 2000 mm, and the film thickness of the second semiconductor layer 3 can be about 1000 mm. Then, an oxide film 4 is formed on the surface of the second semiconductor layer 3 by thermal oxidation of the second semiconductor layer 3. For example, the thickness of the oxide film 4 can be about 250 mm. Here, by forming the oxide film 4 on the second semiconductor layer 3, it is possible to reduce the thickness of the second semiconductor layer 3, and when the cavity 9 is formed below the second semiconductor layer 3. The second semiconductor layer 3 can be reinforced.

  Next, as shown in FIG. 2, the oxide film 4, the second semiconductor layer 3, and the first semiconductor layer 2 are patterned by using a photolithography technique and an etching technique, thereby exposing a part of the first semiconductor layer 2. The opening 8 to be formed is formed. Here, the opening 8 is preferably disposed in the element isolation region of the second semiconductor layer 3. This eliminates the need to provide an opening 8 for removing the first semiconductor layer 2 under the second semiconductor layer 3 in the element formation region, and reduces the cost of the SOI transistor while suppressing an increase in chip size. Is possible.

  When a part of the first semiconductor layer 2 is exposed, the etching may be stopped on the surface of the first semiconductor layer 2, or the first semiconductor layer 2 is over-etched to form a recess in the first semiconductor layer. You may make it form. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first semiconductor layer 2 in the opening 8. Here, by stopping the etching of the first semiconductor layer 2 in the middle, it is possible to prevent the surface of the semiconductor substrate 1 in the opening 8 from being exposed. For this reason, when the first semiconductor layer 2 is removed by etching, the time during which the semiconductor substrate 1 in the opening 8 is exposed to the etching solution or the etching gas can be reduced, and the semiconductor substrate 1 in the opening 8 can be overloaded. Etching can be suppressed.

Next, as shown in FIG. 3, an etching gas or an etchant is brought into contact with the first semiconductor layer 2 through the opening 8, thereby removing a part of the first semiconductor layer 2 by etching. A cavity 9 is formed between the second semiconductor layer 3 and the second semiconductor layer 3. At this time, an electric field may be applied to the semiconductor substrate 1 to promote selective etching of the first semiconductor layer 2.
When part of the first semiconductor layer 2 is removed by etching, the first semiconductor layer 2 remains in the element isolation region, and the first semiconductor layer 2 under the channel region and the source / drain region of the transistor is removed. It is preferable to make it.

  Here, by removing a part of the first semiconductor layer 2 by etching, the second semiconductor layer 3 can be supported on the semiconductor substrate 1 and the cavity 9 is formed under the second semiconductor layer 3. It becomes possible. For this reason, it becomes possible to arrange | position the 2nd semiconductor layer 3 on an insulator, without impairing the quality of the 2nd semiconductor layer 3, and the 2nd semiconductor layer 3 with high reliability is formed on an insulator cheaply. It becomes possible.

  Further, by leaving the first semiconductor layer 2 in the element isolation region, the second semiconductor layer 3 in which the channel region and the source / drain region of the transistor are formed can be disposed on the insulator. For this reason, it is possible to reduce the parasitic capacitance of the source / drain regions while suppressing the complexity of the manufacturing process, and it is possible to improve the quality and characteristics of the SOI transistor while suppressing an increase in cost.

  Further, when the semiconductor substrate 1 and the second semiconductor layer 3 are Si and the first semiconductor layer 2 is SiGe, it is preferable to use hydrofluoric acid as an etchant for the first semiconductor layer 2. As a result, a Si / SiGe selection ratio of about 1:10 to 1000 can be obtained, and the first semiconductor layer 2 can be removed while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 3. It becomes.

Next, as shown in FIG. 4, an oxide film 10 is formed in the cavity 9 by depositing an oxide film in the cavity 9 through the opening 8 by the chemical vapor deposition method.
As a result, the second semiconductor layer 3 can be insulated from the semiconductor substrate 1 while maintaining the crystal quality of the second semiconductor layer 3. Therefore, it is possible to stably manufacture a high-quality SOI substrate while suppressing an increase in processes, and it is possible to stably manufacture an SOI transistor while suppressing an increase in cost. Further, by embedding the oxide film 10 in the cavity 9 by the chemical vapor deposition method of the semiconductor substrate 1 and the second semiconductor layer 3, the mechanical strength of the second semiconductor layer 3 in which the cavity 9 is disposed is improved. Therefore, the reliability of the transistor formed in the second semiconductor layer 3 can be improved.

  In addition, the film thickness of the second semiconductor layer 3 after the oxide film 10 is formed under the second semiconductor layer 3 can be defined by the film thickness of the second semiconductor layer 3 during epitaxial growth. Therefore, the oxide film 10 can be formed under the second semiconductor layer 3 while enabling the thickness of the second semiconductor layer 3 to be accurately controlled, and the variation in the thickness of the second semiconductor layer 3 can be reduced. It can be reduced. In the step of forming the oxide film 10 in the cavity 9, the oxide film 10 is formed by thermally oxidizing the semiconductor substrate 1 and the second semiconductor layer 3 in the cavity 9 while allowing an oxidizing gas to enter. May be.

  Next, as shown in FIG. 5, the oxide film 4 on the second semiconductor layer 3 is removed to expose the surface of the second semiconductor layer 3. Then, after forming the element isolation insulating film 12, the surface of the second semiconductor layer 3 is thermally oxidized to form the gate insulating film 21 on the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 21 is formed by a method such as CVD. Then, the gate electrode 22 is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 22 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, thereby forming LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 22. Layers 23 a and 23 b are formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layers 23a and 23b are formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 24 are formed on the side walls of the electrodes 22. Then, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3 using the gate electrode 22 and the sidewall 24 as a mask, thereby introducing high-concentration impurities respectively arranged on the side of the sidewall 24. Source / drain layers 25 a and 25 b made of layers are formed on the second semiconductor layer 3.

  This makes it possible to dispose the second semiconductor layer 3 on the oxide film 10 while suppressing an increase in the number of processes, and to suppress an increase in defects in the second semiconductor layer 3. For this reason, it is possible to achieve insulation between the second semiconductor layer 3 and the semiconductor substrate 1 without impairing the quality of the second semiconductor layer 3, and to improve the quality of the SOI transistor while suppressing an increase in cost. It becomes possible.

FIGS. 6A to 9A are plan views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIGS. 6B to 9B are FIGS. FIGS. 6A to 9C are cross-sectional views taken along lines A11-A11 ′ to A14-A14 ′ of FIG. 9A, respectively, and FIGS. 6C to 9C are B11 of FIGS. 6A to 9A. It is sectional drawing cut | disconnected by the -B11'-B14-B14 'line | wire, respectively.
In FIG. 6, a first semiconductor layer 32a is formed on a semiconductor substrate 31, and a second semiconductor layer 33 is formed on the first semiconductor layer 32a. The first semiconductor layer 32a can be made of a material having a higher selectivity during etching than the semiconductor substrate 31 and the second semiconductor layer 33. In particular, when the semiconductor substrate 31 is Si, the first semiconductor layer 32a SiGe is preferably used as the second semiconductor layer 33. Then, an oxide film 34 is formed on the surface of the second semiconductor layer 33 by thermal oxidation of the second semiconductor layer 33.

  Next, as shown in FIG. 7, when SiGe is used as the first semiconductor layer 32a and Si is used as the second semiconductor layer 33, Ge ion implantation is selectively performed in a partial region of the first semiconductor layer 32a. In this way, the third semiconductor layer 32b having a higher Ge concentration than the first semiconductor layer 32a is formed. The third semiconductor layer 32b is preferably disposed under the second semiconductor layer 33 where the channel region and source / drain regions of the transistor are formed. Further, it is preferable that the first semiconductor layer 32a is left in the element isolation region without performing Ge ion implantation.

Next, as shown in FIG. 8, a part of the third semiconductor layer 32b is exposed by patterning the oxide film 34, the second semiconductor layer 33, and the third semiconductor layer 32b using a photolithography technique and an etching technique. The opening 38 to be formed is formed.
Next, as shown in FIG. 9, the third semiconductor layer 32b is removed by etching by bringing an etching gas or an etchant into contact with the third semiconductor layer 32b through the opening 38, and the semiconductor substrate 31 and the second semiconductor are removed. A cavity 39 is formed between the layer 33.

Here, by making the Ge concentration of the third semiconductor layer 32b higher than that of the first semiconductor layer 32a, it is possible to increase the selectivity during the etching of the third semiconductor layer 32b. For this reason, it is possible to remove the third semiconductor layer 32b in a wider range while suppressing the etching amount of the first semiconductor layer 32a and the second semiconductor layer 33.
Further, Ge ion implantation is performed while selectively removing Ge ion implantation into a partial region of the first semiconductor layer 32a, thereby enabling the removal of the Ge semiconductor-implanted third semiconductor layer 32b. It is possible to leave a part of the first semiconductor layer 32a not left. For this reason, even when the third semiconductor layer 32 b is removed by etching, the second semiconductor layer 33 can be supported on the semiconductor substrate 31 by the first semiconductor layer 32 a, and a cavity is formed under the second semiconductor layer 33. 39 can be formed. Therefore, the second semiconductor layer 33 can be disposed on the insulator without deteriorating the quality of the second semiconductor layer 33, and the highly reliable second semiconductor layer 33 is formed on the insulator at low cost. It becomes possible.

  Further, by allowing the first semiconductor layer 32a to remain in the element isolation region, the second semiconductor layer 33 in which the channel region and the source / drain region of the transistor are formed can be disposed on the insulator. For this reason, it is possible to reduce the parasitic capacitance of the source / drain regions while suppressing the complexity of the manufacturing process, and it is possible to improve the quality and characteristics of the SOI transistor while suppressing an increase in cost.

Next, an SOI transistor can be formed in the second semiconductor layer 33 through steps similar to those in FIGS.
FIGS. 10A to 13A are plan views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention, and FIGS. 10B to 13B are FIGS. Sectional views cut along lines A21-A21 ′ to A24-A24 ′ in FIG. 13 (a), and FIGS. 10 (c) to 13 (c) are B21 in FIGS. 10 (a) to 13 (a). It is sectional drawing cut | disconnected by the -B21'-B24-B24 'line | wire, respectively.

  In FIG. 10, a first semiconductor layer 52 a is formed on the semiconductor substrate 51. The first semiconductor layer 52a can be made of a material having a higher selectivity during etching than the semiconductor substrate 51. In particular, when the semiconductor substrate 51 is Si, SiGe is preferably used as the first semiconductor layer 52a. . Then, an oxide film 54a is formed on the surface of the first semiconductor layer 52a by thermal oxidation of the first semiconductor layer 52a.

Next, as shown in FIG. 11, a part of the surface of the semiconductor substrate 51 is exposed by removing a part of the oxide film 54a and the first semiconductor layer 52a using a photolithography technique and an etching technique. Note that the region from which part of the oxide film 54a and the first semiconductor layer 52a is removed preferably corresponds to the element isolation region.
Next, as shown in FIG. 12, the second semiconductor layer 52b is formed on the semiconductor substrate 51 by performing epitaxial growth using the oxide film 54a as a mask. Here, the second semiconductor layer 52b can be made of a material having a smaller selectivity at the time of etching than the first semiconductor layer 52a. In particular, when the semiconductor substrate 51 is Si, SiGe is used as the second semiconductor layer 52b. It is preferable. Further, when the selection ratio at the time of etching the second semiconductor layer 52b is smaller than that of the first semiconductor layer 52a, for example, the Ge concentration of the first semiconductor layer 52a is about 50% and the Ge concentration of the second semiconductor layer 52b is 5%. %.

  Next, as shown in FIG. 13, after removing the oxide film 54a, a third semiconductor layer 53 is formed on the first semiconductor layer 52a and the second semiconductor layer 52b by epitaxial growth. It should be noted that the third semiconductor layer 53 can be made of a material having a smaller selection ratio at the time of etching than the second semiconductor layer 52a. In particular, when the second semiconductor layer 52a is SiGe, the third semiconductor layer 53 It is preferable to use Si.

Here, by making the Ge concentration of the first semiconductor layer 52a higher than that of the second semiconductor layer 52b, it is possible to increase the selectivity during the etching of the first semiconductor layer 52a. For this reason, it is possible to remove the first semiconductor layer 52a in a wider range while suppressing the etching amount of the second conductor layer 52b and the third semiconductor layer 53.
In addition, by selectively forming the first semiconductor layer 52a in a partial region on the semiconductor substrate 51, the first semiconductor layer 52a can be removed while the second semiconductor layer 52b can be left. It becomes. For this reason, even when the first semiconductor layer 52 a is removed by etching, the third semiconductor layer 53 can be supported on the semiconductor substrate 51 by the second semiconductor layer 52 b, and a cavity is formed below the third semiconductor layer 53. Can be formed. Therefore, the third semiconductor layer 53 can be disposed on the insulator without impairing the quality of the third semiconductor layer 53, and the highly reliable third semiconductor layer 53 is formed on the insulator at low cost. It becomes possible.

  In addition, by arranging the second semiconductor layer 52b in the element isolation region, the third semiconductor layer 53 in which the channel region and the source / drain region of the transistor are formed can be disposed on the insulator. . For this reason, it is possible to reduce the parasitic capacitance of the source / drain regions while suppressing the complexity of the manufacturing process, and it is possible to improve the quality and characteristics of the SOI transistor while suppressing an increase in cost.

  Next, an SOI transistor can be formed in the second semiconductor layer 53 through steps similar to those in FIGS. 8, 9, 4, and 5.

The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  1, 31, 51 Semiconductor substrate, 2, 32a, 52a First semiconductor layer, 3, 52b Second semiconductor layer, 32b, 53 Third semiconductor layer, 4, 34, 54a, 54b Oxide film, 8, 38 opening, 9, 39 cavity portion, 10 oxide film, 12 element isolation insulating film, 21 gate insulating film, 22 gate electrode, 23a, 23b LDD layer, 24 sidewall spacer, 25a, 25b source / drain layer

Claims (2)

Forming a single crystal SiGe layer on a substrate made of single crystal Si ;
Forming a single crystal Si layer on the single crystal SiGe layer ;
Performing ion implantation of Ge into the first region of the single crystal SiGe layer after forming the single crystal Si layer;
Forming an opening exposing a portion of the first region of the single-crystal SiGe layer after performing the ion implantation;
The single crystal SiGe layer is hydrofluoric acid-treated through the opening, thereby selectively etching the first region of the single crystal SiGe layer to form a cavity under the single crystal Si layer. Process,
Filling the inside of the cavity with a thermal oxide film ,
The method of manufacturing a semiconductor substrate, wherein the opening is disposed in an element isolation region . A method for manufacturing a semiconductor substrate according to claim 1,
Forming a gate electrode on the single crystal Si layer ;
Forming a source and a drain in the single crystal Si layer ;
A method for manufacturing a semiconductor device, further comprising:

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