JP4670524B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a field effect transistor formed on a SON (Silicon On Notifying) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

  In recent years, SON (Silicon On Nothing) in which an air gap layer (relative permittivity = 1.0) is arranged under a Si layer instead of an air gap layer (relative permittivity = 3.9) of an SOI substrate has attracted attention. ing. It has been demonstrated that the transistor formed by the SON can achieve performance superior to that of the SOI transistor in terms of suppressing the short channel effect and reducing the parasitic capacitance.

Further, in Patent Document 3, in order to form SON, a SiGe layer and a Si layer are sequentially stacked on a Si substrate, an anchor for fixing the Si active region to the Si substrate is formed, and then only the SiGe layer is formed. A method for selective removal is disclosed.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 JP 2004-349702 A

  However, in the method of forming SON by the method disclosed in Patent Document 3, since the SiGe layer under the Si layer is removed, it is difficult to secure sufficient strength of the Si layer when the Si layer is thinned. It becomes. For this reason, there has been a problem that the Si layer may be bent or the air gap layer may be crushed during the planarization process by CMP during the selective etching of the SiGe layer or the element isolation formation process.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of forming an air gap layer under the semiconductor layer while improving the supporting strength of the semiconductor layer in which the field effect transistor is formed, and a method for manufacturing the semiconductor device. It is to be.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the first semiconductor layer is formed on the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer is the first semiconductor layer. Forming a film on a semiconductor layer; forming a first exposed portion that exposes the semiconductor substrate through the first and second semiconductor layers; and the first semiconductor through the first exposed portion. A step of removing a part of the first semiconductor layer under the second semiconductor layer by etching the layer in a lateral direction; and a step of wrapping under the second semiconductor layer through the first exposed portion. A step of forming a support for supporting the second semiconductor layer on the semiconductor substrate; and a second exposure for exposing at least a part of the first semiconductor layer on which the support is formed from the second semiconductor layer. Forming the portion, and the second Forming an air gap layer from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the protruding portion; and forming a gate insulating film on the second semiconductor layer. And forming a gate electrode on the second semiconductor layer through the gate insulating film, and performing ion implantation using the gate electrode as a mask, thereby providing a source / Forming a drain layer on the second semiconductor layer.

  As a result, not only the side wall of the second semiconductor layer but also the second semiconductor layer can be supported on the semiconductor substrate from below the second semiconductor layer, and the second semiconductor layer is stacked on the first semiconductor layer. Even in such a case, the etching solution can be brought into contact with the first semiconductor layer below the second semiconductor layer through the second exposed portion. Therefore, it is possible to stably support the second semiconductor layer on the semiconductor substrate while suppressing the bending of the second semiconductor layer, and the second semiconductor layer is stacked on the first semiconductor layer. Even in this case, the first semiconductor layer between the second semiconductor layer and the semiconductor substrate can be removed. As a result, it is possible to achieve insulation between the second semiconductor layer and the semiconductor substrate without impairing the quality of the second semiconductor layer, and to improve the uniformity of the thickness of the air gap layer, The price of the SON transistor can be reduced, and the variation in the characteristics of the SON transistor can be reduced.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.
As a result, it is possible to increase the etching rate of the first semiconductor layer compared to the semiconductor substrate and the second semiconductor layer while allowing lattice matching between the semiconductor substrate, the second semiconductor layer, and the first semiconductor layer. . For this reason, it becomes possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and insulation between the second semiconductor layer and the semiconductor substrate is achieved without impairing the quality of the second semiconductor layer. It becomes possible.

According to the method for manufacturing a semiconductor device of one aspect of the present invention, on the exposed surfaces of the first and second semiconductor layers exposed through the first exposed portion before forming the support. The method further includes the step of forming a silicon oxide film.
Thereby, a semiconductor / oxide film interface with few interface states can be formed at least on the sidewall of the second semiconductor layer.

In addition, according to the method of manufacturing a semiconductor device according to one aspect of the present invention, the exposed surfaces of the first semiconductor layer and the second semiconductor layer exposed through the first exposed portion before forming the support. The method includes a step of thermally oxidizing a part of the first semiconductor layer and the second semiconductor layer after forming a cap oxide film thereon.
Thus, after forming the cap oxide film, the first and second semiconductor layers are subjected to thermal oxidation, thereby suppressing outward diffusion of components contained in the first semiconductor layer and at least the second semiconductor layer. A semiconductor / oxide film interface with few interface states can be formed on the side wall of the layer.

According to the method for manufacturing a semiconductor device of one aspect of the present invention, on the exposed surfaces of the first and second semiconductor layers exposed through the first exposed portion before forming the support. Forming a semiconductor film; and thermally oxidizing the semiconductor film and thermally oxidizing a part of the first semiconductor layer and the second semiconductor layer.
Thus, after the exposed surfaces of the first and second semiconductor layers are covered with the semiconductor film, a part of the first and second semiconductor layers can be thermally oxidized, and the components contained in the first semiconductor layer can be removed. A semiconductor / oxide film interface with few interface states can be formed on the side wall of the second semiconductor layer while suppressing side diffusion.

The method for manufacturing a semiconductor device according to an aspect of the present invention includes a step of thermally oxidizing the back surface of the semiconductor substrate and the second semiconductor layer exposed in the air gap layer. .
As a result, the semiconductor substrate and the second semiconductor layer exposed in the air gap layer can be protected by the thermal oxide film, and the interface state on the back surface of the semiconductor substrate and the second semiconductor layer can be reduced. Can do.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention.
In FIG. 1, a semiconductor layer 5 is formed on a semiconductor substrate 1 via an air gap layer 3. The semiconductor layer 5 is patterned so that the lower surface of the semiconductor layer 5 is exposed on the semiconductor substrate 1. For example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe can be used as the material of the semiconductor substrate 1 and the semiconductor layer 5. Here, the width of the air gap layer 3 is configured to be narrower than the width of the semiconductor layer 5, and the lower surface of the semiconductor layer 5 is exposed from the air gap layer 3. A support 9 that supports the semiconductor layer 5 on the semiconductor substrate 1 is formed in contact with the side surface of the air gap layer 3. Here, the support 9 can be disposed so as to wrap around the semiconductor layer 5 through the side wall of the semiconductor layer 5. As a material for the support 9, an insulator such as a silicon oxide film can be used. A thermal oxide film 2 is formed on the boundary surface between the semiconductor substrate 1 and the air gap layer 3, and a thermal oxide film 4 is formed on the boundary surface between the semiconductor layer 5 and the air gap layer 3. Yes.

A gate electrode 7 is formed on the semiconductor layer 5 via a gate insulating film 6, and sidewalls 8 are formed on the side walls of the gate electrode 7. Further, the semiconductor layer 5 is formed with a source layer 10a and a drain layer 10b arranged so as to sandwich the gate electrode 7 therebetween.
Thus, even when the air gap layer 3 is formed under the semiconductor layer 5 by using the difference in etching rate between the semiconductor layers having different compositions in order to form the air gap layer 3 under the semiconductor layer 5, the semiconductor layer The semiconductor layer 5 can be supported not only from the side wall 5 but also from under the semiconductor layer 5. For this reason, it is possible to form the air gap layer 3 under the semiconductor layer 5 while suppressing the bending of the semiconductor layer 5, thereby improving the uniformity of the thickness of the air gap layer 3, and the semiconductor. It is possible to prevent the air gap layer 3 from being crushed in the planarization step by CMP during the selective etching of the layer 5 or the element isolation formation process. As a result, the SON transistors can be formed uniformly, and the price of the SON transistors can be reduced, and variations in the characteristics of the SON transistors can be reduced.

FIGS. 2A to 10A are plan views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIGS. 2B to 10B are FIGS. Sectional views cut along lines A2-A2 ′ to A10-A10 ′ in FIG. 10 (a), and FIGS. 2 (c) to 10 (c) are B2 in FIGS. 2 (a) to 10 (a). It is sectional drawing cut | disconnected by the -B2'-B10-B10 'line | wire, respectively.
In FIG. 2, a first semiconductor layer 22 and a second semiconductor layer 23 are sequentially stacked on a semiconductor substrate 21 by epitaxial growth. The first semiconductor layer 22 can be made of a material having an etching rate larger than that of the semiconductor substrate 21 and the second semiconductor layer 23. The material of the semiconductor substrate 21, the first semiconductor layer 22 and the second semiconductor layer 23 is as follows. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 21 is Si, it is preferable to use SiGe as the first semiconductor layer 22 and Si as the second semiconductor layer 23. Accordingly, the etching selection ratio between the first semiconductor layer 22 and the second semiconductor layer 23 is ensured while the lattice matching between the first semiconductor layer 22 and the second semiconductor layer 23 can be achieved. be able to. Further, as the first semiconductor layer 22, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used in addition to the single crystal semiconductor layer. Further, instead of the first semiconductor layer 22, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 22 and the 2nd semiconductor layer 23 can be about 10-200 nm, for example.

  Then, a sacrificial oxide film 24 is formed on the surface of the second semiconductor layer 23 by thermal oxidation of the second semiconductor layer 23. Then, an antioxidant film 25 is formed on the entire surface of the sacrificial oxide film 24 by a method such as CVD. As the antioxidant film 25, for example, a silicon nitride film can be used. In addition to the function as the antioxidant film, it can also serve as a stopper layer for a planarization process by CMP or the like.

  Next, as shown in FIG. 3, by using the photolithography technique and the etching technique, the antioxidant film 25, the sacrificial oxide film 24, the second semiconductor layer 23, and the first semiconductor layer 22 are patterned, so that the semiconductor substrate 21. A groove 26 that exposes is formed along a predetermined direction. When a part of the semiconductor substrate 21 is exposed, the etching may be stopped on the surface of the semiconductor substrate 21, or the semiconductor substrate 21 may be over-etched to form a recess in the semiconductor substrate 21. . Further, the arrangement position of the groove 26 can correspond to a part of the element isolation region of the second semiconductor layer 23.

  Next, as shown in FIG. 4, the first semiconductor layer 22 is laterally etched through the groove 26 to remove a part of the first semiconductor layer 22 disposed under the second semiconductor layer 23. The lower surface 28 at the end of the second semiconductor layer 23 is exposed from the first semiconductor layer 22. A thermal oxide film 27 is formed on the exposed surfaces of the first semiconductor layer 22 and the second semiconductor layer 23 by performing thermal oxidation of the exposed surfaces of the first semiconductor layer 22 and the second semiconductor layer 23 through the groove 26. To do. Before forming the thermal oxide film 27 on the exposed surfaces of the first semiconductor layer 22 and the second semiconductor layer 23, cap layers are formed on the side walls of the first semiconductor layer 22 and the second semiconductor layer 23 by a method such as CVD. You may make it form. Here, for example, a silicon oxide film or a silicon film can be used as the cap layer. Then, a part of the first semiconductor layer 22 and the second semiconductor layer 23 may be thermally oxidized in a state where the cap layers are formed on the side walls of the first semiconductor layer 22 and the second semiconductor layer 23.

  Thereby, while suppressing outward diffusion of components such as Ge contained in the first semiconductor layer 22, a semiconductor / oxide film interface having a small interface state is formed on at least the side wall of the second semiconductor layer 23 in which the groove 26 is formed. Can be formed. For this reason, the quality of the SOI transistor formed in the second semiconductor layer 23 is improved while suppressing contamination of the semiconductor manufacturing apparatus and the second semiconductor layer 23 with the components contained in the first semiconductor layer 22. Can be made.

Next, as shown in FIG. 5, the second semiconductor layer 23 is embedded in the groove 26 by a method such as CVD so as to wrap around the second semiconductor layer 23 through the sidewall of the second semiconductor layer 23. A support 29 that is supported on the substrate 21 is formed on the entire surface of the semiconductor substrate 21. As a material for the support 29, an insulator such as a silicon oxide film can be used.
Next, as shown in FIG. 6, by patterning the support 29, the antioxidant film 25, the sacrificial oxide film 24, the second semiconductor layer 23, and the first semiconductor layer 22 using a photolithography technique and an etching technique, A groove 30 exposing a part of the first semiconductor layer 22 is formed along a direction orthogonal to the groove 26. Here, the arrangement position of the groove 30 can correspond to a part of the element isolation region of the second semiconductor layer 23.

  When a part of the first semiconductor layer 22 is exposed, etching may be stopped in the middle of the first semiconductor layer 22 to form a recess in the first semiconductor layer 22. Alternatively, the surface of the semiconductor substrate 21 may be exposed through the first semiconductor layer 22 in the groove 30. Here, by stopping the etching of the first semiconductor layer 22 in the middle, the surface of the semiconductor substrate 21 in the groove 30 can be prevented from being exposed. For this reason, when the first semiconductor layer 22 is removed by etching, the time during which the semiconductor substrate 21 in the groove 30 is exposed to the etching solution or the etching gas can be reduced, and the overetching of the semiconductor substrate 21 in the groove 30 can be reduced. Can be suppressed.

Next, as shown in FIG. 7, the first semiconductor layer 22 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 22 through the groove 30, and the semiconductor substrate 21 and the second semiconductor layer are removed. An air gap layer 31 is formed between
Here, by providing the support 29 in the groove 26, the second semiconductor layer 23 can be supported on the semiconductor substrate 21 even when the first semiconductor layer 22 is removed, and the groove 26. By providing the groove 30 separately, the etching gas or the etchant can be brought into contact with the first semiconductor layer 22 disposed under the second semiconductor layer 23. Therefore, it is possible to achieve insulation between the second semiconductor layer 23 and the semiconductor substrate 21 without impairing the crystal quality of the second semiconductor layer 23.

  Further, by removing a part of the first semiconductor layer 22 disposed under the second semiconductor layer 23, not only the side wall of the second semiconductor layer 23 but also the second semiconductor layer 23 from under the second semiconductor layer 23. Can be supported on the semiconductor substrate 21. For this reason, the air gap layer 31 can be formed under the second semiconductor layer 23 while suppressing the bending of the second semiconductor layer 23, and the uniformity of the thickness of the air gap layer 31 can be improved.

  When the semiconductor substrate 21 and the second semiconductor layer 23 are Si and the first semiconductor layer 22 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 22. preferable. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 22 can be removed while suppressing overetching of the semiconductor substrate 21 and the second semiconductor layer 23. It becomes. Further, as an etchant for the first semiconductor layer 22, hydrofluoric acid / hydrogen peroxide, ammonia / hydrogen peroxide, or hydrofluoric acid / hydrogen peroxide may be used.

Further, before the first semiconductor layer 22 is removed by etching, the first semiconductor layer 22 may be made porous by a method such as anodic oxidation, or by ion implantation into the first semiconductor layer 22, The first semiconductor layer 22 may be made amorphous. Thereby, the etching rate of the first semiconductor layer 22 can be increased, and the etching area of the first semiconductor layer 22 can be increased.
Then, thermal oxidation is performed on the surfaces of the semiconductor substrate 21 and the second semiconductor layer 23 through the grooves 30, thereby forming a thermal oxide film 32 on the back surfaces of the semiconductor substrate 21 and the second semiconductor layer 23. As a result, the surfaces of the semiconductor substrate 21 and the second semiconductor layer 23 exposed by the air gap layer 31 can be protected by the thermal oxide film 32, and in particular, the back surface and side surfaces of the second semiconductor layer 23. The interface state of can be reduced.

Next, as shown in FIG. 8, a buried insulator 33 is deposited on the support 29 so as to fill the groove 30 by a method such as CVD. Note that a silicon oxide film can be used as the material of the buried insulator 33.
Next, as shown in FIG. 9, the buried insulator 33 and the support 29 are thinned using a method such as CMP (Chemical Mechanical Polishing), and planarization is performed using the antioxidant film 25 as a stopper layer. Subsequently, the surface of the second semiconductor layer 23 is exposed by removing the antioxidant film 25 and the sacrificial oxide film 24.

  Next, as shown in FIG. 10, the surface of the second semiconductor layer 23 is thermally oxidized to form a gate insulating film 34 on the surface of the second semiconductor layer 23. Then, a polycrystalline silicon layer or the like is formed on the second semiconductor layer 23 on which the gate insulating film 34 is formed by a method such as CVD. Then, the gate electrode 35 is formed on the second semiconductor layer 23 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, using the gate electrode 35 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 23 to thereby form LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 35. A layer is formed on the second semiconductor layer 23. Then, an insulating layer is formed on the second semiconductor layer 23 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 36 are formed on the side walls. Then, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 23 using the gate electrode 35 and the sidewall 36 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 36. Source / drain layers 37 a and 37 b made of layers are formed on the second semiconductor layer 23.

  As a result, the SON transistors can be formed uniformly, and it is possible to reduce the price of the SON transistors and to reduce variations in the characteristics of the SON transistors.

1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  1, 21 Semiconductor substrate, 2, 4 Thermal oxide film, 3, 31 Air gap layer, 5 Semiconductor layer, 22 First semiconductor layer, 23 Second semiconductor layer, 6, 34 Gate insulating film, 7, 35 Gate electrode, 8 , 36 Side wall, 9, 29 Support, 10a, 37a Source layer, 10b, 38b Drain layer, 24 Sacrificial oxide film, 25 Antioxidation film, 26, 32 Groove, 27 Thermal oxide film, 28 Lower surface, 33 Embedded insulator

Claims (6)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first exposed portion that exposes the semiconductor substrate through the first and second semiconductor layers;
Removing a part of the first semiconductor layer under the second semiconductor layer by laterally etching the first semiconductor layer through the first exposed portion;
Forming a support that is disposed so as to wrap around under the second semiconductor layer through the first exposed portion and supports the second semiconductor layer on the semiconductor substrate;
Forming a second exposed portion for exposing at least a part of the first semiconductor layer on which the support is formed from the second semiconductor layer;
By selectively etching the first semiconductor layer through the second exposed portion, the first semiconductor layer is formed.
Forming an air gap layer from which the semiconductor layer has been removed;
Forming a gate insulating film on the second semiconductor layer;
Forming a gate electrode on the second semiconductor layer via the gate insulating film;
Forming a source / drain layer on each side of the gate electrode on the second semiconductor layer by performing ion implantation using the gate electrode as a mask. Method. It said semiconductor substrate and said second semiconductor layer is Si, a method of manufacturing a semiconductor device according to claim 1, wherein said first semiconductor layer is characterized by a SiGe. The method further comprises forming a silicon oxide film on the exposed surfaces of the first and second semiconductor layers exposed through the first exposed portion before forming the support. A method for manufacturing a semiconductor device according to 1 or 2 . Before forming the support, a cap oxide film is formed on the exposed surfaces of the first semiconductor layer and the second semiconductor layer exposed through the first exposed portion, and then the first semiconductor layer and the second semiconductor layer are formed. method for producing a portion of the semiconductor layer a semiconductor device according to any one of claims 1, characterized in that it comprises the step of thermally oxidizing 3. Forming a semiconductor film on the exposed surfaces of the first and second semiconductor layers exposed through the first exposed portion before forming the support;
Wherein the semiconductor film with thermally oxidized, the first semiconductor layer and that the semiconductor device according to any one of claims 1, wherein 3 a and a step of a portion of the second semiconductor layer is thermally oxidized Production method. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, the back surface of the exposed semiconductor substrate and said second semiconductor layer, characterized in that it comprises a step of thermal oxidation at the air gap layer.

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