JP4670490B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and is particularly suitable for application to a method for manufacturing a field effect transistor formed on a (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in selectivity between Si and SiGe. A cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International GiGe Technology and Meeting Abstracts, pp. 230-231, May (2004)

  However, in order to manufacture a SIMOX substrate, high-concentration oxygen ions must be implanted into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

In addition, in the ion implantation and polishing, the variation in film thickness of the SOI layer is large, and it is difficult to stabilize the characteristics of the field effect transistor when the SOI layer is thinned in order to produce a fully depleted SOI transistor. There was a problem.
In the method disclosed in Non-Patent Document 1, SiO ₂ is used as a support for supporting the Si layer on the Si substrate when the SiGe layer is removed. For this reason, if the SiO ₂ layer on the Si layer is subjected to CMP after the BOX layer is formed between the Si substrate and the Si layer, the surface of the Si layer is stably exposed because there is no CMP stopper layer. There was a problem that could not.

  Here, when SiN is used as a support for supporting the Si layer on the Si substrate, a function as a CMP stopper can be obtained. However, when SiN is removed to expose the surface of the Si layer, the support is removed. The surface of the supporting bulk substrate is also exposed. For this reason, when the gate electrode is disposed on the Si layer, if the gate electrode is extended to the region that supported the support on the bulk substrate, a leakage current to the bulk substrate and the source / drain due to poor insulation occurs. There was a problem of danger.

On the other hand, if the gate electrode is extended in a direction that does not intersect the region that supported the support on the bulk substrate, the etching of the SiGe layer under the Si layer proceeds in this direction, so the width of the Si layer under the gate electrode is There is a problem that it becomes short and it becomes difficult to form a transistor having a large gate width.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can increase the gate width on the SOI layer and prevent insulation failure of the gate electrode without using an SOI substrate. It is.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor layer formed by epitaxial growth in a partial region on a semiconductor substrate, and the semiconductor substrate and the semiconductor layer A buried insulating layer buried in between, a notch formed at four corners of the semiconductor layer, a planarization film formed around the semiconductor layer so as to avoid the notch, and the planarization A gate electrode formed on the semiconductor layer so as to be stretched on the film, a source layer formed on the semiconductor layer and disposed on one side of the gate electrode, and formed on the semiconductor layer, And a drain layer disposed on the other side of the gate electrode.

  As a result, the semiconductor layer can be disposed on the semiconductor substrate via the buried insulating layer, and a support for supporting the semiconductor layer on the semiconductor substrate when the buried insulating layer is buried under the semiconductor layer is provided on the semiconductor layer. Can be placed at the four corners. For this reason, it becomes possible to arrange the gate electrode along the longitudinal direction of the semiconductor layer while avoiding the region where the support is in contact with the semiconductor substrate, and the gate electrode is arranged in the region without the planarization film. The gate width on the semiconductor layer can be increased while preventing the above. As a result, it is possible to form an SOI transistor on the semiconductor layer without using an SOI substrate, to realize a reduction in the price of the SOI transistor, and to reduce the semiconductor substrate and source due to poor insulation of the gate electrode. The current drive capability of the SOI transistor can be ensured while preventing the occurrence of leakage current to the drain layer.

  In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor layer formed by epitaxial growth in a partial region on the semiconductor substrate, and the buried insulation buried between the semiconductor substrate and the semiconductor layer A layer, a notch formed in a part on the long side of the semiconductor layer, a planarization film formed around the semiconductor layer so as to avoid the notch, and the planarization film A gate electrode formed on the semiconductor layer so as to extend, a source layer formed on the semiconductor layer and disposed on one side of the gate electrode, and formed on the semiconductor layer, the gate And a drain layer disposed on the other side of the electrode.

  As a result, the semiconductor layer can be disposed on the semiconductor substrate via the buried insulating layer, and a support for supporting the semiconductor layer on the semiconductor substrate when the buried insulating layer is buried under the semiconductor layer is provided on the semiconductor layer. It can arrange | position to a part of long side of. For this reason, even when the shape of the semiconductor layer is elongated, it is possible to stably support the semiconductor layer on the semiconductor substrate, and it is possible for an etching solution to enter the semiconductor layer from the long side of the semiconductor layer. This can be prevented. Therefore, an SOI transistor can be formed on the semiconductor layer without using an SOI substrate, and the gate width on the semiconductor layer can be increased while the gate electrode is disposed on the planarization film. . As a result, it is possible to reduce the cost of the SOI transistor, and to prevent the generation of leakage current to the semiconductor substrate and the source / drain layer due to poor insulation of the gate electrode, while improving the current driving capability of the SOI transistor. Can be secured.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer on the semiconductor substrate by epitaxial growth, and the second semiconductor having an etching rate smaller than that of the first semiconductor layer. Forming a layer on the first semiconductor layer by epitaxial growth, forming notches at four corners of the first semiconductor layer and the second semiconductor layer, and the semiconductor through the notches. Forming a support in contact with the substrate on the second semiconductor layer; forming an exposed portion for exposing a part of the first semiconductor layer from the second semiconductor layer; and via the exposed portion. And selectively etching the first semiconductor layer to form a cavity from which the first semiconductor layer has been removed between the semiconductor substrate and the second semiconductor layer, and filling the cavity. Forming a buried insulating layer; depositing an insulating film on the entire surface of the semiconductor substrate on which the buried insulating layer is formed; and reducing the thickness of the insulating film using the support as a stopper. Planarizing the insulating film, removing the support after planarizing the insulating film, exposing the surface of the second semiconductor layer, and extending on the planarized insulating film. Forming a gate electrode on the second semiconductor layer; and forming a source / drain layer disposed so as to sandwich the gate electrode in the second semiconductor layer.

  As a result, even when the second semiconductor layer is stacked on the first semiconductor layer, it becomes possible to contact the etching gas or the etchant with the first semiconductor layer through the exposed portion, leaving the second semiconductor layer. The first semiconductor layer can be removed using the difference in selectivity between the first and second semiconductor layers, and a buried insulating layer embedded in the cavity under the second semiconductor layer is formed. can do. In addition, even when the first semiconductor layer under the second semiconductor layer is removed, the second semiconductor layer can be supported on the semiconductor substrate, and the support body that supports the second semiconductor layer is the second. The support can be disposed on the second semiconductor layer while contacting the semiconductor substrate at the four corners of the semiconductor layer. Therefore, it is possible to embed an insulating film around the second semiconductor layer while using the support as a stopper, and to stably expose the surface of the second semiconductor layer in which the buried insulating layer is embedded. In addition, the gate electrode can be disposed along the longitudinal direction of the second semiconductor layer while avoiding the region where the support is in contact with the semiconductor substrate, and the semiconductor substrate and the source / drain due to poor insulation of the gate electrode. It is possible to increase the gate width on the second semiconductor layer while preventing generation of leakage current to the layer. As a result, an SOI transistor can be formed on the second semiconductor layer without using an SOI substrate, so that the SOI transistor can be reduced in price and the current driving capability of the SOI transistor can be secured. can do.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer on the semiconductor substrate by epitaxial growth, and the second semiconductor having an etching rate smaller than that of the first semiconductor layer. Forming a layer on the first semiconductor layer by epitaxial growth, forming a notch in a part on a long side of the first semiconductor layer and the second semiconductor layer, and the notch Forming a support on the second semiconductor layer through the semiconductor substrate, forming an exposed portion exposing a part of the first semiconductor layer from the second semiconductor layer, and Forming a cavity between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the exposed portion; and Embedded in the cavity Forming an embedded buried insulating layer; depositing an insulating film on the entire surface of the semiconductor substrate on which the buried insulating layer is formed; and thinning the insulating film using the support as a stopper, A step of planarizing the insulating film; a step of planarizing the insulating film and then removing the support; exposing a surface of the second semiconductor layer; and stretching on the planarized insulating film. Thus, the method includes a step of forming a gate electrode in the long side direction of the second semiconductor layer, and a step of forming a source / drain layer disposed so as to sandwich the gate electrode in the second semiconductor layer. It is characterized by.

Accordingly, the support can be disposed on the second semiconductor layer while the support supporting the second semiconductor layer is in contact with the semiconductor substrate at a part on the long side of the second semiconductor layer. For this reason, even when the shape of the second semiconductor layer is elongated, the second semiconductor layer can be stably supported on the semiconductor substrate, and the second semiconductor layer can be formed from the long side of the first semiconductor layer. It is possible to prevent the etching solution from entering below. In addition, an insulating film can be embedded around the second semiconductor layer while using the support as a stopper, and the surface of the second semiconductor layer in which the embedded insulating layer is embedded can be stably exposed. . As a result, the SOI transistor can be formed on the second semiconductor layer without using the SOI substrate, the SOI transistor can be reduced in price, and the semiconductor substrate due to the poor insulation of the gate electrode. In addition, it is possible to ensure the current drive capability of the SOI transistor while preventing the occurrence of leak current to the source / drain layer .

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
1 to 9 are perspective views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1, the first semiconductor layer 2 and the second semiconductor layer 3 are sequentially formed on the semiconductor substrate 1 by performing epitaxial growth. As a material of the semiconductor substrate 1, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe can be used. The first semiconductor layer 2 can be made of a material having a higher etching rate than the semiconductor substrate 1 and the second semiconductor layer 3, and the material of the first semiconductor layer 2 and the second semiconductor layer 3 can be Si, for example. , Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. The first semiconductor layer 2 may be a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer. Instead of the first semiconductor layer 2, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 1-100 nm, for example.

Next, as shown in FIG. 2, the first semiconductor layer 2 and the second semiconductor layer 3 are patterned using a photolithography technique and an etching technique, thereby exposing a part of the surface of the semiconductor substrate 1. 4 are formed at the four corners of the first semiconductor layer 2 and the second semiconductor layer 3.
Next, as shown in FIG. 3, a support layer 5 is formed on the entire surface of the semiconductor substrate 1 so as to cover the second semiconductor layer 3 by a method such as CVD, and a photolithography technique and an etching technique are used. By patterning the support layer 5, the side edges of the second semiconductor layer 3 are exposed from the support layer 5 while the support layer 5 is in contact with the semiconductor substrate 1 at the four corners of the second semiconductor layer 3. Let For example, a silicon nitride film can be used as the support layer 5. In addition, before the support layer 5 is formed on the second semiconductor layer 3, the surface of the second semiconductor layer 3 is thermally oxidized to form the sacrificial oxide film 4 on the surface of the second semiconductor layer 3. Good.

Next, as shown in FIG. 4, by etching the second semiconductor layer 3 and the first semiconductor layer 2 using the support layer 5 as a mask, the side walls of the second semiconductor layer 3 and the first semiconductor layer 2 are exposed. An exposed surface 6 is formed.
Next, as shown in FIG. 5, the first semiconductor layer 2 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 2 through the exposed surface 6, so that the semiconductor substrate 1 and the second semiconductor are removed. A cavity 7 is formed between the layer 3.

  Here, even when the second semiconductor layer 3 is formed on the first semiconductor layer 2 by forming the exposed surface 6 that exposes a part of the end portion of the first semiconductor layer 2, the second semiconductor layer 2. Thus, the etching gas or the etching solution can be brought into contact with the first semiconductor layer 2 below, and the cavity 7 can be formed between the semiconductor substrate 1 and the second semiconductor layer 3. Further, the remaining part of the end of the second semiconductor layer 3 is covered with the support layer 5, so that the second semiconductor layer 3 is supported even when the first semiconductor layer 2 is removed. The body layer 5 can be supported on the semiconductor substrate 1.

  Further, the support layers 5 are formed at the four corners of the second semiconductor layer 3 by forming the notches 4 exposing the part of the surface of the semiconductor substrate 1 at the four corners of the first semiconductor layer 2 and the second semiconductor layer 3. The semiconductor substrate 1 can be contacted. Therefore, even when the first semiconductor layer 2 under the second semiconductor layer 3 is removed, the second semiconductor layer 3 can be stably supported on the semiconductor substrate 1, and the first semiconductor layer The intrusion path of the etching solution for removing 2 can be expanded, and the etching residue of the first semiconductor layer 2 can be prevented while suppressing the erosion of the second semiconductor layer 3.

  In the case where the semiconductor substrate 1 and the second semiconductor layer 3 are Si and the first semiconductor layer 2 is SiGe, it is preferable to use hydrofluoric acid as an etchant for the first semiconductor layer 2. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 2 can be removed while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 3. It becomes. Further, as an etchant for the first semiconductor layer 2, hydrofluoric acid / hydrogen peroxide, ammonia / hydrogen peroxide, or hydrofluoric acid / hydrogen peroxide may be used.

  Further, before the first semiconductor layer 2 is removed by etching, the first semiconductor layer 2 may be made porous by a method such as anodic oxidation, or by ion implantation in the first semiconductor layer 2, The first semiconductor layer 2 may be made amorphous. Thereby, the etching rate of the first semiconductor layer 2 can be increased, and the etching area of the first semiconductor layer 2 can be increased.

Next, as shown in FIG. 6, the buried insulating layer 8 is formed in the cavity 7 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. To do.
In the case where the buried insulating layer 8 is formed by thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3, it is preferable to use low-temperature wet oxidation that is reaction-controlled in order to improve the embeddability. At that time, the side wall of the second semiconductor layer 3 is also thermally oxidized. Further, after the buried insulating layer 8 is formed in the cavity 7, high-temperature annealing at 1100 ° C. or higher may be performed. Thereby, the buried insulating layer 8 can be reflowed, the stress of the buried insulating layer 8 can be relieved, and the interface state at the boundary with the second semiconductor layer 3 can be reduced. Further, the buried insulating layer 8 may be formed so as to fill the entire cavity 7 or may be formed so that a part of the cavity 7 remains.

  In the method of FIG. 6, the buried insulating layer 8 is formed in the cavity 7 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. The cavity portion between the semiconductor substrate 1 and the second semiconductor layer 3 is formed by forming an insulating film in the cavity portion 7 between the semiconductor substrate 1 and the second semiconductor layer 3 by the CVD method. 7 may be embedded in the embedded insulating layer 8. Thereby, it is possible to fill the cavity 7 between the semiconductor substrate 1 and the second semiconductor layer 3 with a material other than the oxide film while preventing the second semiconductor layer 3 from being reduced. Therefore, the dielectric constant of the buried insulating layer 8 disposed on the back surface side of the second semiconductor layer 3 can be lowered, and the parasitic capacitance on the back surface side of the second semiconductor layer 3 can be reduced.

  As the material of the buried insulating layer 8, for example, an FSG (fluorinated silicate glass) film or a silicon nitride film may be used in addition to the silicon oxide film. In addition to the SOG (Spin On Glass) film, the buried insulating layer 21 includes a PSG film, a BPSG film, a PAE (poly arylene ether) -based film, an HSQ (hydroxysilsesquioxane) -based film, an MSQ (methyl silsesquioxane Bane-based film). An organic lowk film such as a film, a CF-based film, a SiOC-based film, or a SiOF-based film, or a porous film thereof may be used.

  Next, as shown in FIG. 7, an oxide film 9 is deposited on the entire surface of the semiconductor substrate 1 by a method such as CVD. Then, CMP (chemical mechanical polishing) of the oxide film 9 is performed using the support layer 5 as a stopper, thereby planarizing the oxide film 9 so that the oxide film 9 is embedded around the second semiconductor layer 3. . Here, even when the second semiconductor layer 3 is covered with the oxide film 9 by using the support layer 5 as a stopper when performing the CMP of the oxide film 9, the oxide film 9 is replaced with the second semiconductor layer 3. It is possible to stably expose the surface of the second semiconductor layer 3 while being embedded in the periphery of the semiconductor layer 3.

Next, as shown in FIG. 8, the surface of the second semiconductor layer 3 is exposed by removing the support layer 5 on the second semiconductor layer 3. When the support layer 5 is removed, a part of the surface of the semiconductor substrate 1 with which the support layer 5 is in contact is also exposed.
Next, as shown in FIG. 9, the gate insulating film 10 is formed on the surface of the second semiconductor layer 3 by performing thermal oxidation of the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 10 is formed by a method such as CVD. Then, by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique, a gate electrode 11 disposed on the oxide film 9 is formed on the second semiconductor layer 3. Then, using the gate electrode 11 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, so that the source / drain layers 12 a and 12 b respectively disposed on the sides of the gate electrode 11 are formed. Formed on the second semiconductor layer 3.

  Here, even when the support layer 5 is removed by bringing the support layer 5 into contact with the semiconductor substrate 1 at the four corners of the second semiconductor layer 3, the semiconductor substrate extends over the entire side surface of the second semiconductor layer 3. 1 can be prevented from being exposed. For this reason, even when the gate electrode 11 is disposed along the longitudinal direction of the second semiconductor layer 3, the gate electrode 11 can be extended on the oxide film 9, and the semiconductor substrate 1 due to poor insulation of the gate electrode 11. In addition, it is possible to increase the gate width on the second semiconductor layer 3 while preventing the occurrence of leakage current to the source / drain layers 12a and 12b. As a result, an SOI transistor can be formed on the second semiconductor layer 3 without using an SOI substrate, so that the SOI transistor can be reduced in price and the current driving capability of the SOI transistor can be reduced. Can be secured.

In addition, by forming notches 4 that expose a part of the surface of the semiconductor substrate 1 at the four corners of the first semiconductor layer 2 and the second semiconductor layer 3, the pattern of the support layer 5 is used in a bulk semiconductor wafer. Therefore, the element region forming mask can be used as it is, and the replacement from the bulk structure to the SOI structure can be facilitated.
FIG. 10 is a perspective view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  In FIG. 10, a first semiconductor layer 22 and a second semiconductor layer 23 having an elongated shape are formed on a semiconductor substrate 21. In addition, notches 24 a that expose a part of the surface of the semiconductor substrate 1 are formed at the four corners of the first semiconductor layer 22 and the second semiconductor layer 23, and a notch that exposes a part of the surface of the semiconductor substrate 1. The part 24 b is formed on a part of the long sides of the first semiconductor layer 22 and the second semiconductor layer 23. A support layer 25 is formed on the second semiconductor layer 23 so as to be in contact with the semiconductor substrate 21 through the notches 24a and 24b. Then, an SOI transistor can be formed in the second semiconductor layer 23 through the same steps as those shown in FIGS.

  Thus, the support layer 25 is disposed on the second semiconductor layer 23 while the support layer 25 supporting the second semiconductor layer 23 is in contact with the semiconductor substrate 21 at a part on the long side of the second semiconductor layer 23. can do. For this reason, even when the shape of the second semiconductor layer 23 is elongated, it is possible to stably support the second semiconductor layer 23 on the semiconductor substrate 21 and from the long side of the first semiconductor layer 22. It is possible to prevent the etching solution from entering under the second semiconductor layer 23. In addition, an insulating film can be embedded around the second semiconductor layer 23 while using the support layer 25 as a stopper, and the surface of the second semiconductor layer 23 separated by STI (Shallow Trench Isolation) can be stabilized. And can be exposed. As a result, it is possible to form an SOI transistor on the second semiconductor layer 23 without using an SOI substrate, and it is possible to reduce the price of the SOI transistor and to reduce the semiconductor due to defective insulation of the gate electrode. The current drive capability of the SOI transistor can be ensured while preventing the occurrence of leakage current to the substrate and the source / drain layer.

1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. The perspective view which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  1, 21 Semiconductor substrate, 2, 22 First semiconductor layer, 3, 23 Second semiconductor layer, 4, 24a, 24b Notch, 5, 25 Support layer, 6 Exposed surface, 7 Cavity, 8 Embedded insulating layer , 9 Oxide film, 10 Gate insulating film, 11 Gate electrode, 12a Source layer, 12b Drain layer

Claims (4)

A semiconductor layer formed by epitaxial growth in a partial region on the semiconductor substrate;
A buried insulating layer buried between the semiconductor substrate and the semiconductor layer;
Notches formed at the four corners of the semiconductor layer;
A planarization film formed around the semiconductor layer so as to avoid the notch,
A gate electrode formed on the semiconductor layer so as to extend on the planarization film;
A source layer formed on the semiconductor layer and disposed on one side of the gate electrode;
A semiconductor device comprising: a drain layer formed on the semiconductor layer and disposed on the other side of the gate electrode. A semiconductor layer formed by epitaxial growth in a partial region on the semiconductor substrate;
A buried insulating layer buried between the semiconductor substrate and the semiconductor layer;
Notches formed in a part and four corners on the long side of the semiconductor layer;
A planarization film formed around the semiconductor layer so as to avoid the notch,
A gate electrode formed on the semiconductor layer so as to extend on the planarization film;
A source layer formed on the semiconductor layer and disposed on one side of the gate electrode;
A semiconductor device comprising: a drain layer formed on the semiconductor layer and disposed on the other side of the gate electrode. Forming a first semiconductor layer on a semiconductor substrate by epitaxial growth;
Forming a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer on the first semiconductor layer by epitaxial growth;
Forming notches at four corners of the first semiconductor layer and the second semiconductor layer;
Forming on the second semiconductor layer a support that contacts the semiconductor substrate via the notch,
Forming an exposed portion for exposing a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the exposed portion;
Forming a buried insulating layer buried in the cavity;
Depositing an insulating film on the entire surface of the semiconductor substrate on which the buried insulating layer is formed;
Flattening the insulating film by thinning the insulating film using the support as a stopper;
Removing the support after planarizing the insulating film and exposing a surface of the second semiconductor layer;
Forming a gate electrode on the second semiconductor layer so as to extend on the planarized insulating film;
Forming a source / drain layer arranged so as to sandwich the gate electrode in the second semiconductor layer. A method for manufacturing a semiconductor device, comprising: Forming a first semiconductor layer on a semiconductor substrate by epitaxial growth;
Forming a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer on the first semiconductor layer by epitaxial growth;
Forming a notch in a part and four corners on the long side of the first semiconductor layer and the second semiconductor layer;
Forming on the second semiconductor layer a support that contacts the semiconductor substrate via the notch,
Forming an exposed portion for exposing a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the exposed portion;
Forming a buried insulating layer buried in the cavity;
Depositing an insulating film on the entire surface of the semiconductor substrate on which the buried insulating layer is formed;
Flattening the insulating film by thinning the insulating film using the support as a stopper;
Removing the support after planarizing the insulating film and exposing a surface of the second semiconductor layer;
Forming a gate electrode in a long-side direction of the second semiconductor layer so as to extend on the planarized insulating film;
Forming a source / drain layer arranged so as to sandwich the gate electrode in the second semiconductor layer. A method for manufacturing a semiconductor device, comprising:

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