JP2009176856A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, in which a groove which may cause trouble is prevented from being formed when an SOI structure is partially formed on a semiconductor substrate. <P>SOLUTION: The method of manufacturing the semiconductor device includes steps of: forming an SiGe layer on the Si substrate 1; forming an Si layer 5 on the SiGe layer; etching the Si layer 5 and SiGe layer to form a support hole (h) penetrating the Si layer 5 and SiGe layer; forming a support 12 in the support hole (h); etching the Si layer 5 to form a groove H in which the SiGe layer is exposed ; etching the SiGe layer through the groove H to form a cavity between the Si layer 5 and Si substrate 1; forming an SiO<SB>2</SB>film 23 in the cavity; forming an Si film 31 in the groove H after forming the SiO<SB>2</SB>film 23; and thermally oxidizing the Si film 31. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming a so-called SOI (Silicon On Insulator) structure on a semiconductor substrate.

As a technique for forming an SOI structure on a bulk wafer, for example, there are methods disclosed in Patent Document 1 and Non-Patent Document 1. The methods disclosed in these documents are called SBSI methods, and are methods for partially forming an SOI structure on a bulk wafer. In the SBSI method, a Si / SiGe layer is formed on a bulk Si substrate, and only the SiGe layer is selectively removed using the difference in etching rate between Si and SiGe. A cavity is formed between the two. Next, as shown in FIG. 17A, the upper surface of the Si substrate 101 facing the inside of the cavity and the lower surface of the Si layer 103 are thermally oxidized to form SiO between the Si substrate 101 and the Si layer 103. _Two films (that is, a BOX layer) 111 are formed. Then, as shown in FIG. 17B, a thick SiO ₂ film 113 is formed on the Si substrate 101, and a region where the SOI structure is not formed (that is, an element isolation region) is buried. The formation of the SiO ₂ film 113 is performed by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 17C, the SiO ₂ film 113 is planarized by a CMP (Chemical Mechanical Polish) process, and further etched with a dilute hydrofluoric acid solution or the like. As a result, as shown in FIG. 17D, the surface of the Si layer 103 (that is, the SOI layer) is exposed, and an element isolation layer made of the SiO ₂ film 113 and the like is formed around the Si layer 103.
JP 2005-354024 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

As shown in FIGS. 17B and 17C, the element isolation layer is formed by the formation of the SiO ₂ film 113 and the subsequent CMP process, and the surface of the Si layer 103 is removed after the CMP process. In order to expose (or in subsequent cleaning), it is necessary to perform wet treatment with a diluted hydrofluoric acid solution or the like. At this time, as shown in FIG. 17 (d), a portion of the SiO ₂ film 113 along the outer peripheral portion of the Si layer 103 (that is, a boundary portion with the Si layer 103) is etched deeper than intended to form a groove. There was a problem that 121 was easily made. The cause of the problem, by forming the SiO ₂ film 113 by CVD, nest the portion to be formed along the step between the Si substrate 101 and the Si layer 103 (i.e., voids) easily enters is the SiO ₂ film 113 This is probably because the strength is weaker than other parts.

For example, when the trench 121 is formed, as shown in FIG. 17E, a polysilicon (poly-Si) film 131 that becomes a material of the gate electrode is deposited also in the trench 121 in a process of forming a transistor later. To do. Then, when this poly-Si film 131 is patterned, there is a possibility that the poly-Si film 131 in the trench 121 remains on the Si substrate 101 while being connected to the gate electrode. As described above, if the poly-Si film 131 that should not remain is left on the Si substrate 101 in a state of being connected to the gate electrode, for example, parasitic capacitance is generated in the gate electrode, and the operation speed of the transistor is reduced. The power consumption may increase. Further, the electric field is concentrated between the poly-Si film 131 in the groove 121 and the Si substrate 101, and there is a possibility that dielectric breakdown may occur between the poly-Si film 131 and the Si substrate 101.
Accordingly, the present invention has been made in view of such circumstances, and a semiconductor device capable of preventing formation of a groove that causes a failure when an SOI structure is partially formed on a semiconductor substrate. It aims at providing the manufacturing method of this.

  [Invention 1 and 2] In order to solve the above problems, a manufacturing method of a semiconductor device of Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer on the first semiconductor layer. Forming the first groove, etching the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer, and supporting the first groove Forming a body, etching the second semiconductor layer to form a second groove exposing the first semiconductor layer, and etching the first semiconductor layer through the second groove. Thus, after the step of forming a cavity between the second semiconductor layer and the semiconductor substrate, the step of forming an insulating film in the cavity, and the step of forming the insulating film, the second groove Forming a semiconductor film on the substrate, and thermally oxidizing the semiconductor film It is characterized in that comprises a step.

Here, the “semiconductor substrate” of the present invention is, for example, a bulk silicon (Si) substrate, the “first semiconductor layer” is, for example, a monocrystalline silicon germanium (SiGe) layer, and the “second semiconductor layer” is, for example, It is a single crystal Si layer. The SiGe layer and the Si layer having a single crystal structure can be formed by, for example, an epitaxial growth method. The “support” of the present invention is made of an insulating film such as a silicon oxide (SiO ₂ ) film or a silicon nitride (SiN) film. Furthermore, the “semiconductor film” of the present invention is, for example, an amorphous silicon (a-Si) film or a polysilicon (Poly-Si) film.

The method for manufacturing a semiconductor device according to a second aspect of the invention is the method for manufacturing a semiconductor device according to the first aspect, wherein the step of forming the semiconductor film in the second groove includes the step of forming the semiconductor film over the entire semiconductor substrate, Performing a CMP process on the semiconductor film to remove the semiconductor film from the second semiconductor layer.
According to the method for manufacturing a semiconductor device of the first and second aspects, the oxide film formed in the second groove can be formed by thermal oxidation of the semiconductor film. An oxide film formed by thermal oxidation of a semiconductor film has higher strength than an oxide film formed by a CVD method. Accordingly, when the oxide film is subjected to, for example, a CMP process or a wet process, a portion of the oxide film along the outer periphery of the second semiconductor layer (that is, a boundary portion with the second semiconductor layer) is excessively etched. It can prevent that a groove | channel is formed along a boundary part.

[Invention 3] The manufacturing method of a semiconductor device of Invention 3 includes the step of forming an antioxidant film on the second semiconductor layer before the step of forming the semiconductor film in the manufacturing method of the semiconductor device of Invention 2. Furthermore, it is characterized by including. Here, the “antioxidation film” of the present invention is, for example, a SiN film. The SiN film is an insulating film excellent in oxidation resistance.
According to the method of manufacturing a semiconductor device of the third aspect, since the second semiconductor layer is covered with the antioxidant film when the semiconductor film is thermally oxidized, the oxidation of the second semiconductor layer can be prevented.

  [Invention 4] The method for manufacturing a semiconductor device according to Invention 4 is the method for manufacturing a semiconductor device according to Invention 3, wherein the semiconductor film is subjected to CMP treatment to remove the semiconductor film from the second semiconductor layer. An antioxidant film is used as a stopper for CMP treatment. According to the method for manufacturing a semiconductor device of the fourth aspect, the polishing pad can be prevented from coming into contact with the second semiconductor layer. Thereby, it can contribute to prevention of the occurrence of crystal defects or the like in the second semiconductor layer.

[Invention 5] The manufacturing method of a semiconductor device of Invention 5 includes a step of forming a first semiconductor layer on a semiconductor substrate, a step of forming a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer. And etching the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer; forming a support in the first groove; and the second semiconductor Etching a layer to form a second groove exposing the first semiconductor layer; and etching the first semiconductor layer through the second groove to thereby form the second semiconductor layer and the semiconductor substrate. A step of forming a cavity between the semiconductor substrate, a step of forming an insulating film in the cavity, and a step of forming the semiconductor film over the semiconductor substrate after the step of forming the insulating film, A step of thermally oxidizing the semiconductor film; And a step of subjecting the oxide film formed by thermal oxidation of the conductor film to a CMP process to remove the oxide film from the second semiconductor layer.
According to the semiconductor device manufacturing method of the fifth aspect of the invention, the same effects as those of the semiconductor device manufacturing method of the first aspect of the invention can be obtained. That is, when the oxide film is subjected to CMP treatment or wet treatment, a portion of the oxide film along the outer periphery of the second semiconductor layer (that is, a boundary portion with the second semiconductor layer) is excessively etched. It can prevent that a groove | channel is formed along a boundary part.

[Invention 6] A method for manufacturing a semiconductor device according to Invention 6 is the method for manufacturing a semiconductor device according to Invention 5, wherein the step of forming the semiconductor film and the step of thermally oxidizing the semiconductor film are repeated in this order. It is a feature. According to the semiconductor device manufacturing method of the invention 6, it is easy to form the oxide film thicker than the semiconductor device manufacturing method of the invention 5.
[Invention 7] A method for manufacturing a semiconductor device according to Invention 7 is the method for manufacturing a semiconductor device according to Inventions 1 to 6, wherein the surface of the second semiconductor layer is exposed, and a gate insulating film is interposed on the second semiconductor layer. And forming a gate electrode by etching the conductive film. In the step of forming the gate electrode, an oxide film formed by thermal oxidation of the semiconductor film is formed. The gate electrode is arranged so that a portion along the outer peripheral portion of the second semiconductor layer and the gate electrode intersect in plan view.
According to the method of manufacturing the semiconductor device of the invention 7, since the formation of a trench which has been problematic in the prior art can be prevented, the operation speed of the transistor due to this trench, the increase in the power consumption of the transistor, the dielectric breakdown And other problems can be prevented.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(1) First Embodiment FIGS. 1 to 14 are views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. 1 to 14, (a) is a plan view, (b) is a sectional view when (a) is cut along line X1-X′1 to X14-X′14, and (c) is (a). Is a sectional view taken along line Y1-Y′1 to Y14-Y′14.

First, in FIGS. 1A to 1C, a silicon buffer (Si-buffer) layer 2 is formed on a silicon (Si) substrate 1, and a single crystal silicon germanium (SiGe) layer 3 is formed thereon. A single crystal Si layer 5 is sequentially stacked. The Si-buffer layer 2, the SiGe layer 3, and the Si layer 5 are successively formed by, for example, an epitaxial growth method. Next, the Si layer 5 is thermally oxidized to form a silicon oxide (SiO ₂ ) film 7 on the surface, and a silicon nitride (SiN) film 9 is formed on the entire surface of the SiO ₂ film 7 by CVD. . The SiN film 9 functions as an antioxidant film for preventing oxidation of the surface of the Si layer 5 and also functions as a stopper layer when performing a CMP process in a later process. The method for forming the SiO ₂ film 7 covering the Si layer 5 is not limited to thermal oxidation, and may be formed by, for example, a CVD method.

Next, as shown in FIGS. 2A to 2C, the SiN film 9 and the SiO _{2 in the} region overlapping the element isolation region (that is, the region where the SOI structure is not formed) in plan view by photolithography and etching techniques. The film 7, the Si layer 5, the SiGe layer 3, and the Si-buffer layer 2 are partially etched sequentially. As a result, a support hole h having the Si substrate 1 as a bottom surface is formed through the Si layer 5 and the SiGe layer 3. In the etching step for forming the support hole h, the etching may be stopped on the surface of the Si substrate 1 as shown in FIG. 2B, or the Si substrate 1 is over-etched to form a recess. You may do it.

Next, as shown in FIGS. 3A to 3C, a support film 11 is formed on the entire upper surface of the Si substrate 1 so as to fill the support hole h. Then, as shown in FIGS. 4A to 4C, the support film in the region overlapping the element isolation region in plan view is partially etched by photolithography and etching techniques. Thereby, the support 12 is formed from the support film. Subsequently, as shown in FIGS. 5A to 5C, the SiN film 9, the SiO ₂ film 7, the Si layer 5, the SiGe layer 3, and the Si-buffer layer 2 exposed from below the support 12 are sequentially formed. Etch partially. As a result, a groove H is formed with the Si substrate 1 as the bottom surface and exposing the side surfaces of the Si layer 5 and the SiGe layer 3. Here, the groove H is used as an inlet for an etching solution when the SiGe layer 3 is etched in a later step.

  In the etching step for forming the groove H, the etching may be stopped with a part of the SiGe layer 3 left in the region where the groove H is formed, or the groove H may be formed as shown in FIG. Etching may be stopped at the surface of the Si substrate 1 in the region to be formed, or the Si substrate 1 may be over-etched to form a recess. In this etching step, since the surface of the Si substrate 1 exposed at the bottom surface of the support hole is also etched, a recess is formed in a part of the bottom surface of the support hole h as shown in FIG. It is formed. In FIG. 5A, a rectangular region surrounded by the support hole h and the groove H in plan view is an element region (that is, a region for forming an SOI structure).

  Next, for example, a hydrofluoric acid solution is brought into contact with the side surfaces of the Si layer 5 and the SiGe layer 3 through the groove H, and the SiGe layer 3 is selectively etched and removed. Thereby, as shown in FIGS. 6A to 6C, a cavity 21 is formed between the Si layer 5 and the Si-buffer layer 2. In wet etching using a fluorinated nitric acid solution, the etching rate of SiGe is higher than that of Si (that is, the etching selectivity of SiGe is higher than that of Si). It is possible to etch away only the SiGe layer 3 while leaving it on. During the formation of the cavity 21, the upper surface and the side surface of the Si layer 5 are supported by the support 12 and the like.

Next, as shown in FIGS. 7A to 7C, the Si substrate 1, the Si-buffer layer 2 and the Si layer 5 are thermally oxidized to form an SiO ₂ film (that is, a BOX layer) 23 in the cavity. Form. This step is thermally oxidized, with SiO ₂ film 23a from the upper surface of the Si-buffer layer 2 toward the cavity grows, the SiO ₂ film 23b is grown from the lower surface of the Si layer 5 toward the cavity. The SiO ₂ films 23a and 23b grown from above and below are in close contact with each other in the vicinity of the center in the height direction inside the cavity.

Next, as shown in FIGS. 8A to 8C, for example, a Si film 31 is formed on the entire upper surface of the Si substrate 1 by a method such as CVD to bury the grooves H and the like. Here, the Si film 31 is, for example, amorphous silicon (a-Si) or polysilicon (poly-Si). This Si film 31 changes its composition into a SiO ₂ film in the thermal oxidation step shown in FIG. 11, and serves as a part of the element isolation layer. Further, in FIG. 8 (b) and (c), if it illustrates the case where there remains no gap between the SiO ₂ film 23a and 23b, which are tentatively remaining gap between the SiO ₂ film 23a and 23b The Si film 31 may enter the gap and serve as an adhesive.

  Next, the Si film 31 and the underlying support 12 are flattened by performing, for example, a CMP process. Thus, as shown in FIGS. 9A to 9C, the Si film 31 and the support 12 are removed from the Si layer 5, and the surface of the SiN film 9 on the Si layer 5 is exposed. In the above CMP process, the SiN film 9 can function as a stopper for the CMP process, and the polishing pad can be prevented from coming into contact with the Si layer 5. Thereby, generation | occurrence | production of a crystal defect etc. in the Si layer 5 can be prevented. As shown in FIGS. 9A to 9C, after the CMP process, the Si film 31 is left only in the groove H and a part of the support hole h.

Next, as shown in FIGS. 10A to 10C, the Si film 31 left in the groove H and the support hole h is etched, and the height of the surface is set to the height of the surface of the Si layer 5, for example. And almost the same. This is for shortening the thermal oxidation time necessary for leaving no Si film 31 at the bottom of the trench H as much as possible. Another reason is to prevent the step between the Si layer 5 and the surrounding thermal oxide film from becoming too large when the gate electrode is formed later. Since the thickness of the Si film 31 is reduced by etching, the required time can be shortened in the thermal oxidation step shown in FIG. Note that the etching step shown in FIG. 10 is preferably performed by dry etching having a large etching selectivity ratio of Si to SiO ₂ or SiN. By performing such dry etching, for example, without a resist mask, the Si film 31 can be selectively removed.

Next, as shown in FIGS. 11A to 11C, the Si film is thermally oxidized to change the composition of the Si film into the SiO ₂ film 32. That is, the SiO ₂ film 32 is formed from the Si film by thermal oxidation. At this time, since the Si layer 5 is covered with the SiN film 9 excellent in oxidation resistance, the oxidation of the Si layer 5 can be prevented. After thermal oxidation, the Si layer 5 is surrounded by the SiO ₂ film 31 and the support 12 in plan view, and the SiO ₂ film 31 and the support 12 serve as an element isolation layer. In FIG. 11B, the Si film 31 remains on a part of the bottom surface of the support hole h. The remaining Si film 31 is separated from the Si layer 5 by the SiO ₂ films 23 and 32. There is no problem because it is electrically independent. Therefore, the Si film 31 may or may not remain on a part of the bottom surface of the support hole h.

Next, the SiN film 9 exposed from under the support is wet-etched and removed using, for example, a hot phosphoric acid solution. This exposes the surface of the SiO ₂ film 7 on the Si layer 5 as shown in FIGS. Further, the SiO ₂ film 7 is removed by wet etching using, for example, a diluted hydrofluoric acid solution.
As a result, as shown in FIGS. 13A to 13C, the surface of the Si layer 5 (that is, the SOI layer) is exposed, and the SOI structure including the BOX layer 23 and the SOI layer 5 is completed on the Si substrate 1. To do.

When the support 12 is SiO ₂ formed by the CVD method, the support 12 is also slightly etched in the wet etching process using this diluted hydrofluoric acid solution. As a result, for example, as shown in FIG. 13B, there is a possibility that the corner 12 of the support 12 is slightly cut to form a curved recess 12 ′, which is a process of forming the gate electrode shown in FIG. There is a possibility that a conductive film (for example, a poly-Si film) as the material remains in the recess 12 '. However, even if the conductive film remains in the recess 12 ', the conductive film remaining in the recess 12' and the gate electrode are electrically independent if the gate electrode is disposed so as not to straddle the recess 12 '. So there is no problem. Therefore, the recess 12 ′ may or may not be formed at the corner of the support 12.

Next, for example, a MOS transistor is formed in the SOI layer having the completed SOI structure. That is, as shown in FIGS. 14A to 14C, the gate insulating film 51 is formed on the surface of the Si layer 5. The gate insulating film 51 is, for example, a silicon oxide film (SiO ₂ ) or silicon oxynitride film (SiON) formed by thermal oxidation, or a High-k material film. Next, a conductive film serving as a material for the gate electrode is formed over the entire Si substrate 1 on which the gate insulating film 51 is formed. This conductive film is, for example, a poly-Si film, and is formed by, for example, a CVD method. Here, for example, impurities are introduced into the poly-Si film by ion implantation, in-situ, or the like, so that the poly-Si film has conductivity.

Next, the polysilicon film is partially etched by photolithography technique and etching technique to form the gate electrode 53. As shown in FIGS. 14A to 14C, in the step of forming the gate electrode 53, a portion along the outer peripheral portion of the Si layer 5 in the SiO ₂ film 32 (that is, a boundary portion with the Si layer 5). ) The gate electrode 53 is arranged so that 32 'and the gate electrode 53 intersect in plan view. That is, the gate electrode 53 is disposed so as not to straddle the dent 12 ′ formed at the corner of the support 12.

  Thereafter, impurities are ion-implanted into the Si layer 5 using the gate electrode 53 as a mask, and heat treatment is performed to form a source or drain (hereinafter referred to as S / D layer) 55 in the Si layer 5 on both sides of the gate electrode 53. . Next, an interlayer insulating film (not shown) is formed over the entire upper surface of the Si substrate 1, and the interlayer insulating film is partially etched to form a first contact hole (not shown) having the gate electrode 53 as a bottom surface. And a second contact hole (not shown) having the S / D layer 55 as a bottom surface. Then, an Al wiring or a plug electrode is formed inside these contact holes. Thereby, the gate electrode 53 and the S / D layer 55 are drawn on the interlayer insulating film, and the MOS transistor is completed.

Thus, according to the first embodiment of the present invention, the SiO ₂ film 32 formed in the trench H is formed by thermal oxidation of the Si film 31. The SiO ₂ film 32 formed by thermal oxidation of the Si film 31 has a higher strength than the SiO ₂ film formed by the CVD method. Accordingly, when the SiO ₂ film 32 is subjected to, for example, a CMP process or a wet process, a portion of the SiO ₂ film 32 along the outer periphery of the Si layer 5 (that is, a boundary portion with the Si layer 5) 32 ′. Can be prevented from being etched excessively, and a groove can be prevented from being formed along the boundary portion 32 '. As a result, it is possible to prevent problems such as a decrease in the operation speed of the transistor, an increase in power consumption of the transistor, and dielectric breakdown due to the groove.

(2) Second Embodiment In the first embodiment described above, the Si film 31 is formed on the entire upper surface of the Si substrate 1 in the step of FIG. 8 to fill the groove H, and then the Si film 31 in the step of FIG. In the above description, the CMP process is performed, and then the Si film 31 left in the trench H and the like is thermally oxidized to form the SiO ₂ film 32. However, the method of forming the SiO ₂ film 32 is not limited to this.

15A and 15B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 15 (a) and 15 (b), parts having the same configurations as those in FIGS. 1 to 14 are denoted by the same reference numerals, and detailed description thereof is omitted.
For example, as shown in FIG. 15 (a), after forming a Si film 31 on the entire upper part of the Si substrate 1, as shown in FIG. 15 (b), SiO ₂ film 32 by a Si film 31 is thermally oxidized Form. Thereafter, the SiO ₂ film 32 and the underlying support 12 may be flattened by performing a CMP process. Even in such a method, the SiO ₂ film 32 is formed by thermal oxidation of the Si film 31, and therefore, along the outer peripheral portion of the Si layer 5 in the SiO ₂ film 32 as in the first embodiment. The portion (that is, the boundary portion with the Si layer 5) can be prevented from being excessively etched, and the formation of a groove along the boundary portion can be prevented. As a result, it is possible to prevent problems such as a decrease in the operation speed of the transistor, an increase in power consumption of the transistor, and dielectric breakdown due to the groove.
Also, in the CMP process for the SiO ₂ film 32 and the like, as in the first embodiment, the SiN film 9 can function as a stopper for the CMP process, and the polishing pad can be prevented from coming into contact with the Si layer 5. Can do. Therefore, as in the first embodiment, it is possible to prevent the occurrence of crystal defects and the like in the Si layer 5.

(3) Third Embodiment Furthermore, in the second embodiment, the Si film 31 deposition step and the Si film 31 thermal oxidation step may be repeated in this order.
16A to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention. 16A and 16D, parts having the same configurations as those in FIGS. 1 to 14 and 15 are denoted by the same reference numerals, and detailed description thereof is omitted.

For example, as shown in FIG. 16A, after the first Si film 31a is thinly formed on the entire upper surface of the Si substrate 1, the first Si film is thermally oxidized as shown in FIG. Then, the first SiO ₂ film 32a is thinly formed. Next, as shown in FIG. 16C, after the second Si film 31b is thinly formed on the SiO ₂ film 32a, the second Si film is thermally oxidized as shown in FIG. Then, the second SiO ₂ film 32b is formed thin. Thus, repeated Si film 31a, 31b, ... and a deposition process of a thermal oxidation process, and finally, the SiO ₂ film 32a, 32b, so as to form the SiO ₂ film 32 made of ... Also good. If it is such a method, the effect similar to 1st, 2nd embodiment can be acquired.

Further, since each of the Si films 31a, 31b,... Is thinner than the Si film 31 as compared with the second embodiment, each of the Si films 31a, 31b,. it can. Thereby, it becomes easy to form the SiO ₂ film 32 thick.
In the first to third embodiments, the Si substrate 1 corresponds to the “semiconductor substrate” of the invention, the SiGe layer 3 corresponds to the “first semiconductor layer” of the invention, and the Si layer 5 corresponds to the “semiconductor substrate” of the invention. This corresponds to the “second semiconductor layer”. The support hole h corresponds to the “first groove” of the present invention, and the groove H corresponds to the “second groove” of the present invention. Further, the SiN film 9 corresponds to the “antioxidation film” of the present invention, and the SiO ₂ film 23 corresponds to the “insulating film” of the present invention. The Si films 31, 31a, 31b correspond to the “semiconductor film” of the present invention, and the SiO ₂ films 32, 32a, 32b correspond to the “oxide film” of the present invention.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). FIG. 6 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 13 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 13). FIG. 14 is a view (No. 14) illustrating the method for manufacturing the semiconductor device according to the first embodiment; The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 6 is a view showing a method for manufacturing a semiconductor device according to a third embodiment. The figure which shows a prior art example and its problem.

Explanation of symbols

1 Si substrate, 2 Si-buffer layer, 3 SiGe layer, 5 Si layer (SOI layer), 7 SiO ₂ film, 9 SiN film, 11 support film, 12 support body, 12 ′ recess, 21 cavity part, 23, 23a, 23b SiO ₂ film (BOX layer), 31, 31a, 31b Si film, 32, 32a, 32b (formed by thermal oxidation of Si film) SiO ₂ film, 32 ′ (with Si layer 5) 51 gate insulating film, 53 gate electrode, 55 S / D layer, h support hole, H groove

Claims (7)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Etching the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer;
Forming a support in the first groove;
Etching the second semiconductor layer to form a second groove exposing the first semiconductor layer;
Etching the first semiconductor layer through the second groove to form a cavity between the second semiconductor layer and the semiconductor substrate;
Forming an insulating film in the cavity;
After the step of forming the insulating film, forming a semiconductor film in the second groove;
And a step of thermally oxidizing the semiconductor film. Forming a semiconductor film in the second groove,
Forming the semiconductor film over the semiconductor substrate; and
The method for manufacturing a semiconductor device according to claim 1, further comprising: performing a CMP process on the semiconductor film to remove the semiconductor film from the second semiconductor layer. Before the step of forming the semiconductor film,
The method for manufacturing a semiconductor device according to claim 2, further comprising a step of forming an antioxidant film on the second semiconductor layer.   4. The semiconductor device according to claim 3, wherein in the step of subjecting the semiconductor film to a CMP process to remove the semiconductor film from the second semiconductor layer, the antioxidant film is used as a stopper for the CMP process. Production method. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Etching the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer;
Forming a support in the first groove;
Etching the second semiconductor layer to form a second groove exposing the first semiconductor layer;
Etching the first semiconductor layer through the second groove to form a cavity between the second semiconductor layer and the semiconductor substrate;
Forming an insulating film in the cavity;
After the step of forming the insulating film,
Forming the semiconductor film over the semiconductor substrate; and
Thermally oxidizing the semiconductor film;
And a step of subjecting the oxide film formed by thermal oxidation of the semiconductor film to a CMP process to remove the oxide film from the second semiconductor layer.   6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the semiconductor film and the step of thermally oxidizing the semiconductor film are repeated in this order. Exposing the surface of the second semiconductor layer and forming a conductive film on the second semiconductor layer through a gate insulating film;
Etching the conductive film to form a gate electrode, and
In the step of forming the gate electrode,
The gate electrode is arranged such that a portion of the oxide film formed by thermal oxidation of the semiconductor film along the outer periphery of the second semiconductor layer intersects the gate electrode in plan view. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

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