JP4696640B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a field effect transistor formed on an SOI (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at a low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in selectivity between Si and SiGe. A cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.
JP 2002-299951 A JP, 2000-124092, A Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International GiGe Technology and Meeting Abstracts, pp. 230-231, May (2004)

  However, in order to manufacture a SIMOX substrate, it is necessary to ion-implant high concentration oxygen into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

Also, in ion implantation and polishing, the variation in the thickness of the SOI layer is large, and it is difficult to stabilize the characteristics of the field effect transistor when the SOI layer is thinned in order to produce a fully depleted SOI transistor. There was a problem.
On the other hand, in the method disclosed in Non-Patent Document 1, it is necessary to secure a region around the Si layer for supporting the Si layer on the Si substrate when the SiGe layer is removed. For this reason, there is a problem that the area of a useless portion that cannot be used as an active region is increased, which hinders integration of transistors.

  In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can expand the layout area of a semiconductor layer formed over an insulator without using an SOI substrate.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a first semiconductor layer over a semiconductor substrate, and a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are included in the first semiconductor. Forming on the layer, forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate, and filling the second semiconductor in the first groove Forming a support for supporting a layer on the semiconductor substrate; and forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer. And a step of selectively etching the first semiconductor layer through the second groove to form a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer. And embedded in the cavity Forming a buried insulating layer, forming a buried insulator embedded in the second groove, before embedding the support in said first groove, a first of said first groove A step of forming a cap oxide film on the side walls of the semiconductor layer and the second semiconductor layer and then forming an oxide film at an interface between the side wall and the cap oxide film by a thermal oxidation method is provided.
Thus, the second semiconductor layer can be supported on the semiconductor substrate via the support formed in the element isolation region, and the first semiconductor below the second semiconductor layer via the second groove. An etching gas or an etching solution can be brought into contact with the layer. Therefore, it is possible to stably support the second semiconductor layer on the semiconductor substrate without securing a support for supporting the second semiconductor layer on the semiconductor substrate in the active region, and the first semiconductor layer. Even when the second semiconductor layer is stacked on the first semiconductor layer, the first semiconductor layer between the second semiconductor layer and the semiconductor substrate can be removed. As a result, without damaging the quality of the second semiconductor layer,
Insulation between the second semiconductor layer and the semiconductor substrate can be achieved, and the second semiconductor layer
The area of useless parts that cannot be used as active areas can be reduced on the insulator.
The layout area of the second semiconductor layer formed on the substrate can be increased.
This also makes it possible to embed the support in the first groove after the sidewall of the first semiconductor layer is covered with the cap oxide film. For this reason, it can suppress that the component contained in a 1st semiconductor layer diffuses outward, and can suppress that the circumference | surroundings are contaminated with the component contained in a 1st semiconductor layer.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a first semiconductor layer over a semiconductor substrate, and a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are included in the first semiconductor. Forming on the layer, forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate, and filling the second semiconductor in the first groove Forming a support for supporting a layer on the semiconductor substrate; and forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer. And a step of selectively etching the first semiconductor layer through the second groove to form a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer. And embedded in the cavity Forming a buried insulating layer, forming a buried insulator buried in the second groove, and first filling the first groove in the first groove before embedding a support in the first groove. Forming a semiconductor film on sidewalls of the semiconductor layer and the second semiconductor layer; and thermally oxidizing the semiconductor film and thermally oxidizing a part of the first semiconductor layer and the second semiconductor layer. And
Thus, the second semiconductor layer can be supported on the semiconductor substrate via the support formed in the element isolation region, and the first semiconductor below the second semiconductor layer via the second groove. An etching gas or an etching solution can be brought into contact with the layer. Therefore, it is possible to stably support the second semiconductor layer on the semiconductor substrate without securing a support for supporting the second semiconductor layer on the semiconductor substrate in the active region, and the first semiconductor layer. Even when the second semiconductor layer is stacked on the first semiconductor layer, the first semiconductor layer between the second semiconductor layer and the semiconductor substrate can be removed. As a result, without damaging the quality of the second semiconductor layer,
Insulation between the second semiconductor layer and the semiconductor substrate can be achieved, and an area of a useless portion that cannot be used as an active region of the second semiconductor layer can be reduced, so that the second semiconductor layer is formed on the insulator. The layout area of the second semiconductor layer can be increased.
This also makes it possible to form a semiconductor / oxide film interface with few interface states on the sidewall of the second semiconductor layer while suppressing outward diffusion of components contained in the first semiconductor layer. At the same time, it is possible to prevent the surroundings from being contaminated by components contained in the first semiconductor layer.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming on the first semiconductor layer, forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate, and covering the second semiconductor layer Forming a support embedded in the first groove and supporting the second semiconductor layer on the semiconductor substrate; and connecting at least a part of the first semiconductor layer to the second groove,
Forming a second groove exposed from the semiconductor layer and the support; and selectively etching the first semiconductor layer through the second groove to form a cavity from which the first semiconductor layer has been removed. Forming between the semiconductor substrate and the second semiconductor layer, forming a buried insulating layer buried in the cavity, and filling the second groove so as to cover the support. A step of forming a buried insulator, a step of exposing the surface of the second semiconductor layer by thinning the buried insulator and the support, and a step of embedding the support in the first groove. And forming a cap oxide film on the sidewalls of the first semiconductor layer and the second semiconductor layer in the first groove and then forming an oxide film at the interface between the sidewall and the cap oxide film by a thermal oxidation method. Features.
As a result, it is possible to stably support the second semiconductor layer on the semiconductor substrate without securing a support for supporting the second semiconductor layer on the semiconductor substrate in the active region, and in the first groove. The embedded support and the embedded insulator embedded in the second groove can be thinned at once. For this reason, it is possible to form an SOI transistor on the second semiconductor layer without using an SOI substrate, it is possible to reduce the cost of the SOI transistor, and simplify the element isolation process, The layout area of the SOI transistor can be increased.
This also makes it possible to embed the support in the first groove after the sidewall of the first semiconductor layer is covered with the cap oxide film. For this reason, it can suppress that the component contained in a 1st semiconductor layer diffuses outward, and can suppress that the circumference | surroundings are contaminated with the component contained in a 1st semiconductor layer.

In addition, according to the method of manufacturing a semiconductor device according to one aspect of the present invention, the first semiconductor is formed on the semiconductor substrate.
Forming a body layer and a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer
Forming on the first semiconductor layer, and penetrating the first semiconductor layer and the second semiconductor layer.
Forming a first groove exposing the semiconductor substrate, and covering the second semiconductor layer
A support body embedded in the first groove and supporting the second semiconductor layer on the semiconductor substrate.
A step of forming the first semiconductor layer, the second semiconductor layer being connected to the first groove,
Forming a second groove exposed from the semiconductor layer and the support; and via the second groove
A cavity from which the first semiconductor layer is removed by selectively etching the first semiconductor layer
Forming a portion between the semiconductor substrate and the second semiconductor layer, and embedding in the cavity
Forming a buried buried insulating layer, and covering the support in the second groove
A step of forming a buried insulator, and the buried insulator and the support
The step of exposing the surface of the second semiconductor layer by thinning, and before embedding the support in the first groove, on the side walls of the first semiconductor layer and the second semiconductor layer in the first groove The method includes a step of forming a semiconductor film, a step of thermally oxidizing the semiconductor film, and a step of thermally oxidizing a part of the first semiconductor layer and the second semiconductor layer .
As a result, it is possible to stably support the second semiconductor layer on the semiconductor substrate without securing a support for supporting the second semiconductor layer on the semiconductor substrate in the active region, and in the first groove. The embedded support and the embedded insulator embedded in the second groove can be thinned at once. For this reason, it is possible to form an SOI transistor on the second semiconductor layer without using an SOI substrate, it is possible to reduce the cost of the SOI transistor, and simplify the element isolation process, The layout area of the SOI transistor can be increased.
This also makes it possible to form a semiconductor / oxide film interface with few interface states on the sidewall of the second semiconductor layer while suppressing outward diffusion of components contained in the first semiconductor layer. At the same time, it is possible to prevent the surroundings from being contaminated by components contained in the first semiconductor layer.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second semiconductor layer are single crystal Si, and the first semiconductor layer is single crystal SiGe.
As a result, it is possible to increase the etching rate of the first semiconductor layer compared to the semiconductor substrate and the second semiconductor layer while allowing lattice matching between the semiconductor substrate, the second semiconductor layer, and the first semiconductor layer. . For this reason, it becomes possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and insulation between the second semiconductor layer and the semiconductor substrate is achieved without impairing the quality of the second semiconductor layer. It becomes possible.

In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the end portion of the second groove is terminated with the support.
Thereby, a 2nd groove | channel can be formed, without removing a support body. For this reason, even when the etching rates between the second semiconductor layer and the first semiconductor layer and the support are different, the etching process at the time of forming the second groove can be proceeded without hindrance, and the manufacturing process becomes complicated. While suppressing, element isolation of the second semiconductor layer can be performed.

The method for manufacturing a semiconductor device according to one aspect of the present invention further includes a step of forming an insulating film on a surface of the second semiconductor layer before forming the first groove. .
As a result, it is possible to proceed with subsequent steps while protecting the surface of the second semiconductor layer, and to prevent damage to the second semiconductor layer.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the insulating film includes at least a silicon nitride film.

Thereby, even when the buried insulating layer is formed in the cavity by thermal oxidation of the semiconductor substrate and the second semiconductor layer, it is possible to prevent the surface of the second semiconductor layer from being thermally oxidized. For this reason, it is possible to dispose the second semiconductor layer on the buried insulating layer while reducing the film loss of the second semiconductor layer.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a support is formed over the insulating film, and the film thickness is 400 nm or more.

As a result, in the process of removing the first semiconductor layer by etching, the second semiconductor layer can be supported with a strong support while maintaining its flatness, and the thickness uniformity of the buried oxide film can be improved. This contributes to the expansion of the area .

Also, according to the method of manufacturing a semiconductor device according to an embodiment of the present invention, after forming the cap oxide film in said first groove, a portion of the first semiconductor layer and the second semiconductor layer is thermally oxidized The method further includes a step.

Thus, after the cap oxide film is formed, thermal oxidation is performed to suppress outward diffusion of components contained in the first semiconductor layer, and at least the interface state at the side wall of the second semiconductor layer. Fewer semiconductor / oxide film interfaces can be formed. At the same time, it is possible to prevent the surroundings from being contaminated by components contained in the first semiconductor layer .

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
1A to FIG. 8A are plan views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B to FIG. 8B are FIG. Sectional views cut along lines A1-A1 ′ to A8-A8 ′ in FIG. 8 (a), and FIGS. 1 (c) to 8 (c) show B1 in FIGS. 1 (a) to 8 (a). It is sectional drawing cut | disconnected by the -B1'-B8-B8 'line | wire, respectively.

  In FIG. 1, a first semiconductor layer 2 is formed on a semiconductor substrate 1 by epitaxial growth, and a second semiconductor layer 3 is formed on the first semiconductor layer 2 by epitaxial growth. The first semiconductor layer 2 can be made of a material having an etching rate larger than that of the semiconductor substrate 1 and the second semiconductor layer 3, and the material of the semiconductor substrate 1, the first semiconductor layer 2 and the second semiconductor layer 3 can be used. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. As the first semiconductor layer 2, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used in addition to the single crystal semiconductor layer. Instead of the first semiconductor layer 2, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 10-200 nm, for example.

Then, a sacrificial oxide film 4 is formed on the surface of the second semiconductor layer 3 by thermal oxidation of the second semiconductor layer 3. Then, an antioxidant film 5 is formed on the entire surface of the sacrificial oxide film 4 by a method such as CVD. For example, a silicon nitride film can be used as the antioxidant film 5.
Next, as shown in FIG. 2, by using the photolithography technique and the etching technique, the antioxidant film 5, the sacrificial oxide film 4, the second semiconductor layer 3, and the first semiconductor layer 2 are patterned, thereby the semiconductor substrate 1 A groove 6 for exposing a part of the groove 6 is formed. When a part of the semiconductor substrate 1 is exposed, the etching may be stopped on the surface of the semiconductor substrate 1 or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. . Further, the arrangement position of the groove 6 can correspond to a part of the element isolation region of the second semiconductor layer 3.

  Then, the cap layer 7 is formed on the side walls of the first semiconductor layer 2 and the second semiconductor layer 3 by a method such as CVD. Here, as the cap layer 7, for example, a silicon oxide film or a silicon film can be used. Then, a part of the first semiconductor layer 2 and the second semiconductor layer 3 is thermally oxidized with the cap layer 7 formed on the side walls of the first semiconductor layer 2 and the second semiconductor layer 3.

  Thereby, a semiconductor / oxide film having a low interface state at least on the side wall of the second semiconductor layer 3 in which the first groove 6 is formed while suppressing outward diffusion of components such as Ge contained in the first semiconductor layer 2. An interface can be formed. For this reason, it is possible to improve the quality of the SOI transistor formed in the second semiconductor layer 3 while suppressing the contamination of the second semiconductor layer 3 with the components contained in the first semiconductor layer 2.

  Next, as shown in FIG. 3, after forming a support 8 on the entire surface of the substrate by a method such as CVD, the support 8 is thinned by a method such as CMP (chemical mechanical polishing) or etch back. As a result, the surface of the antioxidant film 5 is exposed. The support 8 is also formed on the side walls of the first semiconductor layer 2 and the second semiconductor layer 3 in the groove 6, and supports the second semiconductor layer 3 on the semiconductor substrate 1. Further, as a material of the support 8, an insulator such as a silicon oxide film or a silicon nitride film can be used.

  Next, as shown in FIG. 4, the first semiconductor layer is patterned by patterning the antioxidant film 5, the sacrificial oxide film 4, the second semiconductor layer 3, and the first semiconductor layer 2 using a photolithography technique and an etching technique. 2 is exposed, and a groove 9 connected to the groove 6 is formed. Here, the arrangement position of the groove 9 can correspond to a part of the element isolation region of the second semiconductor layer 3.

  When a part of the first semiconductor layer 2 is exposed, the etching may be stopped on the surface of the first semiconductor layer 2, or the first semiconductor layer 2 is over-etched to form a recess in the first semiconductor layer. You may make it form. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first semiconductor layer 2 in the groove 9. Here, by stopping the etching of the first semiconductor layer 2 in the middle, the surface of the semiconductor substrate 1 in the groove 9 can be prevented from being exposed. For this reason, when the first semiconductor layer 2 is removed by etching, the time during which the semiconductor substrate 1 in the groove 9 is exposed to the etching solution or the etching gas can be reduced, and the overetching of the semiconductor substrate 1 in the groove 9 can be reduced. Can be suppressed.

Next, as shown in FIG. 5, the first semiconductor layer 2 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 2 through the groove 9, so that the semiconductor substrate 1 and the second semiconductor layer are removed. 3 to form a cavity 10.
Here, by providing the support 8 in the groove 6, the second semiconductor layer 3 can be supported on the semiconductor substrate 1 even when the first semiconductor layer 2 is removed, and the groove 6. By providing the groove 9 separately, the etching gas or the etching liquid can be brought into contact with the first semiconductor layer 2 below the second semiconductor layer 3. For this reason, it is possible to achieve insulation between the second semiconductor layer 3 and the semiconductor substrate 1 without impairing the quality of the second semiconductor layer 3.

  When the semiconductor substrate 1 and the second semiconductor layer 3 are Si and the first semiconductor layer 2 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 2. preferable. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 2 can be removed while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 3. It becomes. Further, as the etchant for the first semiconductor layer 2, hydrofluoric acid / hydrogen peroxide, ammonia / hydrogen peroxide, or hydrofluoric acid / hydrogen peroxide may be used.

  Further, before the first semiconductor layer 2 is removed by etching, the first semiconductor layer 2 may be made porous by a method such as anodic oxidation, or by ion implantation in the first semiconductor layer 2, The first semiconductor layer 2 may be made amorphous. Thereby, the etching rate of the first semiconductor layer 2 can be increased, and the etching area of the first semiconductor layer 2 can be increased.

  Next, as shown in FIG. 6, a buried insulating layer 11 is formed in the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. To do. Thus, the film thickness of the second semiconductor layer 3 after element isolation is defined by the film thickness of the second semiconductor layer 3 during epitaxial growth and the film thickness of the buried insulating layer 11 during thermal oxidation of the second semiconductor layer 3. Can do. For this reason, it is possible to control the film thickness of the second semiconductor layer 3 with high accuracy, and to reduce the variation in the film thickness of the second semiconductor layer 3 while reducing the thickness of the second semiconductor layer 3. it can.

  In the case where the buried insulating layer 11 is formed by thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3, it is preferable to use low-temperature wet oxidation that is reaction-controlled in order to improve the embeddability. At that time, the side wall of the second semiconductor layer 3 is also thermally oxidized. Further, after the buried insulating layer 11 is formed in the cavity 10, high temperature annealing at 1100 ° C. or higher may be performed. Thereby, the buried insulating layer 11 can be reflowed, the stress of the buried insulating layer 11 can be relieved, and the interface state at the boundary with the second semiconductor layer 3 can be reduced. Further, the buried insulating layer 11 may be formed so as to fill the entire cavity 10 or may be formed so that a part of the cavity 10 remains.

  In the method of FIG. 6, the buried insulating layer 11 is formed in the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. The cavity portion between the semiconductor substrate 1 and the second semiconductor layer 3 is formed by forming an insulating film in the cavity portion 10 between the semiconductor substrate 1 and the second semiconductor layer 3 by the CVD method. 10 may be embedded in the embedded insulating layer 11. As a result, the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 3 can be filled with a material other than the oxide film while preventing the second semiconductor layer 3 from being reduced. For this reason, it is possible to increase the thickness of the buried insulating layer 11 disposed on the back surface side of the second semiconductor layer 3 and to reduce the dielectric constant, so that the back surface side of the second semiconductor layer 3 can be reduced. Parasitic capacitance can be reduced.

  As a material of the buried insulating layer 11, for example, an FSG (fluorinated silicate glass) film or a silicon nitride film may be used in addition to the silicon oxide film. In addition to the SOG (Spin On Glass) film, the buried insulating layer 11 includes a PSG film, a BPSG film, a PAE (poly arylene ether) -based film, an HSQ (hydroxysilsesquioxane) -based film, an MSQ (methyl silsesquioxane-based film), and a MSQ (methyl silsesquioxane) film. An organic lowk film such as a film, a CF film, a SiOC film, or a SiOF film, or a porous film thereof may be used.

Further, by providing the antioxidant film 5 on the second semiconductor layer 3, the buried insulating layer 11 is formed on the back surface side of the second semiconductor layer 3 while preventing the surface of the second semiconductor layer 3 from being thermally oxidized. Therefore, it is possible to suppress the film loss of the second semiconductor layer 3.
In addition, by making the arrangement positions of the grooves 6 and 9 correspond to the element isolation regions of the second semiconductor layer 3, it becomes possible to collectively perform the element isolation in the horizontal direction and the vertical direction of the second semiconductor layer 3. By embedding the support 8 in the groove 6, it is not necessary to secure the support 8 that supports the second semiconductor layer 3 on the semiconductor substrate 1 in the active region. Therefore, an SOI transistor can be formed while suppressing an increase in the number of processes, and an increase in chip size can be suppressed, so that the cost of the SOI transistor can be reduced.

Then, after the buried insulating layer 11 is formed in the cavity 10 between the semiconductor substrate 1 and the second semiconductor layer 3, the second semiconductor layer 3 is thermally oxidized, so that the side wall of the second semiconductor layer 3 is thermally oxidized. A film 12 is formed. Here, when forming the thermal oxide film 12 on the side wall of the second semiconductor layer 3, it is preferable to use dry oxidation at a high temperature of 1100 ° C. or higher.
As a result, the corner portion of the second semiconductor layer 3 in which the first groove 6 and the second groove 9 are formed can be rounded, which helps to alleviate the electric field concentration and prevent the gate insulating film from being thinned at the corner portion. . As a result, it is extremely effective to prevent the breakdown voltage and reliability of the gate insulating film and to suppress a phenomenon in which a transistor having a low threshold value is parasitic on the corner portion.

  Next, as shown in FIG. 7, after the buried insulating film 13 is buried in the trench 9 by a method such as CVD, the support 8 is thinned by a method such as CMP or etchback, and the sacrificial oxide film 4 is also formed. Then, the surface of the second semiconductor layer 3 is exposed by removing the antioxidant film 5. Alternatively, the buried insulating film 13 may be buried in the trench 9 after removing the sacrificial oxide film 4 and the antioxidant film 5.

  Next, as shown in FIG. 8, the surface of the second semiconductor layer 3 is thermally oxidized to form a gate insulating film 15 on the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 15 is formed by a method such as CVD. Then, the gate electrode 14 is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 14 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3 to form LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 14. A layer is formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 16 are formed on the side walls. Then, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3 using the gate electrode 14 and the sidewall 16 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 16. Source / drain layers 17 a and 17 made of layers are formed on the second semiconductor layer 3.

  Thereby, it becomes possible to form the support body 8 which supports the 2nd semiconductor layer 3 on the semiconductor substrate 1 in the groove | channel 6, and it becomes unnecessary to arrange | position the support body 8 to an active region. For this reason, it is possible to form an SOI transistor on the second semiconductor layer 3 without using an SOI substrate, so that it is possible to reduce the price of the SOI transistor and increase the layout area of the SOI transistor. Therefore, the integration degree of the SOI transistor can be improved.

In the above-described embodiment, the method of laminating the second semiconductor layer 3 by one layer on the semiconductor substrate 1 through the buried insulating layer 11 has been described. However, a plurality of semiconductor layers are formed through the buried insulating layer, respectively. It may be laminated on the semiconductor substrate 1.
In the embodiment described above, a method of forming the antioxidant film 5 on the second semiconductor layer 3 in order to prevent thermal oxidation of the surface of the second semiconductor layer 3 when forming the buried insulating layer 11. As described above, the buried insulating layer 11 may be formed without forming the antioxidant film 5 on the second semiconductor layer 3. In this case, the insulating film formed on the surface of the second semiconductor layer 3 when the buried insulating layer 11 is formed may be removed by etching or polishing.

FIG. 9A is a plan view showing the layout method of the semiconductor device according to the second embodiment of the present invention, FIG. 9B is a cross-sectional view taken along the line A9-A9 ′ of FIG. FIG. 9C is a cross-sectional view taken along line B9-B9 ′ of FIG. FIG. 9 corresponds to the step of FIG.
In FIG. 9, a first semiconductor layer 22, a second semiconductor layer 23, a sacrificial oxide film 24 and an antioxidant film 25 are sequentially stacked on the semiconductor substrate 21. A groove 26 exposing the semiconductor substrate 21 is formed in the first semiconductor layer 22, the second semiconductor layer 23, the sacrificial oxide film 24 and the antioxidant film 25 along a predetermined direction. A cap layer 27 is formed, and a support 28 is embedded in the groove 26. In the first semiconductor layer 22, the second semiconductor layer 23, the sacrificial oxide film 24, and the antioxidant film 25, a groove 29 that exposes the semiconductor substrate 21 is formed along a direction orthogonal to the groove 26. Here, the grooves 26 and 29 are disposed in the element isolation region, and the end of the groove 29 can be terminated at the position of the support 28. As a result, the grooves 29 can be arranged without removing the support 28, and it is possible to perform element isolation of the second semiconductor layer 23 while suppressing complication of the manufacturing process. Need not be disposed in the active region, and the layout area of the SOI transistor can be increased.

  10 (a) to 18 (a) are plan views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention, and FIGS. 10 (b) to 18 (b) are FIG. 10 (a). Cross-sectional views cut along lines A11-A11 ′ to A19-A19 ′ in FIG. 18 (a), and FIGS. 10 (c) to 18 (c) are B11 in FIGS. 10 (a) to 18 (a). It is sectional drawing cut | disconnected by the -B11'-B19-B19 'line | wire, respectively.

  In FIG. 10, a first semiconductor layer 32 is formed on a semiconductor substrate 31 by epitaxial growth, and a second semiconductor layer 33 is formed on the first semiconductor layer 32 by epitaxial growth. Then, a sacrificial oxide film 34 is formed on the surface of the second semiconductor layer 33 by thermal oxidation of the second semiconductor layer 33. Then, an antioxidant film 35 is formed on the entire surface of the sacrificial oxide film 34 by a method such as CVD.

Next, as shown in FIG. 11, the semiconductor substrate 31 is patterned by patterning the antioxidant film 35, the sacrificial oxide film 34, the second semiconductor layer 33, and the first semiconductor layer 32 using photolithography technology and etching technology. A groove 36 for exposing a part of the groove 36 is formed. The arrangement position of the trench 36 can correspond to a part of the element isolation region of the second semiconductor layer 33.
Then, a cap layer 37 is formed on the side walls of the first semiconductor layer 32 and the second semiconductor layer 33 by a method such as CVD. Here, as the cap layer 37, for example, a silicon oxide film or a silicon film can be used. Then, a part of the first semiconductor layer 32 and the second semiconductor layer 33 is thermally oxidized with the cap layer 37 formed on the side walls of the first semiconductor layer 32 and the second semiconductor layer 33. After forming the cap layer, thermal oxidation is performed to suppress the outdiffusion of the components contained in the first semiconductor layer, and at least the semiconductor / oxidation with a low interface state at the side wall of the second semiconductor layer A film interface can be formed. At the same time, it is possible to prevent the surroundings from being contaminated by components contained in the first semiconductor layer.

  Next, as shown in FIG. 12, a support 38 embedded in the groove 36 is formed so as to cover the entire surface of the substrate by a method such as CVD. The support 38 is also formed on the sidewalls of the first semiconductor layer 32 and the second semiconductor layer 33 in the groove 36, and supports the second semiconductor layer 33 on the semiconductor substrate 31. The support body 38 formed so as to cover the entire substrate needs to support the second semiconductor layer 33 while maintaining the flatness by suppressing the deflection of the second semiconductor layer 33 and the like. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength.

  Next, as shown in FIG. 13, by patterning the support 38, the antioxidant film 35, the sacrificial oxide film 34, the second semiconductor layer 33, and the first semiconductor layer 32 using photolithography technology and etching technology, A part of the first semiconductor layer 32 is exposed, and a groove 39 connected to the groove 36 is formed. Here, the arrangement position of the groove 39 can correspond to a part of the element isolation region of the second semiconductor layer 33.

Next, as shown in FIG. 14, the first semiconductor layer 32 is removed by etching by bringing an etching gas or an etching solution into contact with the first semiconductor layer 32 through the groove 39, and the semiconductor substrate 31 and the second semiconductor layer are removed. A cavity 40 is formed between the first and second members 33.
Next, as shown in FIG. 15, the buried insulating layer 41 is formed in the cavity 40 between the semiconductor substrate 31 and the second semiconductor layer 33 by performing thermal oxidation of the semiconductor substrate 31 and the second semiconductor layer 33. To do. At this time, the side wall of the second semiconductor layer 33 is also oxidized. Note that, when the buried insulating layer 41 is formed by thermal oxidation of the semiconductor substrate 31 and the second semiconductor layer 33, it is preferable to use low-temperature wet oxidation that is reaction-controlled. Then, after forming the buried insulating layer 41 in the cavity 40 between the semiconductor substrate 31 and the second semiconductor layer 33, the second semiconductor layer 33 is thermally oxidized at a high temperature of 1100 ° C. or higher to thereby form the second semiconductor layer 33. The thermal oxide film 42 is formed on the side wall of the second semiconductor layer, and the corner portion of the second semiconductor layer is rounded at the same time. In the case where the thermal oxide film 42 is formed on the side wall of the second semiconductor layer 33, it is preferable to use dry oxidation at a high temperature of 1100 ° C. or higher for the above reason.

Next, as shown in FIG. 16, a buried insulating film 43 buried in the trench 39 is formed so as to cover the entire surface of the support 38 by a method such as CVD.
Next, as shown in FIG. 17, the buried insulating film 43 and the support 38 are thinned by a method such as CMP or etch-back, and the sacrificial oxide film 34 and the antioxidant film 35 are removed, whereby the second The surface of the semiconductor layer 33 is exposed.

  Next, as shown in FIG. 18, the surface of the second semiconductor layer 33 is thermally oxidized to form a gate insulating film 45 on the surface of the second semiconductor layer 33. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 33 on which the gate insulating film 45 is formed by a method such as CVD. Then, the gate electrode 44 is formed on the second semiconductor layer 33 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 44 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 33, thereby forming LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 44. A layer is formed on the second semiconductor layer 33. Then, an insulating layer is formed on the second semiconductor layer 33 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 46 are formed on the side walls. Then, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 33 using the gate electrode 44 and the sidewall 46 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 46. Source / drain layers 47 a and 47 made of layers are formed in the second semiconductor layer 33.

  Thereby, the solid body formed so as to be connected to the semiconductor substrate 31 and to cover the second semiconductor layer 33 without securing the support 38 for supporting the second semiconductor layer 33 on the semiconductor substrate 31 in the active region. It is possible to stably support the second semiconductor layer 33 on the semiconductor substrate 31 with the support 38 and to simultaneously support the support 38 embedded in the groove 36 and the embedded insulator 43 embedded in the groove 39. Thus, it becomes possible to reduce the thickness. For this reason, it is possible to form an SOI transistor on the second semiconductor layer 33 without using an SOI substrate, it is possible to reduce the cost of the SOI transistor, and simplify the element isolation process. The layout area of the SOI transistor can be increased.

FIG. 19A is a plan view showing a layout method of a semiconductor device according to the fourth embodiment of the present invention, FIG. 19B is a cross-sectional view taken along the line A20-A20 ′ of FIG. FIG. 19C is a cross-sectional view taken along line B20-B20 ′ of FIG. FIG. 19 corresponds to the step of FIG.
In FIG. 19, a first semiconductor layer 52, a second semiconductor layer 53, a sacrificial oxide film 54 and an antioxidant film 55 are sequentially stacked on a semiconductor substrate 51. The first semiconductor layer 52, the second semiconductor layer 53, the sacrificial oxide film 54, and the antioxidant film 55 are formed with a groove 56 that exposes the semiconductor substrate 51 along a predetermined direction. A cap layer 57 is formed, and a support body 58 is embedded in the groove 56 so as to cover the entire surface of the antioxidant film 55. In the first semiconductor layer 52, the second semiconductor layer 53, the sacrificial oxide film 54, and the antioxidant film 55, a groove 59 that exposes the semiconductor substrate 51 is formed along a direction orthogonal to the groove 56. Here, the grooves 56 and 59 are disposed in the element isolation region, and the end of the groove 59 can be terminated at the position of the support 58. As a result, the groove 59 can be disposed without removing the support 58, and it is possible to perform element isolation of the second semiconductor layer 53 while suppressing complication of the manufacturing process. Need not be disposed in the active region, and the layout area of the SOI transistor can be increased.

  20, FIG. 23 and FIG. 24 are plan views showing a layout method of a semiconductor device according to the fifth embodiment of the present invention. FIGS. 21A and 22A are A30-A30 ′ lines in FIG. FIG. 21B and FIG. 22B are cross-sectional views taken along line B30-B30 ′ of FIG. In the fifth embodiment, the SRAM layout is taken as an example. 21 shows a configuration corresponding to the layout of the second embodiment described above, and FIG. 22 shows a configuration corresponding to the layout of the fourth embodiment described above.

  20 and 21, a first semiconductor layer 62, a second semiconductor layer 63, a sacrificial oxide film 64, and an antioxidant film 65 are sequentially stacked on a semiconductor substrate 61. The first semiconductor layer 62, the second semiconductor layer 63, the sacrificial oxide film 64, and the antioxidant film 65 are formed with a groove 66 exposing the semiconductor substrate 61 along a predetermined direction. A cap layer 67 is formed, and a support body 68 is embedded in the groove 66. In the first semiconductor layer 62, the second semiconductor layer 63, the sacrificial oxide film 64, and the antioxidant film 65, a groove 69 that exposes the semiconductor substrate 61 is formed along a direction orthogonal to the groove 66. Here, the grooves 66 and 69 are disposed in the element isolation region, and the end of the groove 69 can be terminated at the position of the support 68. In the layout of the fourth embodiment, the support 68 is left on the entire surface of the antioxidant film 65 as shown in FIG.

  As shown in FIG. 20, the second semiconductor layer 63 is provided with active regions R1 to R6 separated by grooves 66 and 69. Further, as in the above embodiment, the first semiconductor layer 62 is selectively removed by etching, and then a buried oxide film is formed. Further, the trench 69 is filled with an insulating film, flattened by CMP or the like, and the antioxidant film 65 is formed. Then, by removing the sacrificial oxide film 64, the second semiconductor layer is separated by an element isolation region formed in a portion corresponding to the grooves 66 and 69. Subsequently, after forming a gate insulating film on the first semiconductor layer 62, as shown in FIG. 23, gate electrodes G1 and G2 are arranged in the vertical direction in the active region R1, and gate electrodes G3 are arranged in the active regions R1 and R2. , G4 are arranged in the vertical direction, and gate electrodes G5, G6 are arranged in the vertical direction in the active region R3. Further, gate electrodes G11 and G12 are arranged in the vertical direction in the active region R4, gate electrodes G13 and G14 are arranged in the vertical direction in the active regions R4 and R5, and gate electrodes G15 and G16 are arranged in the vertical direction in the active region R6. Arranged in the direction. Further, gate electrodes G17 and G18 are disposed in the lateral direction in the active regions R1 and R2. N-type impurity diffusion layers are formed in the active regions R1 and R4, N-channel field effect transistors are formed, and P-type impurity diffusion layers are formed in the active regions R2, R3, R5, and R6. A P-channel field effect transistor is formed. Further, a lower wiring layer H1 is formed on the gate electrodes G1 to G6, G11 to G16, G17, and G18, and an upper wiring layer H2 is formed on the lower wiring layer H1 as shown in FIG. Yes. Then, the active regions R1 to R6, the gate electrodes G1 to G6, G11 to G16, G17, and G18, the lower wiring layer H1, and the upper wiring layer H2 are connected via the contact holes CN and HO, thereby configuring the SRAM. Has been.

The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. FIG. 6 is a diagram showing a layout method of a semiconductor device according to a second embodiment of the present invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the layout method of the semiconductor device which concerns on 4th Embodiment of this invention. The figure which shows the layout method of the semiconductor device which concerns on 5th Embodiment of this invention. FIG. 21 is a cross-sectional view illustrating an example of a cross-sectional structure of the semiconductor device in FIG. 20. FIG. 21 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device of FIG. 20. The figure which shows the layout method of the semiconductor device which concerns on 5th Embodiment of this invention. The figure which shows the layout method of the semiconductor device which concerns on 5th Embodiment of this invention.

Explanation of symbols

  1, 21, 31, 51, 61 Semiconductor substrate 2, 22, 32, 52, 62 First semiconductor layer 3, 23, 33, 53, 63 Second semiconductor layer 4, 24, 34, 54, 64 sacrifice Oxide film 5, 25, 35, 55, 65 Antioxidation film, 6, 9, 29, 36, 39, 59, 66, 69 Groove, 7, 27, 37, 57, 67 Cap layer, 8, 28, 38 58, 68 Support 10, 10, 40 Cavity, 11, 41 Embedded insulating layer, 12, 42 Thermal oxide film, 13, 43 Embedded insulating film, 14, 44 Gate insulating film, 15, 45, G1-G6, G11 ~ G16, G17, G18 Gate electrode, 16, 46 Side wall spacer, 17a, 17b, 47a, 47b Source / drain layer, R1-R6 active region, CN, HO contact hole, H1 lower layer wiring , H2 upper wiring layer

Claims (10)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support embedded in the first groove and supporting the second semiconductor layer on the semiconductor substrate;
Forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the second groove;
Forming a buried insulating layer buried in the cavity;
Forming a buried insulator embedded in the second groove ;
Before embedding a support in the first groove, the first semiconductor layer and the second semiconductor in the first groove
After forming the cap oxide film on the side wall of the layer, it is oxidized at the interface between the side wall and the cap oxide film by thermal oxidation
And a step of forming a film . Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support embedded in the first groove and supporting the second semiconductor layer on the semiconductor substrate;
Forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the second groove;
Forming a buried insulating layer buried in the cavity;
Forming a buried insulator embedded in the second groove ;
Before embedding a support in the first groove, the first semiconductor layer and the second semiconductor in the first groove
Forming a semiconductor film on the side wall of the layer;
The semiconductor film is thermally oxidized, and part of the first semiconductor layer and the second semiconductor layer is heated.
And a step of oxidizing the semiconductor device. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support embedded in the first groove so as to cover the second semiconductor layer and supporting the second semiconductor layer on the semiconductor substrate;
Forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer and the support;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the second groove;
Forming a buried insulating layer buried in the cavity;
Forming a buried insulator embedded in the second groove so as to cover the support;
By thinning the buried insulator and the support, thereby exposing the surface of said second semiconductor layer,
Before embedding a support in the first groove, the first semiconductor layer and the second semiconductor in the first groove
After forming the cap oxide film on the side wall of the layer, it is oxidized at the interface between the side wall and the cap oxide film by thermal oxidation
And a step of forming a film . Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support embedded in the first groove so as to cover the second semiconductor layer and supporting the second semiconductor layer on the semiconductor substrate;
Forming a second groove connected to the first groove and exposing at least a part of the first semiconductor layer from the second semiconductor layer and the support;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the second groove;
Forming a buried insulating layer buried in the cavity;
Forming a buried insulator embedded in the second groove so as to cover the support;
By thinning the buried insulator and the support, thereby exposing the surface of said second semiconductor layer,
Before embedding a support in the first groove, the first semiconductor layer and the second semiconductor in the first groove
Forming a semiconductor film on the side wall of the layer;
The semiconductor film is thermally oxidized, and part of the first semiconductor layer and the second semiconductor layer is heated.
And a step of oxidizing the semiconductor device. The semiconductor substrate and the second semiconductor layer are single crystal Si, and the first semiconductor layer is single crystal Si.
The method of manufacturing a semiconductor device according to any one of claims 1, wherein 4 to be a Ge. The method of manufacturing a semiconductor device according to any one of claims 1 to 5 an end of the second groove, characterized in that it is terminated with the support. Wherein the first before forming the groove, the method of manufacturing a semiconductor device according to any one of claims 1 6, characterized by further comprising a step of forming an insulating film on a surface of the second semiconductor layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the insulating film includes at least a silicon nitride film. The insulating support on the membrane is formed, the manufacturing method of the thickness of the semiconductor device according to claim 7 or 8, wherein the at 400nm or more. After the formation of the cap oxide film in the first groove, the semiconductor device according to claim 1 or 3, wherein a portion of the first semiconductor layer and the second semiconductor layer and further comprising the step of thermally oxidizing Production method.

Images