JP2003324200A - Field effect transistor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor and a method for manufacturing the same for improving the integration density of a circuit, and quickly performing a switching operation. <P>SOLUTION: Four gate electrodes 31, 32, 33, and 34 with the same potentials in parallel are electrically connected to each other at a gate 25. Three p-type regions 35, 36, and 37 are interposed among the gate electrodes. Gate oxide films 38, 39, and 40 are formed in the p-type regions 35, 36, and 37. A source 24 and a drain 26 are each provided with a source electrode 41 and a drain electrode 42 connecting six channels formed in a boundary between the p-type regions 35, 36, and 37 and the insulating layers 38, 39, and 40. When positive voltages are applied to the gate electrodes 31, 32, 33, and 34, six channels are formed, and drain currents are made to flow between the drain 26 and the source 24 through the channels. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an LSI (large sca
MOS (metal), which is the basic element of a le integrated circuit
oxide semiconductor) transistor and MIS (metal in
The present invention relates to a field effect transistor such as a transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as such a field effect transistor, for example, a double gate nMOS transistor as shown in a sectional view in FIG. 1 has been proposed. This field effect transistor includes a substrate 1, an insulating layer 2 provided on the substrate 1, a gate electrode 3 and a gate insulating film 4 provided on the substrate 1, and an insulating material surrounding the gate electrode 3 and the gate insulating film 4. The film 5, the p-type region 6 provided on the gate insulating film 4, and N ⁺ provided on both sides of the p-type region 6 respectively.
The source 7 and the N ⁺ -type drain 8, the gate insulating film 9 and the gate electrode 10 provided on the p-type region 6, and the N ^{+ -type} source 7, the gate electrode 10 and the N ⁺ -type drain 8 are electrically connected to each other. Silicide parts 11, 12 and 13 to be connected,
Between the silicide parts 11 and 12 and the silicide parts 12 and 13
And an insulating portion 14 between them. The silicide portions 11 and 13 form a source electrode and a drain electrode, respectively.

In this case, the gate electrodes 3 and 10 have the same potential, and by applying a positive voltage to the gate electrodes 3 and 10, the interface between the gate insulating film 4 and the p-type region 6 and the gate insulating film are formed. A channel is formed at the interface between 9 and the p-type region 6, and a drain current flows between the drain electrode 13 and the source electrode 11. The drain current that flows when the field effect transistor is turned on is called the on-current.

[0004]

However, in the conventional field effect transistor, in order to obtain a desired on-current, the width of the gate electrode is set to a predetermined value or more, or a plurality of gate electrodes are arranged on the same plane. Because it needs to be formed
The area occupied by the field effect transistor is increased, which hinders the improvement of the circuit integration density.

Further, the parasitic capacitance between the gate electrode and the substrate increases as the width of the gate electrode increases. As a result, in the conventional field effect transistor in which the width of the gate electrode is set to be equal to or larger than a predetermined value, the parasitic capacitance increases, which causes a problem in speeding up the switching operation.

Further, it is necessary to increase the width of the drain electrode by forming a plurality of gate electrodes on the same plane, but the parasitic capacitance between the drain electrode and the substrate is
It increases as the width of the drain electrode increases. As a result, even in the conventional field effect transistor in which a plurality of gate electrodes are formed on the same plane, the parasitic capacitance increases, which causes a problem in speeding up the switching operation.

An object of the present invention is to provide a field effect transistor capable of improving the circuit integration density and performing a switching operation at high speed, and a method of manufacturing the same.

[0008]

A field effect transistor according to the present invention includes three or more gate regions which are electrically connected to each other and which are parallel to each other, and are respectively interposed between these gate regions to form a channel. It is characterized by comprising two or more semiconductor regions, and a source region and a drain region connecting four or more channels formed at an interface between the gate region and a semiconductor region adjacent thereto.

According to the present invention, the gate regions and the semiconductor regions are alternately arranged on the same cross section, that is, in the vertical direction by the three or more gate regions parallel to each other and the two or more semiconductor regions respectively interposed between the gate regions. Is formed. It should be noted that the number of semiconductor regions is one less than the number of gate regions, and the number of semiconductor regions in the semiconductor region is nM.
If it is an OS transistor, it becomes a p-type region, and pM
When it is an OS transistor, it becomes an n-type region.

As a result, four or more channels are formed in the vertical direction, and the on-current per unit gate width (1 μm) in a plane becomes larger than that of the conventional field effect transistor having at most two channels. as a result,
Since it is not necessary to set the width of the gate electrode to a predetermined value or more or to form a plurality of gate electrodes on the same plane in order to obtain a desired on-current, it is not necessary to increase the area occupied by the field effect transistor. The circuit integration density can be improved.

Further, since the parasitic capacitance is not increased due to the increase in the width of the gate electrode or the width of the drain electrode,
The switching operation can be performed at high speed.

The method of manufacturing a field effect transistor according to the present invention comprises three or more parallel gate regions electrically connected to each other and two or more gate regions interposed between the gate regions to form a channel. A step of providing a semiconductor region and a source region connecting four or more channels formed at an interface between the gate region and a semiconductor region adjacent to the gate region and the semiconductor region adjacent to the gate region and the semiconductor region before or after the formation of the semiconductor region And providing a drain region.

According to the present invention, it is possible to manufacture a field effect transistor capable of improving the circuit integration density and performing a switching operation at high speed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a field effect transistor and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. It should be noted that the drawings are not to scale and some are exaggerated. FIG. 2 is a perspective view of a field effect transistor according to the present invention. The field effect transistor as the nMOS transistor shown in FIG.
It comprises a buried SiO ₂ layer 21 formed thereon, and insulating layers 22 and 23, a source portion 24, a gate portion 25 and a drain portion 26 formed thereon. Source part 24,
Each of the gate portion 25 and the drain portion 26 is silicided on the surface of the n ⁺ polycrystalline Si.

FIG. 3A is a view showing a II 'section of FIG. 2, and FIG. 3B is a view showing a II-II' section of FIG.
In FIG. 3B, in the gate portion 25, four gate electrodes 31, 32, 33, 34 that are parallel to each other and have the same potential are electrically connected to each other, and these four gate electrodes 31, 3
Between 2, 33 and 34, three p-type regions 35, 36,
Gate oxide films 38, 39 and 40 are formed in the p-type regions 35, 36 and 37, respectively. Further, as will be described later, N ^{+ -type} sources 35a, 36a, 37 are provided on both sides of the p-type regions 35, 36, 37, respectively.
The a and N ^{+ type} drains 35b, 36b, 37b are arranged. .

The source portion 24 and the drain portion 26 have p-type regions 35, 36, 37 and insulating layers 38, 39, 4 respectively.
It has a source electrode 41 and a drain electrode 42 which connect six channels formed at the interface with 0.

The operation of this embodiment will be described. When a positive voltage is applied to the gate electrodes 31, 32, 33, 34, the above six channels are formed, and a drain current flows between the drain section 26 and the source section 24 through these channels. Thereby, the on-current of the field effect transistor is obtained as the sum of the currents flowing through these six channels.

When compared with the conventional field effect transistor as shown in FIG. 1, when the width of the planar gate electrode is the same, the drain current becomes, for example, about 2-3 times, and as a result, the ON current is increased. Therefore, it is not necessary to set the width of the gate electrode to a predetermined value or more or to form a plurality of gate electrodes on the same plane in order to obtain the necessary drain current. Therefore, it is necessary to increase the area occupied by the field effect transistor. Therefore, the integration density of the circuit can be improved.

Since the parasitic capacitance does not increase due to the increase in the width of the gate electrode or the width of the drain electrode, the switching operation can be performed at high speed. In this case, the parasitic capacitance is, for example, about 1 / 2-1 / 3 as compared with the conventional field effect transistor as shown in FIG.

FIG. 4 is a sectional view of another field effect transistor according to the present invention. This cross section is a cross section corresponding to the II-II ′ cross section of FIG.
1, 42, 43, 44 are electrically connected only on one side. Thereby, the gate electrodes 41, 42, 43, 44
The parasitic capacitance between the substrate and the substrate 45 is further reduced.

Next, a method of manufacturing the field effect transistor shown in FIG. 2 will be described. As will be described later, a part of the manufacturing process is part of the CVD (chemical vapor depositi) shown in FIG.
on) apparatus, but FIG. 5 also shows a wafer 46 on which CVD, which will be described later, is performed.

In explaining the manufacturing process with reference to FIGS. 6-17, FIGS. 6, 7, 8A, 9A, 10A, 11A,
12A, 13A, 14A, 15A, 16A, 17A,
8B, 9B, 10B, corresponding to the II 'cross section of FIG.
11B, 12B, 13B, 14B, 15B, 16B, 1
7B corresponds to the II-II ′ cross section of FIG. 2.

First, the embedded S on the silicon substrate 51.
with iO ₂ layer 52 is buried SOI that ultrathin Si single crystal layer 53 on the SiO ₂ layer 52 is formed (s
(ilicon on Insulator) is prepared (Fig. 6). The ultra-thin Si single crystal layer 53 is, for example, 10 nm.

Then, the SiGe layer 55, the Si layer 56, and the S
The iGe layers 57, the Si layers 58, the SiGe layers 59, and the Si layers 60 are epitaxially grown so as to be alternately stacked (FIG. 7). These SiGe layer 55, Si layer 56, SiG
e layer 57, Si layer 58, SiGe layer 59, and Si layer 60
The thickness of each is, for example, 30 to 50 nm.

For example, when forming a SiGe layer of Ge 18%, Ge ₂ H ₂ (germane) 0.2 Pa, SiH
₄ (silane) 6 Pa, H ₂ (hydrogen) 30 Pa, temperature 55
Under the condition of 0 ° C., the growth rate becomes 70 × 10 ⁻¹⁰ m / min. Therefore, the formation time of the SiGe layer having a thickness of 35 nm is 5 minutes.

In forming the Si layer, SiH ₄
(Silane) 6 Pa, H ₂ (hydrogen) 30 Pa, temperature 550
The growth rate is 10 × 10 ⁻¹⁰ m / min under the condition of ° C. Therefore, it takes 35 minutes to form the Si layer having a thickness of 35 nm.

Next, the SiGe layer 55, the Si layer 56, and the S
The iGe layer 57, the Si layer 58, the SiGe layer 59, and the Si layer 60 are processed by RIE (reactive ion etching) to partially remove them (FIG. 8). At this time, the ultra-thin SiO ₂ film 6
1 and a Si ₃ N ₄ film 62 are sequentially formed and used as a mask during RIE together with a resist.

Next, the wafer shown in FIG. 8 is shown in FIG.
It is housed in a furnace 63 and is formed by CVD using SiO 2._TwoThe membrane 64
After depositing about 500 nm, S is deposited using CMP technology.
iO _TwoThe film 64 is flattened (FIG. 9).

Next, the Si ₃ N ₄ film 62 is removed by etching with a hot phosphoric acid solution, a resist pattern is formed by using a lithography technique, and the formed resist pattern is used as a mask for wet etching (dilute hydrofluoric acid). Such)
By removing a portion of the SiO ₂ film 64, SiO ₂
The film 64 is replaced with the SiGe layer 55, the Si layer 56, the SiGe layer 5
7, the Si layer 58, the SiGe layer 59, and the Si layer 60 are separated from the side surfaces (FIG. 10). Note that RIE may be performed together with wet etching.

Then, for example, HNO ₃ : H ₂ O: HF =
The etching rate of SiGe such as 60: 60: 1 is S
The SiGe layers 55, 57 and 59 are removed by performing anisotropic etching using an etching solution that is significantly faster than i. At this time, the Si layers 53, 56, 58 and 60 are hardly etched.

Then, the Si layers 53 and 5 are formed by thermal oxidation.
A SiO ₂ film is formed on 6, 58 and 60. At this time, a SiO ₂ film having a thickness of 20 nm is formed by wet O _{2 at} 700 ° C., for example. At this time, the Si layer 53 is completely oxidized. Then, with a dilute hydrofluoric acid etching solution,
The formed SiO ₂ film having a thickness of 20 nm is removed (FIG. 11).

Next, thermal oxidation is performed to form SiO ₂ films 61, 62, 63 as gate insulating films. For example, S
The iO ₂ films 61, 62, 63 have the same thickness of about 1-15 nm (FIG. 12). As the gate insulating film, S
In addition to iO ₂ , a SiON film or a silicon nitride film formed by plasma nitriding or the like may be used.

Next, the wafer shown in FIG. 12 is housed in the furnace 63 shown in FIG. 5, phosphorus-doped amorphous Si 64 is deposited by using the CVD method, and then the Si film 64 is flattened by using the CMP technique ( (Fig. 13). The amount of phosphorus added is, for example, 1 × 10 ²⁰ cm ⁻³ or more.

Next, the silicon nitride film 65 is formed, for example, by 10-100 nm by ECR sputtering method, CVD method or the like.
Form a degree. Then, a lithography technique is used to form a resist pattern corresponding to the gate portion 25 of FIG. After that, RI using this resist pattern as a mask
According to E, the silicon nitride film 65, phosphorus-doped amorphous Si 64, Si layers 56, 58, 60 and thin SiO ₂
The films 61, 62 and 63 are processed (FIG. 14).

Next, thermal oxidation is performed. At this time, phosphorus addition
The oxidation rate of the amorphous Si 64 is the Si layers 56, 58,
Compared to the oxidation rate of 60, phosphorus-containing ammo
SiO formed on the surface of Rufus Si 64_TwoMembrane 66-
73 is SiO formed on the Si layers 56, 58, and 60._Two
It becomes thicker than the film. Then, the Si layers 56, 58, 60
SiO formed on_TwoThe film is plasma etched
Removed (FIG. 15). Then, if necessary, phosphorus
Ions are implanted from an oblique direction, annealed, and implanted
Activate on. For example, a dose amount of 2 at 30 keV
× 10¹⁵cm ^-2Ion-implant phosphorus.

Then, phosphorus-doped amorphous Si is deposited and flattened by CMP. The amount of phosphorus added is, for example, 1 × 10 ²⁰ cm ⁻³ or more. Then, the silicon nitride film 65 is removed with hot phosphoric acid or the like. Then, the source section 24 and the gate section 2 of FIG.
5 and a resist pattern corresponding to the drain portion 26 is formed. After that, phosphorus-doped amorphous Si is processed by RIE using this resist pattern as a mask.
Then, by using the CVD method, SiO ₂ film is formed corresponding to the SiO ₂ film 23 of FIG. 2, then planarized by CMP. Then, heat treatment is performed to remove phosphorus from the Si layer 56,
Diffused to 58, 60 and N ^{+ type} sources 74, 75, 76
And N ^{+ type} drains 77, 78, 79 (FIG. 1).
6). Up to this stage, phosphorus-doped amorphous S
i becomes polycrystalline silicon.

Then, a silicide portion 80 forming a part of the source electrode of the field effect transistor shown in FIG. 2, a silicide portion 81 electrically connecting to the gate electrode, and a silicide portion 82 forming a part of the source electrode are formed. It is formed by a conventional method to complete the field effect transistor shown in FIG.

Next, another method of manufacturing the field effect transistor shown in FIG. 2 will be described. Also in this case, a part of the manufacturing process is CVD (chemical vapor deposition) shown in FIG.
It is performed using the device.

In describing the manufacturing process with reference to FIGS. 18-22, FIGS. 18, 19A, 20A, 21A, 22
A corresponds to the II ′ cross section of FIG. 2, and FIG.
B, 21B, and 22B correspond to the II-II 'cross section of FIG.

First, two SOI substrates are wafer-bonded, and only one silicon substrate of the SOI substrates is removed by etching or the like. After that, another S-layer is formed on the substrate in which the _two ultra-thin Si layers are alternately laminated with the embedded SiO ₂ layers.
The OI substrate is wafer-bonded and the silicon substrate of another SOI substrate is removed. As a result, the ultra-thin Si layer 9
A substrate in which 1, 92 and 93 are alternately laminated with SiO ₂ layers 94, 95 and 96 is formed (FIG. 18).

Next, thin SiO_TwoAfter forming the film 97, S
i_ThreeN_FourAfter further forming the film 98, lithographic techniques and
And RIE, ultrathin Si layers 91, 92, 93 and S
iO _TwoPart of the layers 94, 95, 96 are removed (Fig. 1
9).

Next, the wafer shown in FIG. 19 is housed in the furnace 63 shown in FIG. 5, and the SiO ₂ layer 99 is formed by the CVD method.
Of the SiO ₂ film 99, and then using the CMP technique.
Are polished and flattened (FIG. 20).

Then, a part of the SiO ₂ film 99 is removed by using the lithographic technique and the RIE, and the SiO ₂ film 9 is removed.
9 is an ultra-thin Si layer 91, 92, 93, a SiO ₂ layer 95,
96 and the side surface of the Si ₃ N ₄ film 98 (see FIG. 2).
1).

Then, an etching solution such as dilute hydrofluoric acid is used.
Using SiO_TwoUnder layers 95, 96 and ultra-thin Si layer 91
Part of SiO_TwoEtch a portion of layer 94. afterwards,
Si _ThreeN_FourThe film 98 is etched with hot phosphoric acid or the like (Fig.
22).

In the subsequent steps, the Si layer 5 formed by the above thermal oxidation is used.
This is the same as the steps after the step of forming the SiO ₂ film on 3, 56, 58, 60, but completely oxidizes the Si layer 53 before forming the SiO ₂ films 61, 62, 63 as the gate oxide film. The thermal oxidation is not essential, and even if the thermal oxidation is performed, it may be thin.

The present invention is not limited to the above embodiment, but various modifications and variations are possible. For example, in the above embodiment, the case of the nMOS transistor has been described, but in the case of the pMOS transistor,
The present invention can be applied to other types of transistors such as MIS transistors.

Further, a field effect transistor other than the structure shown in FIGS. 2, 3 and 4 can be constructed. For example, the gate electrode can be an arbitrary number of three or more and two or more semiconductor regions can be formed. The number can be one less than the number of gate electrodes.

Further, a manufacturing method other than the manufacturing method of the field effect transistor described in the above-mentioned embodiment can be used. For example, in the step of obtaining the wafer shown in FIG. 10, the SiGe layer 55, the Si layer 56, and the SiGe layer are formed. 57, S
By etching and removing a part of one side of the i layer 58, the SiGe layer 59, and the Si layer 60, the field effect transistor having the structure shown in FIG. 4 can be manufactured. Further, in the step of obtaining the wafer shown in FIG. 21, by etching and removing a part of one side of the ultrathin Si layers 91, 92, 93, the SiO ₂ layers 95, 96 and the Si ₃ N ₄ film 98. The field effect transistor having the structure shown in FIG. 4 can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a conventional field effect transistor.

FIG. 2 is a perspective view of a field effect transistor according to the present invention.

3 is a cross-sectional view of the field effect transistor of FIG.

FIG. 4 is a cross-sectional view of another field effect transistor according to the present invention.

FIG. 5 is a diagram showing a CVD apparatus used in the method for manufacturing a field effect transistor according to the present invention.

FIG. 6 is a diagram showing a first step of a method for manufacturing a field effect transistor according to the present invention.

FIG. 7 is a diagram showing a second step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 8 is a diagram showing a third step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 9 is a diagram showing a fourth step of the method for manufacturing the field effect transistor according to the present invention.

FIG. 10 is a diagram showing a fifth step of the method for manufacturing the field effect transistor according to the present invention.

FIG. 11 is a diagram showing a sixth step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 12 is a diagram showing a seventh step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 13 is a diagram showing an eighth step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 14 is a diagram showing a ninth step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 15 is a diagram showing a tenth step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 16 is a diagram showing an eleventh step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 17 is a diagram showing a twelfth step of the method for manufacturing a field effect transistor according to the present invention.

FIG. 18 is a diagram showing a first step of another method for manufacturing a field effect transistor according to the present invention.

FIG. 19 is a diagram showing a second step of another method for manufacturing a field effect transistor according to the present invention.

FIG. 20 is a diagram showing a third step of another method for manufacturing a field effect transistor according to the present invention.

FIG. 21 is a diagram showing a fourth step of another method for manufacturing a field effect transistor according to the present invention.

FIG. 22 is a diagram showing a fifth step of another method for manufacturing a field effect transistor according to the present invention.

Continued front page    (72) Inventor Masao Sakuraba             8-3-8 Nagamachi, Taihaku-ku, Sendai City, Miyagi Prefecture             101 F-term (reference) 5F110 AA01 AA04 AA07 BB11 CC02                       DD05 DD13 EE05 EE09 EE22                       EE27 EE30 EE45 FF02 FF03                       FF04 FF23 GG02 GG12 GG30                       GG44 HJ01 HJ14 HJ16 HJ23                       HK05 HK14 HK21 HM02 QQ19

Claims (2)

[Claims] 1. Three or more parallel gate regions electrically connected to each other, two or more semiconductor regions respectively interposed between these gate regions to form a channel, and the gate region. A field effect transistor, comprising: a source region and a drain region connecting four or more of the channels, each of which is formed at an interface with a semiconductor region adjacent thereto. 2. Providing three or more parallel gate regions electrically connected to each other and two or more semiconductor regions respectively interposed between the gate regions to form a channel, and these gates. Before, after, or at the same time as forming the region and the semiconductor region, providing a source region and a drain region connecting four or more channels formed at the interface between the gate region and the semiconductor region adjacent thereto, respectively. A method for manufacturing a field effect transistor, comprising: