JP5544715B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a MIS (Metal Insulator Semiconductor) type field effect transistor whose characteristics can be adjusted by a control terminal and which can realize high integration and driving ability. And a manufacturing method thereof.

  MIS field effect transistors (MISFETs) have simultaneously improved driving capability and integration by miniaturizing dimensions. However, recently, the thickness of the gate insulating thin film has reached the level of 2 nm or less and the gate length is 50 nm or less, and it is becoming difficult to simply miniaturize due to an increase in leakage current and the like. For this reason, it is difficult to further improve the driving force and the degree of integration in the conventional planar MISFET formed on the semiconductor substrate plane.

  As means for solving this problem, Patent Documents 1 and 2 describe multilayer channel type MISFETs in which a plurality of thin film semiconductors forming a channel are arranged in the vertical direction with respect to a substrate and these are connected in parallel to form one transistor. ing. 9 is a conceptual diagram showing the structure of a conventional MISFET disclosed in Patent Documents 1 and 2, FIG. 9C is a plan view thereof, FIG. 9A is a cross-sectional view taken along line AA shown in FIG. ) Is a BB cross-sectional view shown in (c). In the following description, it is assumed that the MISFET is an N-channel MISFET. In the case of a P-channel MISFET, the polarity of the potential may be reversed, and N and P, which are impurity conductivity types, may be interchanged and read. In the following description, when referring to the vertical direction, the substrate side is the lower side and the opposite side is the upper side.

  As shown in FIG. 9, above the substrate 100, thin semiconductor layers 102b and 102a that become channels of the MISFET are sequentially stacked so as to be separated from each other. The upper and lower surfaces and two side surfaces of the semiconductor layers 102 a and 102 b are surrounded by the gate electrode 105 with the gate insulating film 104 interposed therebetween. That is, as shown in FIG. 9A, gate electrodes 105b and 105c are provided on the upper and lower surfaces of the semiconductor layer 102b via the gate insulating film 104, respectively, and on the upper and lower surfaces of the semiconductor layer 102a. Are provided with gate electrodes 105 a and 105 b through a gate insulating film 104, respectively. Further, as shown in FIG. 9B, the cross sections of the semiconductor layers 102 a and 102 b formed by the BB cross section are surrounded by the gate electrode 105. In other words, the gate electrode 105 is horizontally penetrated by the semiconductor layers 102a and 102b with the gate insulating film 104 interposed therebetween. The other two sides of the semiconductor layers 102a and 102b are one source / drain region 103a, one side of which is common to both semiconductor layers, and the other source / drain of the other side common to both semiconductor layers. It is connected to the area 103b. Source / drain contact conductors 106a and 106b are provided above the source / drain regions 103a and 103b, respectively, and a gate contact conductor 106c is provided above the gate electrode 105. The source / drain regions 103a and 103b are doped N-type. Thus, a single MISFET is configured.

  A channel is formed in the semiconductor layers 102a and 102b when the potential of the gate electrode 105 is sufficiently higher than the threshold value, and the source / drain 103a and 103b are electrically connected. On the other hand, when the potential of the gate electrode 105 is sufficiently lower than the threshold value, a channel is not formed, and the source / drain 103a and 103b are electrically disconnected.

  In the conventional MISFET structure described above, the channel is formed in the thin semiconductor layers 102a and 102b, and the gate electrode 105 has a so-called double gate SOI (Silicon On Insulator) structure in which the semiconductor layers 102a and 102b are sandwiched from both sides. ing. When a channel is formed in such a thin semiconductor layer, it is possible to suppress the short channel effect and reduce the distance (channel length) between the source and drain regions by thinning the semiconductor layer. The channel length can be reduced approximately in proportion to the thickness of the semiconductor layer. Further, by sandwiching the gate electrode from both sides (double gate), the channel length can be reduced to approximately ½ compared to the case where the gate electrode is only on one side (single gate). Therefore, the conventional MISFET of FIG. 9 is suitable for miniaturization and can meet the demand for high integration.

  In the conventional MISFET structure described above, two semiconductor layers forming a channel are formed in parallel in the vertical direction. For this reason, without increasing the projected area occupied by the MISFET, it is possible to obtain a driving capability almost twice that of a normal double gate MISFET in which only one semiconductor layer is formed. In addition, a driving capability almost four times that of a normal single gate type MISFET (a channel is formed only on one side of a semiconductor layer) in which only one semiconductor layer is formed can be obtained. In this way, the driving capability can be greatly improved without hindering high integration.

  Further, in the conventional SOI structure semiconductor device described in Patent Document 3, a MOS transistor is formed on a silicon substrate via an insulating film, and a gate oxide film on the thin film semiconductor layer in this MOS transistor is formed. A buried gate insulating film and a buried gate electrode are sequentially formed on the side opposite to the opposite side. The threshold voltage of the MOS transistor can be controlled by controlling the voltage applied to the buried gate electrode.

JP 2003-324200 A JP 2004-128508 A Japanese Patent Laid-Open No. 05-167073

  However, the above-described prior art has the following problems.

  In a MISFET using a bulk semiconductor substrate, the threshold voltage of the MISFET can be changed by controlling the potential of the semiconductor substrate. Also in a MISFET using an SOI substrate, the threshold voltage of the MISFET can be changed by controlling the potential of the semiconductor substrate under the buried insulating film embedded in the SOI substrate. In the above, the substrate functions as the fourth terminal. If the threshold voltage of the MISFET can be controlled by the fourth terminal, the threshold voltage is increased when the circuit is in the standby state to reduce the leakage current, and the threshold voltage is decreased when the circuit is in the operating state to drive the MISFET. By increasing the capability, variable threshold operation is possible. Alternatively, when the threshold value of the MISFET deviates from the target value due to manufacturing variations, the threshold voltage can be adjusted to a desired value by the substrate potential. However, in the semiconductor devices disclosed in Patent Documents 1 and 2, since the semiconductor layer in which the channel is formed is surrounded on all sides by the single gate electrode 105, the influence of the substrate potential does not reach the channel, and the threshold voltage Cannot be adjusted.

  In the prior art disclosed in Patent Document 3, although the threshold voltage can be controlled by controlling the voltage applied to the buried gate electrode, the semiconductor layer of the MOS transistor is a single layer, and The structure is different from the structure in which the semiconductor layers are arranged in parallel in a plurality of layers in the vertical direction. For this reason, it is difficult to improve the integration degree and the driving force.

  The present invention has been made in view of such problems, and provides a semiconductor device capable of realizing a high integration degree and a high driving capability and capable of controlling a threshold voltage by an externally applied voltage, and a method for manufacturing the same. With the goal.

A semiconductor device according to the present invention includes a substrate, a source region and a drain region formed on the substrate, and a plurality of channel layers stacked apart from each other between the source region and the drain region on the substrate. Region, a plurality of gate electrodes formed so as to sandwich each channel formation region, and gate insulation formed between each channel formation region and at least one of the pair of gate electrodes adjacent thereto Each channel forming region is separated from each other by any of the gate electrodes, and the gate electrodes adjacent to each channel forming region are not short-circuited to each other, and from the substrate side The odd-numbered gate electrodes are short-circuited to the first conductor connected to the first common wiring, and the even-numbered gate electrodes from the substrate side are connected to the second common wiring. The are short-circuited to the second conductor, said source region and said drain region is a semiconductor region respectively continuous over the plurality of channel forming regions, of the even and odd from the substrate side There are a plurality of the gate electrodes, and the first common wiring to which the odd-numbered gate electrodes are connected and the second common wiring to which the even-numbered gate electrodes are connected are independent from each other. characterized in that there.

  Further, it is preferable that the gate insulating film is formed between each of the channel forming regions and the pair of gate electrodes adjacent to the channel forming regions.

  The gate electrode disposed between the pair of channel forming regions adjacent to each other can be a common gate electrode for both of the pair of channel forming regions.

  Furthermore, the first conductors that short-circuit the odd-numbered gate electrodes from the substrate side are insulated from the even-numbered gate electrodes by the first insulator sidewalls erected on the substrate, The second conductors that short-circuit the even-numbered gate electrodes from the substrate side are configured to be insulated from the odd-numbered gate electrodes by a second insulator side wall standing on the substrate. be able to.

  The channel formation region is preferably formed of a single crystal semiconductor layer.

The method of manufacturing a semiconductor device according to the present invention includes a step of alternately stacking a first semiconductor layer made of a first material and a second semiconductor layer made of a second material on a substrate, Embedding a second semiconductor layer in an insulator; selectively removing the first semiconductor layer to form a cavity in the insulator; and embedding a gate electrode material in the cavity; Forming a gate electrode by removing the unnecessary gate electrode material, and forming a first conductor so as to connect to the odd-numbered gate electrode from the substrate side and not to the even-numbered gate electrode. And a step of forming a second conductor so as to be connected to the even-numbered gate electrodes from the substrate side and not connected to the odd-numbered gate electrodes .

  In this case, the step of alternately stacking the first semiconductor layer and the second semiconductor layer on the substrate includes the step of forming the single crystal on the first semiconductor layer formed on the substrate. The second semiconductor layer and the first semiconductor layer can be alternately epitaxially grown sequentially.

  According to the present invention, in a multilayer channel type MISFET, gate electrodes that are not short-circuited with each other are provided above and below each semiconductor layer in which a channel is formed, and the voltage applied to these gate electrodes is independently controlled, thereby achieving high integration. In addition to the high driving capability, it is possible to provide a semiconductor device having threshold voltage variability.

It is a conceptual diagram which shows the structure of the multilayer channel type | mold MISFET which concerns on embodiment of this invention, (c) is the top view, (a) is AA sectional drawing shown in (c), (b) is (c). It is BB sectional drawing shown in FIG. In this embodiment, it is a conceptual diagram which shows the case where a semiconductor layer is three layers, (a) is sectional drawing equivalent to Fig.1 (a), (b) is sectional drawing equivalent to FIG.1 (b). . It is a conceptual diagram which shows the manufacturing method of this embodiment. It is a conceptual diagram which shows the manufacturing method of this embodiment following FIG. It is a conceptual diagram which shows the manufacturing method of this embodiment following FIG. It is a conceptual diagram which shows the manufacturing method of this embodiment following FIG. It is a conceptual diagram which shows the manufacturing method of this embodiment following FIG. It is a conceptual diagram which shows the formation method of the contact conductor for gate electrodes in this embodiment. It is a conceptual diagram which shows the structure of the conventional MISFET disclosed by patent document 1 and 2, (c) is the top view, (a) is AA sectional drawing shown in (c), (b) is (c) It is BB sectional drawing shown to).

Explanation of symbols

1; substrates 2a, 2b, 2c; semiconductor layers 3a, 3b; source / drain regions 4; gate insulating films 5a, 5b, 5c, 5d; gate electrodes 7a, 7b; conductors 11, 12; body

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a conceptual diagram showing the structure of a multilayer channel MISFET according to an embodiment of the present invention, where (c) is a plan view thereof, (a) is a cross-sectional view taken along line AA shown in (c), and (b). FIG. 4 is a cross-sectional view taken along the line B-B shown in FIG.

  As shown in FIG. 1A, in this embodiment, a gate electrode 5c is formed on a substrate 1, and a semiconductor layer 2b is formed on the gate electrode 5c with a gate insulating film 4 interposed therebetween. ing. A gate electrode 5b is formed on the semiconductor layer 2b through a gate insulating film 4, and a semiconductor layer 2b is formed on the gate electrode 5b through a gate insulating film 4. Further, a gate electrode 5a is formed on the semiconductor layer 2b with a gate insulating film 4 interposed therebetween. The semiconductor layers 2a and 2b are thin semiconductor layers in which the channel of the MISFET is formed. In this way, the semiconductor layers 2b and 2a are sequentially stacked on the substrate 1 while being spaced apart from each other. Yes.

  As shown in FIG. 1B, the odd-numbered gate electrodes 5a and 5c from the substrate side are short-circuited to each other through a conductor 7a and connected to a wiring (not shown). The even-numbered gate electrode 5b from the substrate side is connected to a wiring (not shown) via another conductor 7b. In other words, the odd-numbered gate electrodes from the substrate side are short-circuited to form the first gate electrode, and the even-numbered gate electrodes from the substrate side are short-circuited to form the second gate electrode. The first gate electrode and the second gate electrode are independent gate electrodes so as not to short-circuit the even-numbered gate electrode and the even-numbered gate electrode. However, in this embodiment, since there is only one even-numbered gate electrode, a plurality of gate electrodes are not short-circuited to each other. The conductor 7a is insulated from the even-numbered gate electrode 5b by an insulator side wall (not shown). Similarly, the conductor 7b is insulated from the odd-numbered gate electrode 5a by an insulator side wall (not shown). The insulator sidewall will be described in detail in the manufacturing method of the present embodiment described later.

  As shown in FIG. 1A, two opposing side surfaces of semiconductor layers 2a and 2b (two side surfaces provided opposite to each other in the left-right direction in the illustrated example) are common to both semiconductor layers. The other side surface of one source / drain region 3a is connected to another source / drain region 3b common to both semiconductor layers. The source / drain regions 3a and 3b are doped N-type. As shown in FIG. 1B, source / drain contact conductors 6a and 6b are provided on the source / drain regions 3a and 3b, respectively. As described above, a single MISFET having the fourth terminal is configured.

  The substrate 1 is preferably made of an insulating material at least on the surface thereof. However, if the surface of the substrate 1 has a polarity opposite to that of the source / drain regions (P-type in the N-channel MISFET) so that the source / drain regions 3a and 3b are not short-circuited with each other, the surface or the whole of the substrate 1 is made of a semiconductor. You can also The entire source / drain region is preferably a semiconductor, but at least a partial region may be made of metal. In particular, a metal source / drain transistor may be formed by using a metal in a region in contact with the channel region.

  Next, the operation of this embodiment will be described. A channel is formed in the semiconductor layers 2a and 2b when the potentials of the first and second gate electrodes are sufficiently high, and the source / drain regions 3a and 3b are electrically connected. When the potentials of the first and second gate electrodes are sufficiently low, no channel is formed, and the source / drain regions 3a and 3b are electrically disconnected. In this way, the ON current of the MISFET can be obtained as the sum of the currents flowing through the respective channels. The first gate electrode can be a main gate electrode, and the second gate electrode can be an auxiliary gate electrode for threshold voltage control, that is, a fourth electrode. Increasing the potential of the auxiliary gate lowers the threshold value for the main gate, and decreasing the potential of the auxiliary gate increases the threshold value for the main gate. The roles of the first gate and the second gate may be interchanged. Further, the MISFET of FIG. 1 is considered to be a parallel connection of a first MISFET having a first gate electrode as a gate electrode and a second MISFET having a second gate electrode as a gate electrode. It is also possible to use it.

  According to the present embodiment, a plurality of semiconductor layers each having a channel are stacked so as to be spaced apart from each other, and the first gate electrode and the second gate independent of each other above and below each semiconductor layer. By arranging the electrodes, it is possible to realize a semiconductor device capable of variably controlling the threshold voltage in addition to high integration and high driving force.

  Further, when N double gate MISFETs (having gate electrodes above and below each semiconductor layer) are simply stacked, the number of gate electrodes is 2N. However, in this embodiment, one layer of gate electrode is shared by the upper and lower semiconductor layers. For this reason, when the number of semiconductor layers is N, the number of necessary gate electrode layers is N + 1, the number of manufacturing steps is reduced, and the total thickness of the stacked layers is reduced.

  In the present embodiment, the gate insulating film 4 is provided between the semiconductor layer 2a and the gate electrodes 5a and 5b disposed above and below the semiconductor layer 2a. A gate insulating film 4 is also provided between the arranged gate electrodes 5b and 5c. However, the gate insulating film 4 may not necessarily be interposed between the gate electrode corresponding to the back gate (substrate potential side of the planar FET) and the semiconductor layer. That is, it is not always necessary to provide a gate insulating film between the gate electrode corresponding to the substrate side and the semiconductor layer, and no insulating film is provided between the second gate electrode as the auxiliary gate electrode and the semiconductor layer. Such a configuration is also possible.

  In the present embodiment, the odd-numbered gate electrodes from the substrate side are configured as the first gate electrodes short-circuited with each other, and the even-numbered gate electrodes from the substrate side are configured as the second gate electrodes short-circuited with each other. The gate electrodes can be connected to mutually independent wirings, and the applied voltage can be controlled independently.

  FIG. 1 shows a case where there are two semiconductor layers. FIG. 2 shows a case where there are three semiconductor layers. FIG. 2 is a conceptual diagram showing a case where the semiconductor layer has three layers in this embodiment, (a) is a cross-sectional view corresponding to FIG. 1 (a), and (b) is equivalent to FIG. 1 (b). It is sectional drawing. As shown in FIGS. 2 (a) and 2 (b), odd-numbered gate electrodes 5b and 5d from the substrate side are short-circuited to each other via a conductor 7a to form a first gate electrode. The even-numbered gate electrodes 5a and 5c are short-circuited to each other via the conductor 7b to form a second gate electrode, and the odd-numbered gate electrode and the even-numbered gate electrode are not short-circuited to each other. The gate electrode and the second gate electrode can be independent gate electrodes. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The same can be realized when there are four or more semiconductor layers. With such a configuration, the degree of integration and driving force can be further improved.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG. 3 thru | or FIG. 3 to 7 are conceptual diagrams showing the manufacturing method of the present embodiment in the order of steps, where (c) is a plan view thereof, (a) is a cross-sectional view taken along line AA in (c), and (b) is FIG. It is BB sectional drawing in (c). In order to form a structure as shown in FIGS. 3 and 4, first, a gate electrode is formed on a substrate, then a gate insulating film is formed thereon, and then a semiconductor layer is formed thereon. Thus, a method of forming the constituent layers of the MISFET sequentially from the bottom can be considered. However, with such a method, the semiconductor layers 2a and 2b shown in FIG. 1 cannot be formed into a single crystal. This is because the base layer on which the semiconductor layer is deposited is a gate insulating film, but the gate insulating film (silicon oxide film or the like) is usually amorphous, and when a semiconductor is deposited thereon, the semiconductor is amorphous or polycrystalline. It becomes. Although amorphous or polycrystalline can be used for the channel portion of the MISFET, the driving capability and the uniformity of characteristics are significantly deteriorated as compared with the single crystal.

  Therefore, since the semiconductor layer forming the channel is a single crystal, the MISFET of this embodiment can be manufactured as follows. First, the structure of FIG. 3 is formed. That is, as shown in FIG. 3, a semiconductor layer 11 made of a first material (for example, SiGe (silicon germanium)) and a semiconductor layer 12 made of a second material (for example, Si (silicon)) are formed on the substrate 1. They are alternately deposited. The semiconductor layers 11 and 12 are both single crystals. The semiconductor layer 12 is retracted laterally from the semiconductor layer 11. The semiconductor layer 12 becomes the semiconductor layers 2a and 2b in which channels are formed later. The semiconductor layer 11 functions as a mold.

  In order to form the structure of FIG. 3, first, a silicon-on-insulator (SOI) substrate in which a single crystal semiconductor layer 11 is formed on the entire surface of the substrate 1 or a silicon germanium on insulator (SGOI) substrate is used. . A method for manufacturing an SOI substrate or an SGOI substrate is known. For example, when starting from the SGOI substrate, the SiGe layer originally on the SGOI substrate becomes the lowermost semiconductor layer 11. On this, the semiconductor layer 12 and the semiconductor layer 11 are epitaxially grown sequentially. In the example of FIG. 3, the semiconductor layer 12 and the semiconductor layer 11 are deposited twice each. In the epitaxial growth, since the periodicity of the base semiconductor crystal is inherited by the upper layer, the semiconductor layer 12 and the semiconductor layer 11 can all be single crystals. Next, the deposited multilayer semiconductor is processed into a desired planar shape using lithography and etching. In FIG. 3, it is processed into a horizontally long rectangle. Next, the semiconductor layer 12 is selectively retracted in the lateral direction. Further, an insulator 13 is deposited so as to embed all of the semiconductor layers 11 and 12 to obtain the structure of FIG. In FIG. 3C, the uppermost insulator 13 is seen through to show the state of the lower layer.

  Next, the semiconductor layers 11 and 12 and the insulator 13 are shaped so as to leave the range shown in FIG. Next, only the semiconductor layer 11 is selectively retracted in the lateral direction to obtain the structure of FIG. In FIG. 4C, the uppermost insulator 13 is seen through to show the state of the lower layer.

  Next, the semiconductor layers 11 and 12 are again embedded in the insulator 14. The insulator 14 includes a remaining portion of the insulator 13. Next, holes for forming the source / drain regions 3a and 3b are provided in the insulator 14, and a semiconductor is embedded in the holes to form the source / drain regions 3a and 3b (FIG. 5). The source / drain regions 3a and 3b can be formed by epitaxial growth using the semiconductor layer 12 as a seed. In this case, at least a part of the source / drain regions 3a and 3b can be a single crystal. Impurity doping is appropriately performed on the source / drain regions 3a and 3b by ion implantation or impurity mixing during deposition to make the source / drain regions 3a and 3b N-type. Thereby, the structure of FIG. 5 is obtained. In FIG. 5C, the uppermost insulator 14 is seen through to show the state of the lower layer.

  Next, the semiconductor layers 11 and 12 and the source / drain regions 3a and 3b are buried in the insulator 15 again (FIG. 6). Next, a hole is formed in the insulator 15 from above so that a part of the semiconductor layer 11 is exposed in all the layers inside the hole. For example, a hole reaching the substrate 1 is formed in a circular two-dot chain line portion in FIG. Next, the entire semiconductor layer 11 is removed from the hole by isotropic etching. Next, the gate insulating film 4 is formed on at least the surface of the semiconductor layer 12 in the cavity after the semiconductor layer 11 is removed. The gate insulating film 4 is formed by oxidizing the semiconductor layer 12 or chemical vapor deposition of an insulator. Next, the inside of the cavity is filled with the gate electrode material 5. Next, the gate electrode material 5 formed in the hole provided in the insulator 15 is removed, and the hole is backfilled to obtain the structure of FIG.

  Next, a conductor 7a for connecting the odd-numbered gate electrode layer from the substrate side to the wiring and a conductor 7b for connecting the even-numbered gate electrode layer from the substrate side to the wiring are formed. First, a hole reaching the lowermost gate electrode layer to be connected is provided at a location where the conductor 7a of the insulator 15 is to be formed. Next, an insulator covering the inside of the hole is deposited, and this is anisotropically etched to provide an insulator side wall 8a at the bottom of the hole. Next, a conductor is embedded in the hole to form a conductor 7a. Thus, the conductor 7a is connected only to the odd-numbered gate electrode, and is insulated from the even-numbered gate electrode by the insulator side wall 8a. Next, a hole reaching the lowermost gate electrode layer to be connected is provided at a location where the conductor 7b of the insulator 15 is to be formed. Next, an insulator covering the inside of the hole is deposited, and this is anisotropically etched to provide the insulator side wall 8b at the bottom of the hole. Next, a conductor is embedded in the hole to form a conductor 7b. Thus, the conductor 7b is connected only to the even-numbered gate electrode, and is insulated from the odd-numbered gate electrode by the insulator sidewall 8b. The source / drain contact conductors 6a and 6b for connecting the source / drain regions 3a and 3b to the wirings are also formed by making holes in the insulator 15 and burying the conductors therein. Thus, the structure of FIG. 7 is obtained. The structure of FIG. 7 is equivalent to the structure of FIG. 1, the semiconductor layer 12 corresponds to the semiconductor layers 2a and 2b, and the gate electrode material 5 constitutes the gate electrodes 5a, 5b and 5c.

When SiGe is used as the semiconductor layer 11 and Si is used as the semiconductor layer 12, SF ₆ , H ₂ , and CF ₄ are used in the step of selectively retracting the semiconductor layer 12 in the lateral direction to obtain the structure of FIG. Dry etching using a mixed gas of can be used. Further, wet etching using a mixed aqueous solution of peracetic acid and hydrogen fluoride can be used in the step of selectively retracting the semiconductor layer 11 in the lateral direction to obtain the structure of FIG. Further, wet etching using a mixed aqueous solution of peracetic acid and hydrogen fluoride can also be used in the step of selectively removing the semiconductor layer 11 and forming a cavity in which the gate electrode is embedded.

  According to the manufacturing method of this embodiment, a multilayer channel MISFET can be manufactured so that a semiconductor layer in which a channel is formed is a single crystal.

  The manufacturing method in the case where there are two semiconductor layers has been described above, but the same manufacturing method can be applied even in the case where there are three or more semiconductor layers. However, a method of forming a conductor that selectively connects only odd-numbered or even-numbered gate electrode layers may be performed as described below. As shown in FIG. 8, first, contact holes are made up to the lowest gate electrode layer to be connected. Next, the insulator sidewall 8 is formed on the side surface from the lowermost layer to the second layer upward. Next, the conductor 7 is filled in the contact hole. However, at this time, the conductor 7 is filled up to a depth that is connected to the third layer upward from the lowermost layer but not connected to the fourth layer upward. As a result, the structure shown in FIG. Thereafter, when a step of forming a sidewall insulator and filling the conductor is performed, the structure of FIG. 8B can be obtained. If the formation of the insulator side wall and the filling of the conductor are repeated as appropriate, it is possible to form a conductor that selectively connects only the odd-numbered or even-numbered gate electrode layers with respect to the arbitrary number of layers.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2006-226821 for which it applied on August 23, 2006, and takes in those the indications of all here.

  The semiconductor device according to the present invention can be suitably mounted on various integrated circuits.

Claims (7)

A substrate, a source region and a drain region formed on the substrate, a plurality of channel formation regions stacked on the substrate so as to be spaced apart from each other, and the channel formation regions A plurality of gate electrodes formed so as to sandwich the gate electrode, and a gate insulating film formed between each of the channel forming regions and at least one of the pair of gate electrodes adjacent thereto, Each channel formation region is separated from each other by one of the gate electrodes, the gate electrodes adjacent to each channel formation region are not short-circuited to each other, the odd-numbered gate electrodes from the substrate side, Shorted to the first conductor connected to the first common wiring, the even-numbered gate electrode from the substrate side is short-circuited to the second conductor connected to the second common wiring. Cage, and said source region and said drain region, said a plurality of semiconductor regions each continuous over the channel formation region, the even and odd of the gate electrode from the substrate side is more respectively, and an odd The semiconductor device, wherein the first common wiring to which the th-th gate electrode is connected and the second common wiring to which the even-numbered gate electrodes are connected are independent from each other . 2. The semiconductor device according to claim 1, wherein the gate insulating film is formed between each of the channel formation regions and a pair of the gate electrodes adjacent to the channel formation region. The gate electrode disposed between a pair of channel formation regions adjacent to each other is a gate electrode common to both of the pair of channel formation regions. Semiconductor device. The first conductors that short-circuit the odd-numbered gate electrodes from the substrate side are insulated from the even-numbered gate electrodes by first insulator sidewalls erected on the substrate, and from the substrate side. The second conductor for short-circuiting the even-numbered gate electrodes to each other is insulated from the odd-numbered gate electrodes by a second insulator side wall provided upright on the substrate. 2. The semiconductor device according to 1. The semiconductor device according to claim 1, wherein the channel formation region is formed of a single crystal semiconductor layer. A step of alternately stacking a first semiconductor layer made of a first material and a second semiconductor layer made of a second material on a substrate; and burying the first and second semiconductor layers in an insulator. A step of selectively removing the first semiconductor layer to form a cavity in the insulator; a step of embedding a gate electrode material in the cavity; and a gate by removing unnecessary gate electrode material. Forming an electrode; forming a first conductor so as to connect to an odd-numbered gate electrode from the substrate side and not connect to an even-numbered gate electrode; and Forming a second conductor so as to be connected to the gate electrode and not to be connected to the odd-numbered gate electrode . The step of alternately stacking the first semiconductor layer and the second semiconductor layer on the substrate includes the step of stacking the second semiconductor on the single-crystal first semiconductor layer formed on the substrate. 7. The method of manufacturing a semiconductor device according to claim 6 , wherein layers and the first semiconductor layer are alternately and epitaxially grown sequentially.

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