JPH0465868A - Mos transistor - Google Patents

Abstract

PURPOSE:To increase drain current and realize high speed operation, by forming a first and a second channels of a first conductivity type on both sides of a gate electrode via a first and a second gate insulating films, and forming a source region and a drain region of a second conductivity type so as to interpose the first and the second channel. CONSTITUTION:A second gate insulating film 11 is formed on the upper surface side of a gate electrode 5, and a second channel 12 of P-type is formed on the upper surface side of the gate insulating film 11. A second drain region 13 and a second sourfe region 14 in contact with the source region 6 and a drain region 7 are formed on both sides of the second channel 12. Thereby a device equivalent to the constitution wherein two MOS type transistors M1 and M2 are connected in parallel is obtained, and the drain current can be remarkably increased as compared with a usual MOS type transistor. Further the increase of cell area viewed from a plane can be prevented. As the result, high degree integration is enabled, and high speed operation is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS transistor, and particularly to a MOS transistor that can obtain a large drain current.

[Conventional technology]

This type of MOS transistor is shown in Fig. 8(a).
As shown in and (b), for example, a gate electrode 5 is formed through a gate insulating film 4 in the center of an element formation region 3 surrounded by element isolation insulating films 2a and 2b formed on a p-type semiconductor substrate 1. are formed, and an n-type source region 6 and drain region 7 are formed on the surface of the semiconductor substrate 1 except under the gate insulating film 4, and a channel 8 is formed between these source region 6 and drain region 7. ing.

By the way, in order to increase the speed by integrating MOS transistors, it is necessary to increase the drain current flowing through the channel 8.

In order to increase this drain current, conventionally, the drain current I is increased. is the value obtained by dividing the channel width W by the channel length (W
/L), and among these, the minimum value of channel length is determined by the process, so by widening the channel width W, the drain current ■.

We are trying to increase this.

[Problems to be Solved by the Invention] However, in the conventional MOS transistor described above, the drain current is increased by widening the channel width W. There was an unresolved problem that the cell area of the transistor increased, making it difficult to achieve high integration.

For example, in a CMOS transistor, in order to achieve high integration, 2 & 11 source regions and drain regions of different conductivity types are formed above and below the gate electrode.
It is known to construct a stacked CMOS inverter (see Japanese Patent Publication No. 60-51272, etc.).

This stacked CMOS inverter is simply an n-channel MO
S) By stacking transistors and P-channel MOS transistors, the cell area is the same as that of a normal MOS transistor, and high integration is achieved.
No consideration is given to increasing the drain current of the MO5 type transistor to increase its speed.

Therefore, the present invention has been made by focusing on the unresolved problems of the conventional example, and aims to increase the drain current without increasing the channel width W, thereby increasing the speed without impairing high integration. It is an object of the present invention to provide a MOS type transistor that can achieve the following.

[Means to solve the problem]

In order to achieve the above object, a MOS transistor according to the present invention has first and second channels of a first conductivity type formed on both sides of a gate electrode via first and second gate insulating films. and a source region and a drain region of a second conductivity type are formed sandwiching the first and second channels.

[Effect]

In the present invention, by forming a channel, a source region, and a drain region on both sides of a gate electrode, two
This is equivalent to forming two MOS transistors in parallel, and the drain current can be significantly increased compared to a normal MOS transistor, while also preventing the cell area from increasing when viewed from the plane. .

As a result, it is possible to achieve high integration and high speed.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention.

In the figure, 1 is a semiconductor substrate having a p-type first conductivity type, 2
a and 2b are element isolation insulating films formed on the surface of the semiconductor substrate 1; 3 is an element formation region; 4 is a first gate insulating film;
5 is a gate electrode, 6 and 7 are first drain and source regions having a second conductivity type of n'' type, and 8 is a first channel, and these structures are similar to the conventional example described above. It has a configuration.

In the first embodiment, a second electrode is provided on the upper surface side of the gate electrode 5.
A p-type second channel 12 is formed on the upper surface side of the gate insulating film 11, and the source region 6 and drain region 7 are formed on both sides of the second channel 120. Contacting second drain region 1
3 and a source region 14 are formed.

Next, a method of manufacturing a MOS type transistor having the above structure will be explained with reference to FIG.

First, a semiconductor substrate 1 made of a p-type silicon substrate containing boron as an impurity is prepared, and on the surface of this semiconductor substrate 1,
70 by LOCO3 method, pyrogenic oxidation method, etc.
By forming field insulating films 2a and 2b having a thickness of approximately 0 nm, an element formation region 3 surrounded by these is formed (see FIG. 2(a)).

Next, a gate insulating film 4 made of a thin silicon oxide film of about 30 nm is formed on the surface of the semiconductor substrate 1 by, for example, an oxygen atmosphere oxidation method, and then a low pressure CVD method using monosilane as a reactive gas is formed on the gate insulating film 4. The polycrystalline silicon film that will become the gate electrode 5 has a film thickness of 400 mm.
After stacking the layers to a thickness of approximately 100 nm, photoetching is performed to pattern the gate electrode portion leaving only the gate electrode portion, thereby forming the gate electrode 5 (see FIG. 2(b)).

Next, using the gate electrode 5 as a mask, the silicon 7 substrate 1 is
Arsenic 60keV, F-su amount 5X10'Sa
By forming an n+ type first drain region 6 and source region 7 by ion implantation at toms/di, a MOS transistor similar to the conventional example is constructed (see FIG. 2(C)).

Next, a thin silicon oxide film of about 30 nm is formed on the semiconductor substrate 1 and the gate electrode 5 by an oxygen atmosphere oxidation method, and a first drain region 6 and a source region are formed on the semiconductor substrate 1 by photoetching this silicon oxide film. A portion corresponding to 7 is removed to form a second gate insulating film 11 (see FIG. 2(d)).

Next, the upper surface of the semiconductor substrate 1 and the second gate insulating film 1
Low pressure CVD using monosilane as the reaction gas on 1
A polycrystalline silicon film 21 that will become the second channel 12 is formed with a thickness of about 150 rv by a method, and 25 k of boron as a p-type impurity is applied to the entire surface of this polycrystalline silicon film 21.
After ion implantation at a dose of 2×10” atoms/cIII at a dose of 2×10” eV, the polycrystalline silicon film on the field insulating films 2a and 2b is removed by photoetching and a second MOS transistor is patterned (
(See Figure 2(e)).

Next, after masking the second channel 12 with a photomask, arsenic is added as an n-type impurity into the polycrystalline silicon film 21 at 80 keV and at a dose of 5×10”ato.
The second drain region 1 is formed by ion implantation at ms/cTll.
3 and a source region 14 are formed, and then annealing is performed at 1000'C for 10 seconds using a lamp annealing method to activate the impurities and obtain the desired multilayer MOS transistor shown in FIG.

As described above, according to the first embodiment, channels 8 and 12 are formed on both upper and lower surfaces of the gate electrode 5 formed in one element formation region 3 with the gate insulating films 4 and 11 interposed therebetween. Drain regions 6 on both sides of 120,
13 and source regions 7.14 are formed, these drain regions 6.13 and source regions 7, 14 are formed.
Since they are in contact with each other and can be regarded as electrically one drain and source, equivalently, as shown in FIG. 3, two MOS transistors M1 and M2 have a common gate electrode, The sources are connected in parallel to each other, and when a gate voltage is applied to the gate electrode 5, the drain current I, flowing from the drain region 6, 13 to the source region 7, 14, the channel 8,
The drain current IDI flowing through 12 and 1. It is the sum of

Here, the multilayer MOS transistor of the first embodiment and the conventional MOS transistor have the same channel width of 30 μm,
Assuming the same channel length of 2 μm, drain voltage ■. and drain current 1. Figure 4 shows the results of measuring the relationship between

As is clear from FIG. 4, the multilayer MO of the first embodiment
The drain voltage-drain current characteristics of an S-type transistor are approximately 1.
It is possible to obtain 6 times the drain current ID, and at this time,
Since the overall cell area seen from the plane is the same, high speed can be achieved without sacrificing high integration.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this second embodiment, the MOS transistor is further multilayered to further increase the drain current.

That is, a second gate electrode 26 surrounded by a gate insulating film 25 is arranged on the upper part of the multilayer MOS transistor of the first embodiment described above, and a channel 27, a drain region 28, and a source region are formed on the upper surface side of this gate electrode 26. 29, the gate electrode 5 and the second gate electrode 2
6 is electrically connected outside the element formation region.

According to this second embodiment, two gate electrodes 5 and 26
Since a channel, a drain region, and a source region are individually formed on both sides of the MOS transistors, equivalently, as shown in FIG. The configuration is such that they are connected in common and connected in parallel, and the drain current is 2 compared to the first embodiment.

can be further increased, and in this case as well, the overall cell area seen from the plane is equal to that of a conventional MOS type transistor, so higher speeds can be achieved without sacrificing high integration.

Next, a third embodiment of the present invention will be described with reference to FIG.

This third embodiment is configured as a lateral type MOS transistor.

That is, as shown in FIG. 7, a p-type silicon substrate 1
A wide n° type drain region 31 is formed on the upper surface by ion implantation of arsenic as an n-type impurity, and a polygonal region surrounded by a thin gate insulating film 32 is formed on the upper surface corresponding to the center of this drain region 31. A gate electrode 33 made of a crystalline silicon film is formed, and a channel 34 is formed on both sides of this gate electrode 330 by implanting boron as a p-type impurity into a polycrystalline silicon film. It has a configuration in which a source region 35 is formed wider than the gate electrode 33 into which arsenic as a type impurity is ion-implanted.

Also in this third embodiment, a channel 34 is formed on both sides of a gate electrode 33, and a drain region 31 and a source region 35 are formed in the vertical direction with the channel 34 in between, so that equivalently, as shown in FIG. Similarly, the configuration is such that two MOS type transistors are connected in parallel, and the same effects as in the first embodiment described above can be obtained.

In each of the above embodiments, the present invention is applied to an n-channel M
OS) We have explained the case where it is applied to transistors, but
Not limited to this, p-channel MOSI-
It goes without saying that the present invention can also be applied to transistors.

〔Effect of the invention〕

As explained above, according to the MOS transistor according to the present invention, the first and second channels are formed on the opposing surfaces of the gate electrode with the gate insulating film interposed therebetween, and the source region and Since the structure is configured to form a drain region, it is equivalent to a structure in which multiple MOS transistors are connected in parallel, so when the cell area is the same as that of the conventional example, the drain current is lower than that of the conventional example. In comparison, it is possible to significantly increase the number of circuits, and it is possible to achieve the effect that high speed can be achieved without impairing high integration.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG.
) to (e) are process diagrams showing the manufacturing process of the first embodiment, and the third
The figure is an equivalent circuit diagram of the first embodiment, FIG. 4 is a characteristic diagram showing the measurement results of the drain voltage-drain current characteristics in the first embodiment and the conventional example, and FIG. 5 is the equivalent circuit diagram of the second embodiment of the present invention. 6 is an equivalent circuit diagram of the second embodiment, FIG. 7 is a sectional view of the third embodiment of the present invention, and FIGS. 8(a) and (
b) is a sectional view and a plan view, respectively, showing a conventional example. In the figure, 1 is a semiconductor substrate, 2a and 2b are insulating films for element isolation, 3 is an element formation region, 4 is a first gate insulating film, 5 is a gate electrode, 6 is a drain region, 7 is a source region, and 8 is a channel, 11 is a second gate insulating film, 12 is a second channel, 13 is a second drain region, 14 is a second source region, 31 is a drain region, 32 is a gate insulating film, 34
is a channel, and 35 is a source region. Figure 5 Figure 6 To--1

Claims (1)

[Claims] First and second channels of the first conductivity type are formed on both sides of the gate electrode via first and second gate insulating films, and a second channel is formed with the first and second channels in between. A MOS type transistor characterized in that a conductive type source region and drain region are formed.