JPS627148A - Complementary semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a parasitic MOS inversion leakage by providing a gate electrode formed through source and drain regions formed on a substrate surrounded by an element separating region and on the surface of a well element region, a high density impurity layer and a gate oxide film. CONSTITUTION:A P-well 22 is formed on the surface of an N-type silicon substrate 21, and N<+> type source and drain regions 29, 30 are formed on the well 22 element region. A parasitic leakage preventing P<+> type region 33 is formed to the place where it is suitably separated from a boundary of the source and drain regions 29, 30 near the edge of the field oxide film 23 of the element region, and a gate electrode 27 is formed through a gate oxide film 24 on the element region. Since the region 33 is not extended underneath the film 23, the region 33 is not formed before the field oxidation to reduce the number of steps and to avoid the contamination of a field oxide furnace. The parasitic MOS inversion leakage current can be prevented due to the presence of the region 33.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary semiconductor device and a method for manufacturing the same, and more particularly to a CMO3 semiconductor device used in an environment exposed to radiation and a method for manufacturing the same. (Technical Background of the Invention) Conventionally, in an n-channel MOS transistor, the
Exposure to Ai causes an anomalous MO8 inversion leakage current. Therefore, in order to reduce this leakage current, an n-channel MOS transistor shown in FIG. 5 has been proposed (T, V, N0rdStrO1, and F, W
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1 in the figure is a P-type silicon substrate. This board 1
A field oxide film 2 is formed on the surface. In the device region surrounded by this field oxide 112, N+
Type source and drain regions 3.4 are formed. A P+ region 5 for preventing parasitic leakage is formed under the field oxide film 2 and in a region close to the element region. This P+ region 5 is formed before field oxide film 2 is formed. On the element region, a gate electrode 7 made of polycrystalline silicon is formed via a gate oxide 116 via field oxidation II! It is formed so as to extend over 2.

(Problems of the Background Art) However, the prior art has the following problems.

■ To form the P+ region 5 for preventing accidental leaks,
Requires mask alignment and ion implantation process, compared to normal CM
The number of steps is increased compared to the O8L-8I process.

(2) Field oxidation [Since the P+ region 5 is formed before the formation of the field oxidation furnace 12, the field oxidation furnace is contaminated.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of reducing parasitic MO8 inversion leakage caused by radiation irradiation, and
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that requires fewer steps and less contamination of a furnace.

[Summary of the invention]

One invention of the present invention includes a semiconductor substrate of a first conductivity type, an in region, a high concentration impurity layer provided in the same element region and in the direction of the channel, and a gate oxide film provided on the same element region. The device is characterized in that it includes a gate electrode provided therein, and is intended to achieve the above object.

The invention of cylinder 2 of the present application has a high concentration impurity layer formed of n-channel Mo.
The main feature is that the source and drain regions of the S transistor are formed simultaneously by introducing the same amount of n-type impurities, thereby achieving the same effect as the invention of the present invention. .

[Embodiments of the invention]

Hereinafter, a CMOS transistor according to an embodiment of the present invention will be described with reference to factors 1 (a) to (C) and FIGS. 2 to 4. Here, Fig. 1 is a process cross-sectional view, and Fig. 2 is Fig. 1 (
b) A plan view of the n-channel MOS transistor region, FIG. 3 is a plan view of the n-channel MOS transistor region of FIG. 1(C), and FIG. 4 is a plan view of the n-channel MOS transistor region of FIG. 1(C).
3A and 3B respectively show perspective views of transistor regions.

First, after forming a P well 22 on the surface of an N type silicon substrate 21, a normal L well 22 is formed on the substrate 21 and the P well 22.
A field oxide film 23 was formed by the OCO8 method. Subsequently, a gate oxide film 24 was formed on the device region surrounded by these field oxide films 23 (see FIG. 1(a)).
(Illustrated).

Next, a prescribed mask was formed by resist formation and patterning, and channel ion implantation layers 25 and 26 of different conductivity types were formed in the P well 22 and the substrate 21, respectively. Further, after forming a polycrystalline silicon layer on the entire surface, phosphorus diffusion and buttering were performed to form a gate electrode 27 for an n-channel MOS transistor and a gate electrode 28 for an n-channel MoS transistor, respectively. After that,
The well 22 is masked with the device region on the p-channel side.
An n-type impurity was introduced into the structure to form two N+ type source and drain regions 30 (as shown in FIG. 1(b) and FIG. 2).
. Note that in FIG. 1(b), N+ type source and drain regions 29, 30, . The gate electrode 27 constitutes an n-channel MoS transistor.

Next, after forming a resist over the entire surface, a portion of the resist corresponding to an element region on the p-channel side and a portion of the resist corresponding to a P+ region described later were opened. Next, using this resist as a mask, boron was applied at an acceleration voltage of 40KeV and a dose of 12X10.
Under the condition "a", the p-channel side element region and P well 2
P0 type source and drain regions 31 and 32 were formed on the surface of the substrate 21, and at the same time, a P+ region 33 was formed in the P well 22. Here, the P" region 33 is formed up to a location three degrees away from the boundary between the source and drain regions 29 and 30, and the field oxidation region 1I23
It is formed in an area of 1 m from the boundary of the element region toward the element region (as shown in FIGS. 1(C) and 3). In addition,
In FIG. 1(C), the p-channel MOS is
A transistor is configured. Next, although not shown, C
A CMOS transistor was manufactured by depositing a VD-8i02 film and an 8PSG film, reflowing, forming a contact, forming an A2 wiring, depositing a PSG film, and opening a pad.

According to the present invention, the P+ region 33 for preventing accidental leakage in the n-channel MOS transistor region is formed at the same time as the P" type square source and drain regions 31 and 32 of the p-channel M-OS transistor are formed. Therefore, compared to the conventional method, special mask alignment and ion implantation steps for forming the P+ region 33 are not required, and the number of steps can be reduced.

Furthermore, since the P+ region 33 is formed after field oxidation, contamination of the field oxidation furnace can be avoided.

Furthermore, the presence of the P+ region 33 can reduce the parasitic MO8 inversion leakage current even when exposed to radiation.

Finally, the CMOS transistor according to the above embodiment is
As shown in FIG. A P'' region 33 for preventing parasitic leakage is provided close to the edge of the oxide film 23 and appropriately spaced from the boundary between the source and train regions 29 and 30, and is further provided with a gate oxide I!lI 24 over the same element region. Therefore, since the P+ region 33 is not formed extending below the field oxide film 23, the <P" region 33 is formed before field oxidation as in the conventional method. Without this, it is possible to reduce the number of steps and avoid contamination of the field oxidation furnace. Also, P
The presence of the + region 33 can prevent parasitic MO8 inversion leakage current.

Note that the CMOS transistor according to the present invention is shown in FIG.
The same effect as described above can be obtained not only with the structure shown in C) but also with the structures shown in FIGS. 6 to 11. Here, the same members as those in the above embodiment are given the same reference numerals, and the description thereof will be omitted. In FIG. 6, the length of the P1 region 33 in the channel length direction is 1 m for the source and drain regions! It has a structure that is somewhat shortened to the boundary band of 29.30. In FIG. 7, the length of the P" region 33 in the channel length direction is somewhat shortened to the boundary zone between the source and drain regions 29, 30, and the P+ region R33 is extended from the boundary 42 between the field oxide film 23 and the device region to the device region. 8 shows a structure in which one end of the gate electrode 27 in FIG. 7 is not extended to the top of the field oxide film 23, but is provided halfway into the element region. 9, the region of the field oxide film 23 in FIG. 6 is replaced with the source and drain regions 29.3.
It has a structure that is slightly expanded in the direction of the 0 boundary. FIG. 10 shows the area of field oxide 1123 in FIG.
It has a structure in which the boundary zone between the drain regions 29 and 30 is slightly widened. FIG. 11 has a structure in which the region of the field oxide film 23 in FIG. 8 is slightly expanded to the boundary zone between the source and drain regions 29 and 30.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to reduce the parasitic MO8 inversion leakage caused by radiation irradiation, and to provide a highly reliable complementary semiconductor device and its manufacturing method with a small number of steps and less contamination of the furnace. It is.

[Brief explanation of drawings]

FIGS. 1(a) to (C) show a CMO according to an embodiment of the present invention.
Cross-sectional diagram showing the manufacturing method of the S transistor in order of steps, 2nd
The figure is a partial plan view of Figure 1(b), and Figure 3 is a partial plan view of Figure 1(b).
FIG. 4 is a partial perspective view of FIG. 1(C), FIG. 5 is a perspective view of a conventional n-channel MO5 transistor, and FIGS. 6 to 11 are each a partial plan view of FIG. FIG. 3 is a partial plan view of another CMOS transistor according to the invention. 21...N type silicon substrate, 22...P well,
23...Field oxide film, 24...Gate oxide film, 25.26...Channel ion implantation layer, 27.28
... Gate electrode, 29.31 ... Source region, 30
．． 32...Drain region, 33...p"am, 41
···boundary. (a) (b) (c) Fig. 1 Fig. V Fig. 8 Fig. 10 Fig. 9 Fig. 7 Fig. 11

Claims (2)

[Claims] (1) A semiconductor substrate of a first conductivity type, a well of a second conductivity type provided on the surface of the substrate, an element isolation region provided on the surfaces of the substrate and the well, and a semiconductor substrate surrounded by the element isolation region. A source and drain region provided on the surface of the element region of the base and well, a high concentration impurity layer provided on the surface of the same element region and spaced apart from the source and drain region in the channel width direction, and a high concentration impurity layer provided on the same element region. 1. A complementary semiconductor device comprising: a gate electrode provided through a gate oxide film; and a gate electrode provided through a gate oxide film. (2) A semiconductor substrate of a first conductivity type, a well of a second conductivity type provided on the surface of the substrate, an element isolation region provided on the surfaces of the substrate and the well, and a substrate surrounded by the element isolation region. and a source and drain region provided on the surface of the element region of the well, a high concentration impurity layer provided in the same element region and spaced apart from the source and drain region in the channel width direction, and a gate oxidation layer on the same element region. In a method for manufacturing a semiconductor device of a complementary semiconductor device having a gate electrode provided through a film, a high concentration impurity layer is introduced with the same amount of p-type impurities for forming source and drain regions of a p-channel MOS transistor. 1. A method for manufacturing a complementary semiconductor device, characterized in that the semiconductor devices are formed simultaneously.