JP2948256B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] An electrically rewritable nonvolatile memory cell formed with a tunnel oxide film is provided, and an impurity diffusion layer constituting the electrically rewritable nonvolatile memory cell is provided. A method of manufacturing a semiconductor memory device, in which an impurity diffusion layer portion below a tunnel oxide film is formed deeper than other impurity diffusion layer portions, relates to an insulated gate constituting an input / output protection circuit without increasing the number of manufacturing steps. An insulated gate field effect transistor which forms the input / output protection circuit when impurity ions are implanted to form an impurity diffusion layer portion below the tunnel oxide film. In the impurity diffusion layer of the transistor, a region where an impurity diffusion layer forming a current input path is to be formed is simultaneously implanted with the impurity ions. A diffusion layer portion is formed.

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a tunnel insulating film, for example, a tunnel oxide film (tunnel oxide film).
xide), an electrically rewritable nonvolatile memory cell, so-called EEPROM (electrically erasable and
The present invention relates to a method of manufacturing a semiconductor memory device provided with cells (programmable read only memory), that is, a so-called EEPROM.

In general, such an EEPROM is also provided with an input protection circuit and an output protection circuit in order to protect an internal circuit from a high voltage due to static electricity or the like applied to an input / output terminal, as in the case of other semiconductor integrated circuit devices.

[Prior Art] Conventionally, an EEPROM as shown in a sectional view of a main part thereof in FIG. 3 has been proposed.

In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is an EEPROM cell forming a memory cell, 4 is an n-channel insulated gate field effect transistor (hereinafter referred to as an nMOS transistor) forming an input protection circuit. So,
EEPROM cell 3, the drain region 5 composed of n ⁺⁺ diffusion layer 5A and the n ⁺ diffusion layer 5B, as with the source region 6 consisting of n ⁺ diffusion layer, a gate oxide film (SiO ₂ film) 7, a tunnel oxide film (SiO ₂ film) 8, floating gate 9 made of polysilicon, and control gate 10 also made of polysilicon. 11 and 12 are SiO ₂
The insulating films 13 and 14 are Al (aluminum) wirings. Here, the n ⁺⁺ diffusion layer 5A below the tunnel oxide film 8
Is a portion deeper than the n ⁺ diffusion layer 5B and has a higher n-type impurity concentration, in order to complete writing (accumulation of electrons in the floating gate 9).

Also, nMOS transistor 4 includes a drain region 15 made of n ⁺ diffusion layer, the source region 16 similarly made of n ⁺ diffusion layer
And a gate oxide film (SiO ₂ film) 17 and a gate 18 made of polysilicon. Note that 19 is an insulating film made of a SiO ₂ film, and 20 and 21 are Al wirings. Where nMOS
The transistor 4 has its drain region 15 connected to a signal input terminal 22 via an Al wiring 20, and its gate 18 and source region 16 grounded via an Al wiring 21. FIGS. 4 and 5 are a plan view and a circuit diagram, respectively, showing an input protection circuit comprising the nMOS transistor 4, wherein 23 indicates a contact hole and 24 indicates an internal circuit.

 Such an EEPROM is manufactured as follows.

First, as shown in FIG. 6A, a p-type silicon substrate 1 is prepared, a field oxide film 2 and gate oxide films 7 and 17 are formed in this order, and then a tunnel oxide film 8 in the gate oxide film 7 is formed.
An opening 25 is formed in a portion where a tunnel oxide film 8 is to be formed.
Is formed by thermal oxidation.

Next, as shown in FIG. 6B, formation of a polysilicon layer 26 for forming a floating gate and application of a resist 27 are sequentially performed, and an opening 28 is formed in a portion including the tunnel oxide film 8, and n-type impurities and For example, arsenic As is ion-implanted at a higher concentration and deeper than in the case where the source region 6, the drain region 15, the source region 16, and the like are formed, and n ⁺⁺
The diffusion layer 5A is formed.

Next, as shown in FIG. 6C, after forming the floating gate 9, the control gate 10, the insulating film 11, the gate 18 and the insulating film 19 of the nMOS transistor 4, an n-type impurity such as arsenic As is ion-implanted. , N ⁺⁺ diffusion layers 5A and n ⁺
Forming a drain region 5, n ⁺ drain region 15 composed of the source region 6, n ⁺ diffusion layer made of the diffusion layer, n ⁺ source region 16 composed of a diffusion layer consisting of a diffusion layer 5B.

Next, as shown in FIG. 3, after forming the insulating layer 12,
A contact hole is formed, and Al wirings 13, 14, 20, 21 are formed. Here, an EEPROM provided with an input protection circuit using the nMOS transistor 4 can be obtained.

In the EEPROM configured as described above, when a voltage of 5 [V] or more is applied to the signal input terminal 22 due to static electricity or the like, a junction (junction) immediately below the gate electrode on the drain region 15 side of the nMOS transistor 4 is broken down. ,
Since the current flows into the p-type silicon substrate 1, the internal circuit 24
Current can be prevented from flowing through the internal circuit 24, and the internal circuit 24 can be protected.

[Problems to be Solved by the Invention] However, in such a conventional EEPROM, the nMOS
Since the drain region 15 of the transistor 4 is formed shallowly, when a high voltage is applied to the signal input terminal 22,
As shown in the figure, aluminum at the junction of the Al wiring 20 with the drain region 15 is melted, penetrates through the drain region 15, and destroys the pn junction between the drain region 15 and the p-type silicon substrate 1. There was a problem that sometimes.
In this case, such a problem can be solved by forming the drain region 15 deep, but on the other hand, in order to avoid a decrease in throughput and an increase in price,
It is necessary not to increase the number of manufacturing steps. The same can be said for the output protection circuit.

In view of the above, the present invention provides an EEPROM manufacturing method capable of achieving a high breakdown voltage structure of a MOS transistor constituting an input / output protection circuit without increasing the number of manufacturing steps. Aim.

[MEANS FOR SOLVING THE PROBLEMS] A method of manufacturing an EEPROM according to the present invention comprises providing an EEPROM cell having a tunnel insulating film, and diffusing an impurity in an impurity diffusion layer constituting the EEPROM cell below the tunnel insulating film. In a method of manufacturing an EEPROM in which a layer portion is formed deeper than other impurity diffusion layer portions, when an impurity ion is implanted to form an impurity diffusion layer portion below a tunnel insulating film, a MOS constituting an input / output protection circuit is formed. In the impurity diffusion layer of the transistor, impurity ions are sometimes implanted into a region where an impurity diffusion layer forming a current input path is to be formed, thereby forming a deep impurity diffusion layer portion.

[Operation] According to the present invention, the MO constituting the input / output protection circuit is provided.
In the impurity diffusion layer of the S transistor, a deep impurity diffusion layer is also formed in a region where an impurity diffusion layer forming a current input path is to be formed. As a result, the MO that constitutes the input / output protection circuit
The breakdown voltage of the S transistor can be increased.

Moreover, according to the present invention, the deep impurity diffusion layer portion is formed simultaneously with the formation of the impurity diffusion layer portion below the tunnel insulating film. As a result, there is no increase in the number of manufacturing steps.

Embodiment An embodiment of the present invention will be described below with reference to FIG. 1 and FIG. In FIGS. 1 and 2, parts corresponding to FIGS. 3 to 7 are denoted by the same reference numerals.

In the present embodiment, first, as shown in FIG.
After a p-type silicon substrate 1 is prepared and a field oxide film 2 and gate oxide films 7 and 17 are sequentially formed, a gate oxide film 7 is formed.
An opening 25 is formed in a portion where the tunnel oxide film 8 is to be formed, and the tunnel oxide film 8 is formed by thermal oxidation.

Next, as shown in FIG. 1B, formation of a polysilicon layer 26 for forming a floating gate and application of a resist 27 are sequentially performed to form a portion including the tunnel oxide film 8 and a drain region 15 of the nMOS transistor 4. forming a respective sub-apertures 28 and 29, n-type impurity, such as arsenic As a high concentration as compared to the case of forming the source regions 6 and 16, etc., and ions are implanted over a deep range, n ⁺⁺ diffusion Layer 5A, 1
Form 5A.

Next, as shown in FIG. 1C, after forming the floating gate 9, the control gate 10, the insulating film 11, the gate 18 and the insulating film 19 of the nMOS transistor 4, an n-type impurity such as arsenic As is ion-implanted. , N ⁺⁺ diffusion layers 5A and n ⁺
Forming a drain region 5, the n ⁺ diffusion source region 6 consisting of layers, n ⁺⁺ diffusion layer 15A and the n ⁺ diffusion layer drain region 15 made of 15B, n ⁺ source region 16 composed of a diffusion layer consisting of a diffusion layer 5B.

Next, as shown in FIG. 1D, after the insulating layer 12 is formed, contact holes are formed, and Al wirings 13, 14, 20, 21 are formed.
To form Here, an EEPROM provided with an input protection circuit using the nMOS transistor 4 can be obtained.

According to this embodiment, nM constituting the input protection circuit
Deep n ⁺⁺ diffusion layer 15A in drain region 15 of OS transistor 4
Thus, even if the aluminum at the junction of the Al wiring 20 and the drain region 5 is melted by the application of a high voltage, the penetration of the drain region 15 is avoided as shown in FIG. Of the pn junction between the substrate and the p-type silicon substrate 1 can be prevented.

Moreover, according to the present embodiment, the n ⁺⁺ diffusion layer 15A is formed simultaneously when the n ⁺ diffusion layer 5A below the tunnel oxide film 8 is formed. Therefore, the EEPROM can be manufactured in the same number of steps as required for forming the EEPROM of the conventional example in FIG.

As described above, according to the present embodiment, it is possible to achieve a high breakdown voltage structure of the nMOS transistor 4 constituting the input protection circuit without increasing the number of manufacturing steps. Note that a high breakdown voltage structure of the nMOS transistor constituting the output protection circuit can be achieved in the same manner.

[Effects of the Invention] As described above, according to the present invention, when impurity ions are implanted to form the impurity diffusion layer portion below the tunnel insulating film, the impurity diffusion layer of the MOS transistor constituting the input / output protection circuit is In addition, since a method of simultaneously implanting impurity ions into a region where an impurity diffusion layer forming a current input path is to be formed and forming a deep impurity diffusion layer portion is employed, the number of manufacturing steps is increased. In addition, a high breakdown voltage structure of the MOS transistor constituting the input / output protection circuit can be achieved.

[Brief description of the drawings]

1A to 1D are cross-sectional views showing a method for manufacturing an EEPROM according to an embodiment of the present invention, FIG. 2 is a cross-sectional view for explaining the effect of the embodiment of the present invention, and FIG. FIG. 4 is a plan view showing an input protection circuit composed of an nMOS transistor, FIG. 5 is a circuit diagram showing an input protection circuit composed of an nMOS transistor, and FIGS. FIG. 7 is a cross-sectional view showing a conventional EEPROM manufacturing method. FIG. 7 is a cross-sectional view for explaining the problems of the conventional EEPROM shown in FIG. 3 ... EEPROM cell 4 ... nMOS transistor 5 ... drain region of EEPROM cell 6 ... source region of EEPROM cell 15 ... drain region of nMOS transistor 16 ... source region of nMOS transistor

Continuation of the front page (56) References JP-A-62-25458 (JP, A) JP-A-64-68973 (JP, A) JP-A-63-306771 (JP, A) JP-A-57-155771 (JP) , A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/788-29/792 H01L 21/8247 H01L 27/10-27/115 H01L 21/8239-21/8247

Claims (1)

(57) [Claims] An electrically rewritable nonvolatile memory cell having a tunnel insulating film is provided, and in an impurity diffusion layer constituting the electrically rewritable nonvolatile memory cell, a portion below the tunnel insulating film. In a method of manufacturing a semiconductor memory device in which an impurity diffusion layer portion is formed deeper than other impurity diffusion layer portions, an input / output protection is performed when impurity ions are implanted to form an impurity diffusion layer portion below the tunnel insulating film. In the insulated gate field effect transistor constituting the circuit, the impurity ions are simultaneously implanted into a region where an impurity diffusion layer forming a current input path is to be formed, thereby forming a deep impurity diffusion layer portion. A method for manufacturing a semiconductor memory device, characterized by: