JP2817518B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a p + region and an n + region are mixed in the same polysilicon film constituting a polycide film.

[0002]

2. Description of the Related Art In recent years, in order to miniaturize a MOS transistor, p + polysilicon is generally used for a gate electrode of a p-channel type MOS transistor, and an n-channel type MOS transistor is generally used.
It is known that n + polysilicon is preferably used for the gate electrode of the S transistor. This effect is, for example,
I E E E, I E D M,
Technical, Digest, IEEE, IEDM, Te
chemical Digest p418-422 (1
984).

Further, p + polysilicon is used to make contact between the polysilicon film and the p + region formed in the semiconductor substrate, and n + polysilicon is used to make contact between the n + region and the polysilicon film. Have been.
Therefore, a CMOS in which p-channel and n-channel MOS transistors are formed on the same semiconductor substrate
In the type semiconductor device, if the p + region and the n + region can be mixed in the same polysilicon film, it is convenient to reduce the area of the integrated circuit element.

Since a polysilicon film in which P-type and N-type are mixed has a higher resistivity than a general metal film, a refractory metal silicide film or a refractory metal nitride film is formed on the polysilicon film. Generally, a polycide film is formed by forming a film or the like. By using a polycide film, the p + polysilicon film and the n + polysilicon film are electrically connected by the refractory metal silicide film or the refractory metal nitride film, and a special connection region is not required. After the polycide film is formed, a heat treatment at 900 ° C. is performed, so that the BPSG (silicate glass containing boron and phosphorus) film can be planarized. Such a semiconductor device is reported, for example, in JP-A-57-192079.

However, in the case of a polycide film in which polysilicon and silicide are simply laminated, boron which is a p-type impurity in p + polysilicon and boron in n + polysilicon are subjected to a heat treatment such as planarization using a BPSG film in a later step. Phosphorus or arsenic, which is an n-type impurity, mutually diffuses in the silicide film, and when the polycide film is used for the gate electrode of the MOSFET, the threshold voltage (Vt) varies. This variation in Vt is caused by the P-channel type M
N-channel type MOSFET which occurs only in OSFET
Does not occur. This phenomenon is described in, for example, IEE Electron Device Letter, Volume 12, IEEE, EDL, vol. 12p696-69
8, 1991. Similarly, when used as a wiring connecting the n + diffusion layer and the p + diffusion layer, the contact resistance increases. Further, a method of forming a diffusion preventing film between polysilicon and silicide in order to prevent the diffusion via the silicide has been reported. Such a semiconductor device or a method of manufacturing a semiconductor device is disclosed in, for example,
-265542 or JP-A-2-192161
No. is reported in the official gazette.

[0006]

However, in the above-mentioned method for forming a polycide film, the diffusion preventing effect of the titanium nitride film (TiN) used for the diffusion preventing film is included as an N / Ti composition ratio and impurities. The process is highly dependent on the amount of oxygen, the crystal grain size, the crystal orientation, and the like, and the process is unstable. In particular, when the polycide film is used as the wiring, the thickness of the TiN film in the contact portion is reduced, and the diffusion preventing effect is lost, and the p-type impurity or the n-type impurity in the polysilicon diffuses into the silicide film,
Furthermore, the diffusion in the silicide causes the p-type impurity to reach the n + polysilicon film and the n-type impurity to reach the p + polysilicon film, resulting in a reduction in carrier concentration due to the compensation effect, resulting in an increase in contact resistance. I was

The present invention has been made in view of the above problems, and in a semiconductor device in which an n + region and a p + region are mixed in the same polysilicon film in a polycide film, the polycide film is formed in a MOSFET even if heat treatment is performed in a later step. When used for a gate electrode, a threshold voltage (V) is applied to a P-channel MOSFET as well as an N-channel MOSFET.
An object of the present invention is to provide a semiconductor device in which the variation of t) does not occur and which can stabilize the p + contact resistance as well as the n + contact when used for a wiring connecting the n + diffusion layer and the p + diffusion layer, and a method of manufacturing the same. .

[0008]

A semiconductor device and a method of manufacturing the same according to the present invention for solving the above-mentioned problems include a p-channel MOS transistor and an n-channel MOS transistor.
A multi-layer film of a polysilicon film and a silicide film as a gate electrode or a wiring, wherein the polysilicon film in the multi-layer film has both a p + region and an n + region, and a silicide film in the multi-layer film Boron over the entire area , and 1 × 10 ¹⁷ cm ^-3 or more so that there is no gradient in concentration
It is included .

[0009]

According to the present invention, since there is no concentration gradient in boron in the silicide film due to the above structure, boron which is a p-type impurity in the p + polysilicon film diffuses in the silicide film even when the heat treatment is performed at 900.degree. Nothing. Therefore, p
+ The concentration of boron as a p-type impurity in the polysilicon film does not decrease. Also, boron in the silicide film hardly diffuses into the n + polysilicon film, and the n-type conductivity of the n + polysilicon can be maintained. Further, since the p + polysilicon film and the n + polysilicon film are electrically conducted mainly through the silicide film due to the polycide structure, it becomes possible without using a special connection region.
Further, even if a heat treatment of about 900 ° C. such as planarization using a BPSG film is performed, the present effect can be maintained.

[0010]

(Embodiment 1) Hereinafter, as a first embodiment of the present invention, a semiconductor device using a multilayer film of polysilicon and silicide (polycide film) for a gate electrode will be described.
This will be described with reference to the drawings.

FIG. 1 is a sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is p
Type silicon substrate 2 and n formed in silicon substrate 1
-Well, 3 is an element isolation region, 4 is a p-channel type MO
S transistor region, 5 is an n-channel MOS transistor region, 6 is a p + diffusion layer region serving as a source / drain region of a p-channel MOS transistor, 7 is an n + diffusion layer region serving as a source / drain region of an n-channel MOS transistor , 8 are gate oxide films, 9a is p +
Polysilicon film, 9b is n + polysilicon film, 12 is 1
It is a tungsten silicide film containing boron of 10 ¹⁷ cm ^-3 or more and having no gradient in boron concentration. A polycide film is formed by a two-layer film of the polysilicon film 9 and the tungsten silicide film 12. Note that p shown in FIG.
+ Diffusion layer region 6 and n + diffusion layer region 7 are not formed immediately below the gate electrode.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to the cross-sectional view of FIG.

In FIG. 2A, an n-well 2 is formed in a P-type silicon substrate 1 having a plane orientation (100) by ion implantation and thermal diffusion, and a typical selection is formed on the substrate 1. The element isolation region 3 is formed by an oxidation method. A p-channel MOS transistor region 4 is formed in the n-well 2 region, and an n-channel MOS transistor region 5 is formed in regions other than the n-well 2 region. Thereafter, a gate oxide film 8 is formed to a thickness of 10 nm on the substrate 1, a polysilicon film 9 is deposited on the gate oxide film 8, and the n-channel MOS transistor region 5 is covered with a photoresist 10. B + ions are implanted into the polysilicon film 9 at an acceleration energy of 10 KeV and a dose of 6 × 10 15.
Ion implantation is performed under the condition of cm @ -2 to make the polysilicon film 9 a p + polysilicon film 9a.

In FIG. 2B, the photoresist 10 is then removed, the p-channel MOS transistor region 5 is covered with a photoresist 11, and the polysilicon film 9
S + ions are accelerated at an energy of 20 KeV and a dose of 1
Ion implantation is performed under the condition of x1015 cm-2, and the polysilicon film 9 is changed to an n + polysilicon film 9b.

In FIG. 2C, the photoresist 11 is thereafter removed, and the tungsten silicide film 12 is
nm. Then, the entire surface B + ions, the acceleration energy 10 KeV, by ion implantation at a dose of 6x1015cm-2, the contained tungsten silicide film 12 boron 1x10 ¹⁷ cm ^-3 or more in, the boron concentration Eliminate the gradient.

Next, a silicon oxide film is formed on the entire surface to a thickness of 200 nm.
accumulate. Thereafter, the p + polysilicon film 9a, n +
By etching the polysilicon film 9b, the tungsten silicide film 12, and the silicon oxide film so as to have a desired wiring shape, for example, the gate electrode of the p-channel MOS transistor and n
A wiring pattern for connecting the gate electrodes of the channel type MOS transistors is formed. Then, p channel MO
In the surface region of the S transistor region 4, BF2 + is ion-implanted under the conditions of an acceleration energy of 30 keV and a dose of 6.times.10@15 cm @ -2 to form a p + diffusion layer region 6 as a source or drain region. In the surface region of the region 5, As + is ion-implanted under the conditions of an acceleration energy of 40 keV and a dose of 6.times.10@15 cm @ -2, thereby forming an n + diffusion layer region 7 as a source or drain region. Thereafter, using a known insulating film forming method and a known wiring forming method, a wiring made of, for example, an aluminum alloy is formed on the source, drain, and gate electrodes to complete the semiconductor device.

Next, the results of analyzing the distribution of impurities in the polycide film after the heat treatment will be described. FIG. 3 shows a tungsten silicide film and a polysilicon film.
The thickness distribution of boron concentration before and after heat treatment in a polycide film having a layer structure is shown. The heat treatment was performed at a temperature of 900 ° C. for 30 minutes. As shown in FIG. 3A, when boron is implanted only in polysilicon before heat treatment and does not exist in silicide, 60 to 90% of boron in the polysilicon film is tungsten silicide by heat treatment. The boron is diffused in the film and to the surface of the tungsten silicide film, and as a result, the boron concentration in the polysilicon film is reduced. FIG. 5A schematically shows a diffusion path of an impurity in a conventional semiconductor device. It can be seen that the diffusion of boron from the polysilicon film into the tungsten silicide film corresponds to boron diffusion 1 in FIG. 5A, and the diffusion amount is much larger than the result in FIG. Therefore, the p-channel type MO
In a semiconductor device having an S transistor and an n-channel MOS transistor, if boron is not present in the tungsten silicide film of the n-type polycide, boron present in the polysilicon film of the p-type polycide region is replaced by tungsten silicide of the n-polycide region. It also diffuses into the film, and further reduces the boron concentration. This boron diffusion corresponds to boron diffusion 2 in FIG. 5A, and the diffusion amount is very large.

On the other hand, as shown in FIG. 3B, when boron is implanted only in the tungsten silicide film, the amount of boron diffusion from the tungsten silicide film to the polysilicon film is 10 even if heat treatment is performed. % Or less. When arsenic is contained in the polysilicon film, the amount of diffusion of boron is further reduced. This boron diffusion corresponds to boron diffusion 3 in FIG. 5A, and the diffusion amount is small. That is, it was found that boron became higher in the silicide film than in the polysilicon film and reached equilibrium. The diffusion 4 of boron that diffuses in the polysilicon film in FIG. 5A is much smaller than the diffusion 2 of boron that diffuses in the silicide film.

FIG. 4 shows the results of analyzing the distribution of the concentration of arsenic in the thickness direction before and after the heat treatment in a polycide film having a two-layer structure of a tungsten silicide film and a polysilicon film. The heat treatment after arsenic implantation is performed at 900 ° C. for 3 hours.
Performed for 0 minutes. As shown in FIG. 4A, when arsenic is implanted in the polysilicon film of the polycide film, the diffusion amount of arsenic from the polysilicon film to the tungsten silicide film by the heat treatment is 30% or less. This arsenic diffusion corresponds to arsenic diffusion 1 in FIG. 5A, and the diffusion amount is small. On the other hand, when arsenic is distributed in the tungsten silicide film, the diffusion amount of arsenic from the tungsten silicide film to the polysilicon film due to the heat treatment is 60% or more, and arsenic is more poly than the silicide film. The concentration becomes high in the silicon film and reaches equilibrium. This arsenic diffusion corresponds to arsenic diffusion 3 in FIG.

As described above, by heat-treating the polycide film, boron, which is a p-type impurity, has a high concentration in the silicide film, and arsenic, which is an n-type impurity, has a high concentration in the polysilicon film. I understand. The present invention utilizes the distribution characteristics of the impurities, and it is possible to form a gate electrode of a p-channel MOS transistor, a gate electrode of an n-channel MOS transistor, and a wiring connecting them with continuous polycide. It is to be. FIG. 5B schematically shows a diffusion path of the impurity in the semiconductor device according to the present invention. The arrow indicated by the dotted line in FIG. 5B is a diffusion path eliminated by the present invention. First, boron is contained in the tungsten silicide 12 in the p-channel MOS transistor region and is made to have a concentration substantially equal to the boron concentration in the p + polysilicon 9a. Does not spread inside. This boron diffusion corresponds to boron diffusion 1 in FIG. 5B and is eliminated by the present invention. Further, by including the same amount of boron in the tungsten silicide 12 in the n-channel MOS transistor region as in the tungsten silicide 12 in the p-channel MOS transistor region and eliminating the gradient of the boron concentration, the p-type in the tungsten silicide 12 is reduced. Diffusion of boron from the channel region to the n-channel region does not occur. This boron diffusion corresponds to boron diffusion 2 in FIG. 5B and is eliminated by the present invention. Therefore, the boron concentration in p + polysilicon 9a does not decrease.

The purpose of eliminating the gradient of the boron concentration in the tungsten silicide film in the present invention is to prevent the occurrence of boron diffusion 2 due to the subsequent heat treatment. Therefore, even if there is some variation in the boron concentration in the tungsten silicide film, there is no problem as long as the change in the boron concentration after the heat treatment does not affect the characteristics.

As shown in FIG. 3B, even if the tungsten silicide film 12 contains boron, the boron does not diffuse from the tungsten silicide film 12 to the n + polysilicon 9a. This boron diffusion is shown in FIG.
This corresponds to boron diffusion 3 in (B), but does not increase to an amount that causes a problem in characteristics even with the configuration of the present invention. 4A, the arsenic in the n + polysilicon film 9b does not diffuse from the n + polysilicon 9b to the tungsten silicide 12, and therefore diffuses in the tungsten silicide 12 to the p + polysilicon 9a. There is nothing to reach. That is, the arsenic diffusion 2 in FIG. 5A is not a problem because the arsenic diffusion 1 is small, and the arsenic diffusion 3 is not a problem because the arsenic diffusion 2 is small. In addition, arsenic diffusion 4 in the polysilicon film is small and causes no problem.

As described above, the gate electrode of the p-channel MOS transistor is p + polysilicon, and the gate electrode of the n-channel MOS transistor is n + polysilicon. By including boron, even if heat treatment is performed, the boron in p + polysilicon 9a does not decrease, and the arsenic in n + polysilicon 9b does not diffuse into p + polysilicon 9a. Therefore, the threshold voltage (Vt) of the p-channel MOS transistor is the same as the threshold voltage (Vt) of the n-channel MOS transistor.
Does not fluctuate.

(Embodiment 2) As a second embodiment of the present invention, a semiconductor device in which polycide is used for wiring will be described. FIG. 6 is a sectional configuration view of a main part of the semiconductor device. 6, 1 is a p-type silicon substrate, 2 is an n-well formed in the silicon substrate 1, 3 is an element isolation region, 4 is a p-channel MOS transistor region, 5 is an n-channel MOS transistor region, 6 Is a p + diffusion layer region, 7 is an n + diffusion layer region, 8 is a gate oxide film, 13
Is an interlayer insulating film, 14 is a contact hole opened in the interlayer insulating film 13, 15a is a p + polysilicon film, and 15b is n.
+ Polysilicon film, 16 is a tungsten silicide film. Note that the p + polysilicon film 9a, n +
Polysilicon film 9b, tungsten silicide film 12
Is a cross-sectional configuration view of a portion that is not displayed.

Next, a method of manufacturing the semiconductor device of FIG. 6 will be described. p + diffusion layer region 6 and n + diffusion layer region 7
The steps up to this are the same as those in the first embodiment. Then, after forming an interlayer insulating film 13 on the entire surface, a contact hole 14 is opened in the interlayer film 13. After that, a natural oxide film at the interface is removed by performing dip etching using an aqueous solution containing hydrofluoric acid, and then a method similar to that for forming the p + polysilicon film 9a and the n + polysilicon film 9b in FIG. 1 is used. Then, a p + polysilicon film 15a and an n + polysilicon film 15b are formed. Thereafter, a tungsten silicide film 16 is formed by using the same method as that of the tungsten silicide film 12, and boron is contained in the tungsten silicide film 16 by using the same method as in the first embodiment.

As described above, in the present embodiment, even when the polycide formed according to the present invention is used as a wiring, as in the first embodiment, the tungsten silicide film 16 contains boron so that the heat treatment can be performed. Does not reduce the boron in the p + polysilicon film 15a, and the arsenic in the n + polysilicon film 15b
+ Does not diffuse into polysilicon film 15a. Thus, even when the p + diffusion layer region 6 and the n + diffusion layer region 7 are connected by the polycide of the present invention, the p + polysilicon film 15a is formed in the same manner as the contact resistance of the n + polysilicon film 15b and the n + diffusion layer region 7. And the contact resistance of p + diffusion layer region 6 does not increase.

In the above embodiment, after the tungsten silicide film is formed, boron is contained in the entire surface. However, the present invention can be applied to any structure in which boron diffusion 2 shown in FIG. 5 does not occur. good. For example, even if boron is contained in the tungsten silicide film at least in a portion other than the p + polysilicon region, the boron diffusion 2 in FIG.
Does not occur and the same effect can be obtained. That is, how much p +
Even if the boron concentration in the region is increased, if boron is not present in tungsten silicide other than the p + region, boron diffusion 2 in FIG.
The boron concentration in the region decreases. According to the present invention, a portion where boron is likely to diffuse is made to contain boron in advance to prevent a decrease in boron concentration due to a subsequent heat treatment.

The gate oxide film 8 may be made of a material other than the oxide film, for example, a nitrided oxide film. Although the n + polysilicon and the p + polysilicon are formed by using the ion implantation method, a thermal diffusion method may be used. Although tungsten silicide is used as the silicide, the same effect can be obtained by using another silicide such as a titanium silicide film or a molybdenum silicide film. Although arsenic is used as the n-type impurity, the same effect can be obtained by using phosphorus. Although B + ion implantation is used as a method for incorporating boron, the same effect can be obtained by performing BF2 + ion implantation. Further, in the embodiment, the gate electrode of the p-channel type MOS transistor, the gate electrode of the n-channel type MOS transistor and the wiring connecting them are integrated by continuous polycide,
Although the example in which the + diffusion layer region 6 and the n + diffusion layer region 7 are connected by a continuous polycide has been described, it is of course possible to connect the diffusion layer and another part such as a gate electrode.

[0029]

According to the method of manufacturing a semiconductor device of the present invention, p +
In a polycide film containing polysilicon and n + polysilicon, boron is contained in the entire surface of the tungsten silicide film, so that even if heat treatment is performed, the boron in the p + polysilicon film does not decrease and the n + polysilicon film Does not diffuse into the p + polysilicon film. Therefore, even if the heat treatment is performed using the polycide film as the gate electrode of the MOSFET, the threshold voltage (Vt) does not fluctuate, and the contact resistance is reduced when the polycide film is used for the wiring connecting the n + diffusion layer and the p + diffusion layer. It does not increase. Furthermore, since the polycide structure is used, electrical conduction between p + polysilicon and n + polysilicon can be achieved without using a contact, and the effect can be maintained even if heat treatment is performed at 900 ° C.
Flattening using a BPSG film becomes possible. Further, conventionally, it was necessary to increase the distance between the p + region and the n + region in order to prevent the influence of lateral diffusion. However, the structure of the present invention makes it possible to shorten this distance. This can also greatly contribute to reducing the area of the integrated circuit element.

[Brief description of the drawings]

FIG. 1 is a cross-sectional configuration diagram of a main part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a main step in the embodiment.

FIG. 3 is a distribution diagram of boron in a polycide film after heat treatment.

FIG. 4 is a distribution diagram of arsenic in a polycide film after heat treatment.

FIG. 5 is a diagram schematically showing a diffusion path of an impurity.

FIG. 6 is a cross-sectional configuration diagram of a main part of a semiconductor device according to a second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 n-well 3 element isolation region 4 p-channel MOS transistor region 5 n-channel MOS transistor region 6 p + diffusion layer region 7 n + diffusion layer region 8 gate oxide films 9a, 15a p + polysilicon films 9b, 15b n + Polysilicon film 10, 12 Resist 13, 16 Tungsten silicide film 13 Interlayer insulating film 14 Contact hole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/092

Claims (5)

(57) [Claims] A p-channel MOS transistor and an n-channel MOS transistor;
A multi-layered film of a polysilicon film and a silicide film is used as a gate electrode of the channel type MOS transistor and the n-channel type MOS transistor, and the polysilicon film in the multi-layered film covers both the p + region and the n + region.
In other words, the entire area of the silicide film that is in contact with the two areas is sized.
Ron, as no gradient in concentration, 1 × 10 ¹⁷ cm ^-3 or more
A semiconductor device characterized by being included . 2. A semiconductor device comprising a p-channel MOS transistor and an n-channel MOS transistor,
A multi-layer film of a polysilicon film and a silicide film is used as a wiring for electrically connecting the p + diffusion layer region and the n + diffusion layer region of the channel type MOS transistor and the n-channel type MOS transistor. The film has both p + and n + regions ,
Boron is formed over the entire area of the silicide film in contact with the two areas.
Is contained at least 1 × 10 ¹⁷ cm ^-3 so that there is no gradient in concentration.
Wherein a that it has. 3. A semiconductor device having both a p-channel type MOS transistor and an n-channel type MOS transistor,
A method of manufacturing a semiconductor device using a multilayer film of a polysilicon film and a silicide film as a gate electrode of a channel type MOS transistor and an n-channel type MOS transistor, wherein the polysilicon film in the multilayer film has both a p + region and an n + region In, after forming the multilayer film,
A method for manufacturing a semiconductor device, comprising a step of including boron in a concentration of 1 × 10 ¹⁷ cm ⁻³ or more in the entire region of the silicide film in the multilayer film so that there is no concentration gradient. 4. A semiconductor device having both a p-channel MOS transistor and an n-channel MOS transistor,
A multi-layer film of a polysilicon film and a silicide film is used as a wiring for electrically connecting the p + diffusion layer region and the n + diffusion layer region of the channel type MOS transistor and the n channel type MOS transistor, and the polysilicon film in the multilayer film is used. In the method for manufacturing a semiconductor device having both the p + region and the n + region, after forming the multilayer film, boron is applied to the entire region of the silicide film in the multilayer film so that the concentration is 1 × 10 ¹⁷ cm ⁻ the method of manufacturing a semiconductor device characterized by having a ^third step to include more. 5. A method for manufacturing a semiconductor device using a multilayer film of a polysilicon film and a silicide film, wherein the polysilicon film in the multilayer film has both a p + region and an n + region. Silicide film in multilayer film
At least a portion in contact with a region other than the n + region
In addition, boron was added to 1 × 10 ¹⁷ cm so that there was no gradient in concentration.
The method of manufacturing a semiconductor device characterized by comprising the step of including ^-3.