JPS61258452A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61258452A JPS61258452A JP60100915A JP10091585A JPS61258452A JP S61258452 A JPS61258452 A JP S61258452A JP 60100915 A JP60100915 A JP 60100915A JP 10091585 A JP10091585 A JP 10091585A JP S61258452 A JPS61258452 A JP S61258452A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alloy
- semiconductor device
- layers
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 19
- 239000000956 alloy Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 13
- 229910008484 TiSi Inorganic materials 0.000 claims description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 229910018580 Al—Zr Inorganic materials 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims 3
- 229910021364 Al-Si alloy Inorganic materials 0.000 claims 1
- 229910004339 Ti-Si Inorganic materials 0.000 claims 1
- 229910010978 Ti—Si Inorganic materials 0.000 claims 1
- 229910007735 Zr—Si Inorganic materials 0.000 claims 1
- 238000005546 reactive sputtering Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 77
- 239000011229 interlayer Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910001093 Zr alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野）
本発明は半導体装置に関し、特に配線材料に改良を加え
たものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to one in which improvements are made to wiring materials.
従来、ＭＯ８型トランジスタなどの半導体装置においで
、例えばシリコン基板表面の拡散層とコンタクトホール
を介して接続する配線材料として八λが用いられている
。しかしながら、この場合、Ａｌ、のＳｉとの合金化に
よりアロイスパイクが発生し、ＰＮ接合の破壊が生じる
。また、ＡＩ、のエレクトロマイグレーションが生じる
。BACKGROUND ART Conventionally, in semiconductor devices such as MO8 type transistors, 8λ has been used as a wiring material for connecting, for example, to a diffusion layer on the surface of a silicon substrate via a contact hole. However, in this case, alloy spikes occur due to alloying of Al with Si, resulting in destruction of the PN junction. Furthermore, electromigration of AI occurs.
そのため、ＡＩ中に予めＳｉを１〜５％程度含有させて
Ａｌ１中のＳｉの固溶度を十分に満足させる方法が取ら
れている。しかしながら、この方法によれば、Ａｌ１の
Ｓｉ含有量をアロイスパイクが発生しない程度にすると
、Ａｌ配線中に固溶度を越えたＳｉが析出し、これが抵
抗として働きへβ配線の見掛は上の切れにつながる（配
線のオー７ン）。また、前述したＡｌのエレクトロマイ
グレーションも十分に解消するには至らない。Therefore, a method has been adopted in which approximately 1 to 5% of Si is previously included in AI to fully satisfy the solid solubility of Si in Al1. However, according to this method, if the Si content of Al1 is set to a level that does not cause alloy spikes, Si exceeding the solid solubility will precipitate in the Al wiring, and this will act as a resistance, resulting in an increase in the appearance of the β wiring. This will lead to a break in the wiring (opening of the wiring). Further, the electromigration of Al mentioned above cannot be sufficiently eliminated.
更に、他の方法として、なんらかのバリアメタルを使用
し、Ａｌ中のＳｉの含有器を減らす方法が取られている
。この場合、バリアメタルとしては、ＴｉＮが良く用い
られている。しかしながら、ＴｉＮを用いない方法によ
れば、コンタクトをＢＦ２又はＢ、ＢＣｎ２が注入され
たＰ＋拡散層上に形成した場合、前述したＳｌのコンタ
クトホー −ル中への析出が顕著に起り、コンタクトサ
イズの減少に伴うコンタクト抵抗の増大が激しく起こる
（コンタクト抵抗の増大）。また、ＴｉＮを用いた場合
、やはりＴｉＮとＰ＋型のＳ；の間でＢのＴｉＮ中への
拡散が起り、良好なオーミックコンタクトが形成できな
い。Furthermore, another method is to use some kind of barrier metal to reduce the amount of Si contained in Al. In this case, TiN is often used as the barrier metal. However, according to the method that does not use TiN, when a contact is formed on a P+ diffusion layer into which BF2, B, or BCn2 is implanted, the aforementioned precipitation of Sl into the contact hole occurs significantly, and the contact size increases. As contact resistance decreases, contact resistance increases sharply (increase in contact resistance). Furthermore, when TiN is used, diffusion of B into TiN occurs between TiN and P+ type S, making it impossible to form a good ohmic contact.
本発明は上記事情に鑑みてなされたもので、コンタクト
抵抗の増大、アロイスパイクを抑制するとともに、耐エ
レクトロマイグレーション強度を向上できる半導体装置
を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can suppress an increase in contact resistance and alloy spikes, and can improve electromigration resistance.
本発明は、半導体基板と、この基板表面に設けられた拡
散層と、同基板上に設けられ前記拡散層に対応する部分
にコンタクトホールを有した絶縁膜と、この絶縁膜のコ
ンタクトホールに設けられ八β又はへ２合金層／Ｔ ｉ
Ｎ層／ Ｔ ｉ層の少なくとも３層構造の配線を具備
することを特徴とし、コンタクト抵抗の増大、アロイス
パイクを抑制するとともに、耐エレクトロマイグレーシ
ョン強度の向上を図ったものである。The present invention provides a semiconductor substrate, a diffusion layer provided on the surface of this substrate, an insulating film provided on the substrate and having a contact hole in a portion corresponding to the diffusion layer, and a contact hole provided in the insulating film. 8 β or 2 alloy layer/T i
It is characterized by having wiring with at least a three-layer structure of N layer/Ti layer, and is intended to suppress an increase in contact resistance and alloy spikes, and to improve electromigration resistance.
本発明に係る配線としては、ＡＭ層／Ｔ ｉ Ｎ層／Ｔ
ｉｌ又はＡｌ合金層／ＴｉＮ層／Ｔｉ層の３層構造のも
の、若しくはＡｌ又はＡｌ合金層ＺＴｉ層／ＴｉＮ１ｉ
／ＴｉＮｌ１．ＴｉＳｉ層／Ａ℃！／Ｔ ｉ Ｎ層／Ｔ
ｉ層、ＴｌＳｉ層／Ａｆｉ合金層／Ｔ ｉ Ｎｉ！／Ｔ
ｉ層の４層構造のものが挙げられる。The wiring according to the present invention includes AM layer/T i N layer/T
il or Al alloy layer/TiN layer/Ti layer three-layer structure, or Al or Al alloy layer ZTi layer/TiN1i
/TiNl1. TiSi layer/A℃! /T i N layer/T
i layer, TlSi layer/Afi alloy layer/T i Ni! /T
Examples include those having a four-layer structure with an i-layer.
本発明に係るＡｌの材料としては、Ａｌ−ｓ ＋合金、
ＡＩ−Ｔｉ−３ｌ合金、ＡＵ−Ｚｒ−８ｌ合金、ＡＩ−
Ｔｉ合金、ＡＩ−Ｚｒ合金等が挙げられる。The Al material according to the present invention includes Al-s + alloy,
AI-Ti-3l alloy, AU-Zr-8l alloy, AI-
Examples include Ti alloy and AI-Zr alloy.
以下、本発明の一実施例に係る相補型（Ｃ）ＭＯＳトラ
ンジスタを製造工程順に第１図（ａ）〜（ｆ）を参照し
て説明する。Hereinafter, a complementary (C) MOS transistor according to an embodiment of the present invention will be described in the order of manufacturing steps with reference to FIGS. 1(a) to 1(f).
（１）、まず、通常の工程により、Ｐ型のシリコン基板
１の表面にＰウェル２、Ｎウェル３及びフィールド酸化
膜４を形成したく第１図（ａ＞図示）。なお同図（ａ＞
において、５はフィールド酸化ＦＩ４で囲まれた素子領
域を示す。つづいて、前記素子領域５の表面にゲート酸
化１１６を形成し、トランジスタのしきい値電圧用のチ
ャネルインプラを行いイオン注入Ｍ７ａ、７ｂを夫々形
成した後、多結晶シリコン層を堆積した。次いで、この
多結晶シリコン層に所定の不純物をドープした債、これ
をパターニングしてゲート電極８ａ、８ｂを夫々形成し
た（第１図（ｂ）図示）、、次いで、前記ゲート電極８
ａ、８ｂを夫々マスクとしてＰウェル２、Ｎウェル３に
ｎ型不純物、ｎ型不純物（ボロン）を導入し、Ｐウェル
の表面にはＮ＋型のソース、ドレイン領域９ ａ、１０
ａを形成し、Ｎウェル３にはＰ＋型のソース、ドレイン
領域９ｂ、１０ｂを形成した。更に、全面に層間絶縁膜
１層を形成した後、前記ソース領域９ａ、９ｂに対応す
るゲート酸化膜６、層間絶縁１１１１にコンタクトホー
ル１２ａ、１２ｂを形成した（第１図（Ｃ）図示）。(1) First, a P well 2, an N well 3, and a field oxide film 4 are formed on the surface of a P type silicon substrate 1 by a normal process in FIG. 1 (a>shown). The same figure (a>
In the figure, 5 indicates an element region surrounded by field oxidation FI4. Subsequently, gate oxide 116 was formed on the surface of the element region 5, channel implantation for the threshold voltage of the transistor was performed, ion implantations M7a and 7b were formed, and then a polycrystalline silicon layer was deposited. Next, this polycrystalline silicon layer was doped with a predetermined impurity and patterned to form gate electrodes 8a and 8b, respectively (as shown in FIG. 1(b)).
Using a and 8b as masks, n-type impurities and n-type impurities (boron) are introduced into the P-well 2 and N-well 3, respectively, and N+ type source and drain regions 9a and 10 are formed on the surface of the P-well.
In the N well 3, P+ type source and drain regions 9b and 10b were formed. Furthermore, after forming one layer of interlayer insulating film over the entire surface, contact holes 12a and 12b were formed in the gate oxide film 6 and interlayer insulating film 1111 corresponding to the source regions 9a and 9b (as shown in FIG. 1C).
（２）６次に、厚さ５００人ｃ７）Ｔ ｉｌｌ ３、厚
さ５００人のＴｉＮ層１４を同一真空槽中で化成 。(2) 6 Next, a TiN layer 14 with a thickness of 500 layers is formed in the same vacuum chamber.
ＴｉＮ層１４の堆積の際、基板１にＲＦバイアスを加え
てコンタクトエツジ部でのＴｉＮ層１４のステップカバ
レージ及びその部分の結晶性を改善してもよい。つづい
て、これら１Ａｌ層１５、Ｔ ｉ Ｎ１１ｌ ４及び７
１層１３からなる３層を写真蝕剣法、反応性イオンエツ
チングを用いてバターニングを行った。ここで、エツチ
ングガスと、しては、ＢＣｊ２ｉ 、 Ｃｆｆ１２、Ｈ
ｅを混合ガスを用イル。During the deposition of the TiN layer 14, an RF bias may be applied to the substrate 1 to improve the step coverage of the TiN layer 14 at the contact edge and the crystallinity of that portion. Subsequently, these 1Al layer 15, T i N11l 4 and 7
The three layers consisting of layer 1 and layer 13 were buttered using photoetching and reactive ion etching. Here, the etching gas is BCj2i, Cff12, H
Use a mixed gas.
その結果、純へり層１５、ＴｉＮ層１４．７１層１３の
３層構造の第１１目の配置１１６ｔ、１６２が形成され
た（第１図（ｅ）図示）。次いで、全面に低温プラズマ
ＣＶＤ法により、
ＣＶＤ−Ｓｉ ０２１７を形成した後、前記配線１６１
に対応する前記５１０２１ｍ７を選択的に除去し、コン
タクトホール１８を形成した。更に、このコンタクトホ
ール１８に前記と同様な方法により、第２１１Ｉ目のＡ
ｌ配線を形成し、ＣＭＯＳトランジスタを製造したく第
１図（ｆ）図示）。As a result, an eleventh arrangement 116t, 162 having a three-layer structure of a pure edge layer 15, a TiN layer 14, and a TiN layer 13 was formed (as shown in FIG. 1(e)). Next, after forming CVD-Si 0217 on the entire surface by low temperature plasma CVD method, the wiring 161
The contact hole 18 was formed by selectively removing the 51021 m7 corresponding to the contact hole 18. Furthermore, a 211Ith A is formed in this contact hole 18 by the same method as described above.
1(f) to form a CMOS transistor.
本発明に係るＣＭＯＳトランジスタは、第１図（ｆ）に
示す如く、第１！１目の配線１６１．１６２を夫々Ａｌ
層１５．．’Ｔ ｉ Ｎ層１４／Ｔｉ１１３の３Ｍ構造
とし、この配線１６１．１６２を層間絶縁膜１１に設け
られたコンタクトホール１２ａ１１２ｂを夫々介してソ
ース領域９ａ、９ｂ１．：ｌ気的に接続した構成となっ
ている。従って、本発明によれば、以下に示す効果を有
する。In the CMOS transistor according to the present invention, as shown in FIG.
Layer 15. ．． 'A 3M structure of TiN layer 14/Ti 113 is used, and these wirings 161 and 162 are connected to source regions 9a, 9b1 . :It has a configuration in which it is electrically connected. Therefore, according to the present invention, the following effects are achieved.
■、配置！１６ｓ（又は１６２）を構成する純Ａｌ層１
５と７１層１３との間にＴｉＮ層１４を介在させること
により、層間絶縁ｆｉ１１１のコンタクトホール１２ａ
、１２ｂ１あるいは配線１６１．１６２のＳｉの析出を
なくし、コンタクト抵抗の増大を抑制でき、またＰＮ接
合の破壊を抑止できる。また、ＴｉＮ層１４の下層に７
１層１３を設けることにより、Ｒ２型のソース類［９ｂ
中のボロンがＴｉＮ層１４に拡散するのを防止し、良好
なコンタクト特性が得られる。事実、Ｔ ｉｌｌ ３を
４５０℃、１５分の条件でシンターを行ったところ、Ｔ
ｉが７ｉＳｉ２に変化し良好なコンタクトが形成できた
。なお、従来及び本発明のトランジスタによりコンタク
トホールの大きさとコンタクト抵抗との関係は第２図に
示す通りである。同図において、（イ）は本発明による
Ｐ＋拡散層とのコンタクト抵抗を、（ロ）は同発明によ
るＮ１拡散層とのコンタクト抵抗を、また（ハ）、（ニ
）は夫々従来によるＰ”、Ｎ＋拡散層とのコンタクト抵
抗を示す。同図により、本発明によれば、Ｐ１拡散層と
のコンタクト抵抗がコンタクトホールの大きさに比例し
て著しく減少することが確認できる。■, Placement! Pure Al layer 1 constituting 16s (or 162)
By interposing the TiN layer 14 between the 5 and 71 layers 13, the contact hole 12a of the interlayer insulation fi111 is
, 12b1 or the wirings 161, 162, it is possible to suppress an increase in contact resistance, and it is also possible to suppress breakdown of the PN junction. In addition, 7
By providing one layer 13, R2 type sources [9b
This prevents the boron therein from diffusing into the TiN layer 14, resulting in good contact characteristics. In fact, when T ill 3 was sintered at 450°C for 15 minutes, T
i was changed to 7iSi2 and a good contact could be formed. Incidentally, the relationship between the size of the contact hole and the contact resistance of the conventional transistor and the transistor of the present invention is as shown in FIG. In the figure, (a) shows the contact resistance with the P+ diffusion layer according to the present invention, (b) shows the contact resistance with the N1 diffusion layer according to the same invention, and (c) and (d) respectively show the contact resistance with the conventional P" , which shows the contact resistance with the N+ diffusion layer. From this figure, it can be confirmed that according to the present invention, the contact resistance with the P1 diffusion layer is significantly reduced in proportion to the size of the contact hole.
■、前述した如＜ＴｉＮＲ１４の下層に１１層１３を設
けることにより、エレクトロマイグレーションを抑制で
きる。(2) Electromigration can be suppressed by providing the 11 layer 13 below the TiNR layer 14 as described above.
■、前記■と同様な理由により、配線のオーブンを防止
できる。(2) For the same reason as (2) above, wiring ovens can be prevented.
なお、上記実施例では、配線を純ＡＪ２／ＴｉＮ層／Ｔ
ｉ層の３層構造としてが、例えばＡｌ又はＡり合金１１
／Ｔ ｉ ｉ！／Ｔ １Ｎｌｆ／Ｔ ｉ ！！、あるい
はＴｉ３ｌ層／Ａｌ又はＡｌ合金１／Ｔ ｉ Ｎｌｌ／
Ｔｉｌの４１構造としてもよい。こうした構造にすれば
、八２にロックを防止できる。即ち、館者の場合は、Ｔ
ｉｌによりＴｉＮ層中のＮがＡｌｌ！！ｉ中に拡散する
のを押えるとともに、Ｔｉ層中のＴｉがＡｌｌ中に拡散
することにより、Ａｌヒロックを防止するものである。In the above embodiment, the wiring is pure AJ2/TiN layer/T
The three-layer structure of the i-layer is, for example, Al or Al alloy 11
/ T i i! /T 1Nlf/T i! ! , or Ti3l layer/Al or Al alloy 1/T i Nll/
It may also be a Til 41 structure. With this structure, locking can be prevented to a large extent. In other words, in the case of the curator, T
Due to il, all N in the TiN layer! ! In addition to suppressing diffusion into the Ti layer, Ti in the Ti layer diffuses into the Al layer, thereby preventing Al hillocks.
一方、後者の場合は、ＴｉＳｉ層の応力がヒロックを抑
制する方向に働くとともに、Ｔｉ３ｌ層中のＴｉがＡｌ
２又はＡｌ合金層中に拡散することにより、Ａβヒロッ
クを防止するものである。そして、このＴｉはエレクト
ロマイグレージョンを抑止するためにも大きな効果を有
する。なお、前者の構造の場合、Ｔｉ１ｌ、ＴｉＮ層、
Ｔｉ１ｉｉ、Ａｌｌの４層を同一真空中で堆積すること
ができる。On the other hand, in the latter case, the stress in the TiSi layer acts in the direction of suppressing hillocks, and the Ti in the Ti3l layer
2 or diffused into the Al alloy layer to prevent Aβ hillocks. This Ti also has a great effect in suppressing electromigration. In addition, in the case of the former structure, Ti1l, TiN layer,
Four layers of Ti1ii and All can be deposited in the same vacuum.
また、上記実施例では、配線の上層に練入ρ層を用いた
が、これに限らず、既述した如く、Ａｌ−５ｒ合金層、
Ａｌ−Ｔｉ−３ｌ合金層、Ａｌ−Ｚｒ−８ｌ合金層、Ａ
ｌ−Ｔｉ合金層、Ａｌ−Ｚｒ合金層のうちいずれか１つ
を用いてもよい。ここで、Ｔｉ又はＺｒを含んだ合金層
の場合は、Ａｌのエレクトロマイグレーション、Ａｌ１
のとロックを抑制できる。また、Ｓｌを含んだ合金層の
場合は、ＡｌのＳｉの含有量を低く押えることにより、
コンタクトホール及び配線中でのＳｉの析出を押え、コ
ンタクト抵抗の増大の抑制、特にボロンが注入された拡
散層でのコンタクト抵抗の増大を抑制でき、かつ配線の
オーブンを防止できるものである。Further, in the above embodiment, a kneaded ρ layer was used as the upper layer of the wiring, but the invention is not limited to this, and as described above, an Al-5r alloy layer,
Al-Ti-3l alloy layer, Al-Zr-8l alloy layer, A
Either one of the l-Ti alloy layer and the Al-Zr alloy layer may be used. Here, in the case of an alloy layer containing Ti or Zr, electromigration of Al, Al1
and lock can be suppressed. In addition, in the case of an alloy layer containing Sl, by keeping the Si content of Al low,
It is possible to suppress the precipitation of Si in the contact hole and wiring, to suppress the increase in contact resistance, especially in the diffusion layer into which boron is implanted, and to prevent the wiring from being baked.
以上詳述した如く本発明によれば、コンタクト抵抗の増
大、アロイスパイスの発生を抑制するとともに、耐エレ
クトロマイグレーション強度を向上しえる半導体装置を
提供できる。As described in detail above, according to the present invention, it is possible to provide a semiconductor device that can suppress an increase in contact resistance and the generation of alloy spices, and can improve electromigration resistance.
第１図（ａ）〜（ｆ）は本発明の一実施例に係るＣＭＯ
Ｓトランジスタを製造工程順に示す断面図、第２図は従
来及び本発明によるコンタクトホールの大きさとコンタ
クト抵抗との関係を示す特性図である。
１・・・Ｐ型のシリコン基板、２・・・Ｐウェル、３・
・・Ｎウェル、４・・・フィールド酸化膜、５・・・素
子領域、６・・・ゲート酸化膜、７ａ、７ｂ・・・イオ
ン注入領域、８ａ、８ｂ・・・ゲート電極、９ａ、９
ｂ ・Ｖ−ス領域、１０ａ、１０ｂ・・・ドレイン領域
、１１・・・層間絶縁膜、
１２ａ、１２ｂ、１ Ｂ・ｗンタ’） ト＊−ル、１３
・・・７ｌ層、１４・・・ＴｉＮ層、１５・・・練入２
層、１６１．１６２．１９・・・配線、
１７・・・ＣＶＤ−Ｓｉ ０２ ＩＩ。
出願人代理人 弁理士 鈴江武彦
ＩＩ２図FIGS. 1(a) to 1(f) show a CMO according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the S transistor in the order of manufacturing steps, and a characteristic diagram showing the relationship between contact hole size and contact resistance according to the conventional method and the present invention. 1... P-type silicon substrate, 2... P well, 3...
...N well, 4...Field oxide film, 5...Element region, 6...Gate oxide film, 7a, 7b...Ion implantation region, 8a, 8b...Gate electrode, 9a, 9
b・V-su region, 10a, 10b...drain region, 11...interlayer insulating film, 12a, 12b, 1 B*-tor') tor, 13
...7l layer, 14...TiN layer, 15...kneading 2
Layer, 161.162.19... Wiring, 17... CVD-Si 02 II. Applicant's agent Patent attorney Takehiko Suzue II Figure 2
Claims (13)
層と、同基板上に設けられ前記拡散層に対応する部分に
コンタクトホールを有した絶縁膜と、この絶縁膜のコン
タクトホールに設けられＡｌ又はＡｌ合金層／ＴｉＮ層
／Ｔｉ層の少なくとも３層構造の配線とを具備すること
を特徴とする半導体装置。(1) A semiconductor substrate, a diffusion layer provided on the surface of this substrate, an insulating film provided on the substrate and having a contact hole in a portion corresponding to the diffusion layer, and a contact hole provided in the insulating film. What is claimed is: 1. A semiconductor device comprising wiring having at least a three-layer structure of an Al or Al alloy layer/TiN layer/Ti layer.
層／Ｔｉ層の４層構造であることを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) The wiring is Al or Al alloy layer/Ti layer/TiN
2. The semiconductor device according to claim 1, wherein the semiconductor device has a four-layer structure of Ti layer and Ti layer.
ｉＮ層／Ｔｉ層の４層構造であることを特徴とする特許
請求の範囲第１項記載の半導体装置。(3) The wiring is TiSi layer/Al or Al alloy layer/T
The semiconductor device according to claim 1, characterized in that it has a four-layer structure of an iN layer/Ti layer.
請求の範囲第１項〜第３項記載の半導体装置。(4) The semiconductor device according to any one of claims 1 to 3, wherein the Al layer is a pure Al layer.
Ｔｉ合金、Ａｌ−Ｚｒ合金のうちいずれか１つからなる
ことを特徴とする特許請求の範囲第１項又は第３項記載
の半導体装置。(5), the Al alloy layer is Al-Si alloy, Al-Ti-Si alloy, Al-Zr-Si alloy, Al-
4. The semiconductor device according to claim 1, wherein the semiconductor device is made of one of a Ti alloy and an Al-Zr alloy.
を特徴とする特許請求の範囲第１項記載の半導体装置。(6) The semiconductor device according to claim 1, wherein the content of Si in the Al alloy layer is small.
することを特徴とする特許請求の範囲第１項記載の半導
体装置。(7) The semiconductor device according to claim 1, wherein the Al layer, TiN layer, and Ti layer are deposited in the same vacuum.
層を同一真空中で堆積することを特徴とする特許請求の
範囲第２項記載の半導体装置。(8), Al or Al alloy layer/Ti layer/TiN layer/Ti
3. A semiconductor device according to claim 2, wherein the layers are deposited in the same vacuum.
ことを特徴とする特許請求の範囲第３項記載の半導体装
置。(9) The semiconductor device according to claim 3, wherein the TiSi layer/Al or Al alloy layer/TiN layer/Ti layer are deposited in the same vacuum.
ことを特徴とする特許請求の範囲第１項〜第３項記載の
半導体装置。(10) A semiconductor device according to any one of claims 1 to 3, characterized in that the TiN layer is deposited by a reactive sputtering method.
処理した後、窒化し、更にＡｌ又はＡｌ合金層を形成す
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。(11) The semiconductor device according to claim 1, wherein a TiN layer is deposited, heat-treated once in an N_2 atmosphere, and then nitrided, and further an Al or Al alloy layer is formed.
処理した後、窒化し、更にＴｉ層、Ａｌ層を形成するこ
とを特徴とする特許請求の範囲第２項記載の半導体装置
。(12) The semiconductor device according to claim 2, wherein a TiN layer is deposited, heat-treated once in an N_2 atmosphere, and then nitrided, and further a Ti layer and an Al layer are formed.
処理した後、窒化し、更にＡｌ層、 ＴｉＳｉ層を形成することを特徴とする特許請求の範囲
第３項記載の半導体装置。(13) The semiconductor device according to claim 3, wherein a TiN layer is deposited, heat-treated once in an N_2 atmosphere, and then nitrided, and further an Al layer and a TiSi layer are formed.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60100915A JPS61258452A (en) | 1985-05-13 | 1985-05-13 | Semiconductor device |
| DE19863650170 DE3650170T2 (en) | 1985-05-13 | 1986-05-07 | Semiconductor arrangement with connecting electrodes. |
| EP9494108007A EP0613180A3 (en) | 1985-05-13 | 1986-05-07 | Semiconductor device having wiring electrodes. |
| EP86106245A EP0209654B1 (en) | 1985-05-13 | 1986-05-07 | Semiconductor device having wiring electrodes |
| US07/976,664 US5278099A (en) | 1985-05-13 | 1992-11-16 | Method for manufacturing a semiconductor device having wiring electrodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60100915A JPS61258452A (en) | 1985-05-13 | 1985-05-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61258452A true JPS61258452A (en) | 1986-11-15 |
Family
ID=14286631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60100915A Pending JPS61258452A (en) | 1985-05-13 | 1985-05-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61258452A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63244861A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture of same |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPH03129755A (en) * | 1989-07-14 | 1991-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH03179745A (en) * | 1989-12-07 | 1991-08-05 | Fujitsu Ltd | Semiconductor device |
-
1985
- 1985-05-13 JP JP60100915A patent/JPS61258452A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63244861A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture of same |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPH03129755A (en) * | 1989-07-14 | 1991-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH03179745A (en) * | 1989-12-07 | 1991-08-05 | Fujitsu Ltd | Semiconductor device |
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