JPS61144872A - Semiconductor device - Google Patents

Abstract

PURPOSE:To dissolve increase of contact resistance at the time of step coverage at a side wall section of contact hole and taking out an electrode by polycrystalline Si and to contrive to improve high reliability and high integration by a method wherein an Si film is buried to the bottom section of a contact hole formed to the insulated film on a substrate through metallic nitride film with low resistance and high melting point. CONSTITUTION:A field oxide film, a thermallyu oxidized film and a polycrystalline Si film are formed on a p type Si substrate 11 and then a gate electrode 12 is formed patterning after P is duffused to the Si film. A gate oxide film 13 is formed etching the thermally oxidized film by means that the electrode 12 regards as a maks, then an n<+> type source and drain region 14, 15 is formed implanting As ion by means of the field oxide film and the electrode 12 regard as the masks. An SiO2 film 16 is deposited on all surface, making aperture to contact hole 171-173, depositing a TiN film 18, and a polycrystalline Si film 19 on all surface, making the film 19 diffuse P, forming TiN film 182 and an Al film 20 remaining the Si film 19 to the contact hole 171-173, and forming the wiring 21-23 by patterning of the film 181, 182, then MOST is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device with an improved contact hole structure.

[Technical background of the invention and its problems]

Conventionally, when taking out the electrode from the contact hole,
An AI2 membrane is used. Affi electrodes have been widely used in the field of semiconductor devices for many years because they can make good ohmic contact with both n-type and n-type diffusion layers formed on semiconductor substrates and have low contact resistance. . However, as semiconductor devices become smaller and more highly integrated, alloy spikes occur when the contact hole size becomes 3 μm and the junction depth becomes less than 1 μm, so A2 electrodes are replaced with 82.3i alloys. electrodes are used. High as an A2/Si alloy! (42
In order to withstand heat treatment at temperatures of 0 to 500° C., a material containing 1 to 2% Si is usually used. However, as the dimensions of the contact hole become finer as semiconductor devices become more highly integrated, the contact resistance with the conductor II (for example, the diffusion layer of the semiconductor substrate) increases rapidly, as shown in FIG. This is because the solid solubility of Si in He2 at room temperature is as low as 0.1%, so that an excessive amount of St in the A2-Si alloy electrode segregates, and this segregation tends to occur at the bottom of the contact hole. This is further caused by the fact that the size of the segregated 3i is as large as 0.5 to 1 μm. Therefore, the size of the contact hole is 2 μm.
Hereinafter, especially when the thickness is 1.5 μm or less, the contact resistance increases as described above. Further, the 8β.5i alloy is usually formed by sputtering technology. However, as shown in FIG.
When the i-alloy film 4 is deposited by sputtering technology,
An alloy film of sufficient thickness is not formed inside the contact hole 3, which is a problem from the viewpoint of long-term reliability and electromigration resistance.

On the other hand, polycrystalline silicon is also often used as an electrode. However, when connecting such a polycrystalline silicon electrode to a diffusion layer or polycrystalline silicon wiring on the surface of a semiconductor substrate through a contact hole, the size of the contact hole is 2.
When miniaturized to micrometers or less, the contact resistance between them increases rapidly.

This is due to the fact that an extremely thin SiO2 film is formed on the surface of the diffusion layer and polycrystalline silicon wiring exposed from the contact hole, and serves as a high-resistance material. Said 5i
Because Ozl has cracks and pinholes,
Although electrical continuity was established through these defects,
As the dimensions of contact holes become smaller, contact holes without the above-mentioned defects will exist, causing the above-mentioned problems.

[Purpose of the invention]

The present invention provides a highly reliable, 8-integration semiconductor device that eliminates the step force balayage on the side wall of the contact hole due to miniaturization of the contact hole size and the increase in contact resistance when taking out the electrode due to polycrystalline silicon. This is what I am trying to do.

[Summary of the invention]

The present invention provides a semiconductor substrate, an insulating film provided on the substrate and having a contact hole, and a silicon film embedded in the bottom of the contact hole with at least a low-resistance high-melting point metal nitride film interposed therebetween. It is characterized by the following: According to the present invention, as described above, step force rayage on the side wall of the contact hole due to miniaturization of the contact hole size and increase in contact resistance when taking out the electrode due to polycrystalline silicon are eliminated, and high reliability and high performance can be achieved. It is possible to obtain a semiconductor device with a high degree of integration.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to an n-channel MO8) transistor will be described with reference to the manufacturing steps shown in FIGS. 1(a) to 1(f).

First, a p-type silicon substrate 11 is selectively oxidized to form a field oxide film (not shown), and then a thermal oxidation treatment is performed to form island-shaped substrates 11!1ll separated by the field oxide film.
A thermal oxide layer with a thickness of 180 mm was grown on the E surface. Subsequently, a polycrystalline silicon film with a thickness of, for example, 3000 μm is deposited on the entire surface, and the polycrystalline silicon film is subjected to, for example, phosphorus diffusion to lower the resistance (for example, sheet resistance of 30Ω/hole).
A gate electrode 12 was formed by patterning using a photoetching technique. Subsequently, the thermal oxide layer is selectively etched using the gate electrode 12 as a mask to form a gate oxide film 13, and then an n-type impurity such as arsenic is ion-implanted using the field oxide film and the gate electrode 12 (not shown) as masks. The junction depth becomes 0.15 after activation.
A 04'' type source and drain am!14.15 μm were formed (as shown in FIG. 1(a)).

Next, deposit cVD-8i 02 film 16 on the entire surface,
The CVD-
Contact holes 171 to 173 having dimensions of 1.2 μm were formed in 8+02 WAl 6 by photo etching technique (as shown in FIG. 8B).

Next, a first titanium nitride (T
iN) II118x was deposited. TiNIII was formed by chemical sputtering using a mixed plasma of Ar'/N2 (mixing ratio 1:2) from a Ti target using a DC magnetron sputtering method. Note that the source region 14 and the like exposed from the contact holes 171 to 173 may be cleaned by sputter etching in the same vacuum chamber immediately before the TiN film is deposited. Next, the board 11 is
Polycrystalline silicon with a thickness of 6,500 mm is deposited on the entire surface by heating to 00 to 650°C and using a low-pressure CVD method using thermal decomposition of SiH4 gas. 19 were deposited. At this time, the polycrystalline silicon is sufficiently buried in the contact holes 171 to 173 because film formation by the low pressure CVD method has good step force coverage. Note that instead of the low pressure CVD method, a plasma CVD method, a photo CVD method, a bias sputtering method, etc. may be employed.

After this, phosphorus was diffused into the polycrystalline silicon [119] in a POCffi+ atmosphere at 900°C to reduce the sheet resistance to 2.
It was lowered to 0Ω/mouth (as shown in the same figure (C)). In this step, impurities such as phosphorus, arsenic, and boron may be implanted by ion implantation and then activated to lower the resistance of the polycrystalline silicon film.

Next, the entire surface of the polycrystalline silicon film 19 was etched to the same thickness as the polycrystalline silicon film 19, leaving the polycrystalline silicon 19- in the contact holes 171 to 173 (as shown in FIG. 4D). Next, a second TiN film 182 with a thickness of 1000 nm is deposited on the entire surface by the magnetron sputtering method described above.
Furthermore, an Aλ film 20 with a thickness of 1 μm was deposited on the entire surface (see the same figure).
e) As shown). Continuing with the above Affi! 20 and 2nd
, the first TiN films 182 and 181 are sequentially padded using a photoetching technique to form gate, source, and drain interconnections 21 to 23, thereby forming an n-channel MO.
An S transistor was manufactured (Cf in the same figure>illustration).

According to the present invention, the contact holes 17 correspond to the gate electrode 12 made of polycrystalline silicon and the n+ type source and drain regions 14 and 15 formed on the surface of the substrate 11! ~173, polycrystalline silicon 1119'' is placed on the bottom surface of the first T i N1 which has low resistance and excellent oxidation resistance!
By leaving and burying at least the polycrystalline silicon 11119'' in the arranged state, a good low-resistance connection can be achieved without interposing an SiO2 film between the remaining polycrystalline silicon 11119'' and the source region 1i!14, etc. As a result, even if the size of the contact hole is reduced to 1 μm square, the contact resistance between the remaining polycrystalline silicon 1119- and the n4 type source region 14 etc. can be suppressed to 100 to 200Ω.Moreover, the contact hole 171- By providing the first TiN film 18 on the bottom surface of the contact hole 173, a low resistance (~10"3Ω) is created in the contact holes 171 to 173 as described above.
・Since it is possible to embed polycrystalline silicon 11119' in 1), the reliability of MOS transistors, which is caused by poor step force coverage in minute contact holes and on the side walls when using AR, is improved. can eliminate the decline in

Furthermore, a second TiN film 111 is also formed on the exposed surface of the polycrystalline silicon film 19- buried in the contact holes 171 to 173.
182, A for taking out the source region 14 etc.
2 wirings 21-23 and 2 contact holes 171-173
The reaction of 3i and AI with the polycrystalline silicon film 19' inside can be prevented, and as a result, problems such as Si segregation can also be avoided.

In the above embodiment, the first TiN film was provided on the entire surface of the CVD-8i 02 II including the contact hole, but the present invention is not limited thereto. For example, as shown in Figure 2, CVD
-8i 02 Before covering the entire surface of the film, the gate electrode 12
In this case, the first TiN film 181 on the gate electrode 12 and the source,
It is necessary to form the first TiN film 181 on the drain regions 14 and 15 separately from each other.

In the above embodiment, impurities such as phosphorus are diffused into the polycrystalline silicon film buried in the contact holes of the gate bridge and the source and drain regions to lower the resistance, but the present invention is not limited thereto. For example, as shown in FIG. 3, the polycrystalline silicon film buried in the contact hole 171 of the source/drain region 14.15 is not subjected to phosphorus diffusion, and the polycrystalline silicon film is used as the high resistance element 24. You may also use it.

In the above embodiment, a TiN film was used as the high melting point metal nitride film, but it is not limited thereto.
An fN film or the like may also be used.

In the above embodiment, an example in which the present invention is applied to an n-channel MOS transistor has been described, but the present invention can be similarly applied to an n-channel MOS transistor, a complementary MOS transistor, a bipolar transistor, etc. In addition, a polycrystalline silicon film is used as the second layer wiring, and this wiring is made of Al1
Alternatively, the present invention can be similarly applied to a multilayer wiring structure connecting third layer wiring of an AI2/Si alloy.

〔Effect of the invention〕

As described in detail above, the present invention eliminates the step force burrage on the side wall of the contact hole due to the miniaturization of the contact hole size and the increase in contact resistance when taking out the electrode due to polycrystalline silicon, thereby achieving high reliability and high performance. It is possible to provide a semiconductor device with a high degree of integration.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are cross-sectional views showing the manufacturing process for obtaining an n-channel MOS transistor in an embodiment of the present invention, and FIGS. 2 and 3 show other embodiments of the present invention, respectively. FIG. 4 is a sectional view of an n-channel MOS transistor, FIG. 4 is a characteristic diagram showing the relationship between contact hole dimensions and contact resistance, and FIG. 5 is a sectional view for explaining problems with conventional semiconductor devices. 11...p-type silicon substrate, 12...gate electrode made of polycrystalline silicon, 14...n++ source region,
15...n+ type drain region 16...CVD-8
i021! , 171-173... contact hole,
18i, 182...TiNI! I, 19-...Residual polycrystalline silicon film, 21-23...A2 wiring, 24
...High resistance body. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Coater 2, 10L → 91m) Figure 5

Claims (5)

[Claims] (1) A semiconductor substrate, an insulating film provided on the substrate and having a contact hole, and silicon embedded in the contact hole with at least a low-resistance, high-melting-point metal nitride film interposed at the bottom of the contact hole. A semiconductor device characterized by comprising a film. (2) The semiconductor device according to claim 1, wherein the low resistance high melting point metal nitride film is selected from titanium nitride, zirconium nitride, tantalum nitride, and hafnium nitride. (3) The semiconductor device according to claim 1, wherein the resistivity is reduced by diffusing an impurity that becomes a donor or an acceptor into the silicon film embedded in the contact hole. (4) The semiconductor device according to claim 1, wherein the silicon film embedded in the contact hole has a high specific resistance and is used as a resistor. (5) The semiconductor device according to claim 1, wherein a high melting point metal nitride film is provided on the exposed surface of the silicon film buried in the contact hole.