JPH0235774A - Semiconductor device - Google Patents

Abstract

PURPOSE:To relieve stress in a gate electrode or interconnection by providing a multilayer structure consisting of films of high-melting metals or silicides thereof and a film of reaction barrier conductor such that each film has a thickness smaller than a specific value. CONSTITUTION:An oxide film 2 is formed on a P-type silicon substrate 1 and a thin oxide film 3 is formed in an active region. After a polycrystalline silicon film 4 is formed all over the surface by the CVD, a dopant such as phosphorus or the like is diffused to convert the polycrystalline silicon film 4 into a low resistor. Subsequently, a TiNx film 5 is formed all over the surface and a TiSix film 6, a TiNx film 7 and a TiSix film 8 are formed sequentially in that order such that each film has a thickness of 100nm or less. These layers 5, 6, 7 and 8 are etched sequentially to provide a gate electrode pattern and an interconnection pattern. Then, dopant ions are implanted into all the surface so that an implanted layer 14 is formed in the region not covered with the gate electrode. An interlayer insulating film 9 is then formed and heat treated so that source and drain layers 10 are formed. Contact holes 11 are provided and electrode patterns 12 are formed. In this manner, effect of stress to the elements can be relieved and it is made possible to provide the gate electrode and the interconnection stably and easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device having a gate electrode or wiring having a low resistance value and high reliability.

BACKGROUND OF THE INVENTION As semiconductor integrated circuits become faster and more highly integrated, higher density wiring, multilayer wiring, and lower resistance are essential.

For this reason, methods have been proposed in which high-melting point metals or their silicides are used as wiring materials instead of polysilicon, which has a high resistance value, or aluminum, which is susceptible to high-temperature heat treatment for planarization. Currently, it is possible to achieve high density by replacing the wiring material with a low-resistance refractory metal or refractory metal silicide, or by creating a polycide structure in which a low-resistance refractory metal or refractory metal silicide is laminated on a conventional polysilicon electrode. Studies are being conducted to lower the resistance.

Problems to be Solved by the Invention However, when the above structure is used, for example, in a gate electrode, the tensile stress of the high melting point metal or high melting point metal silicide is large, so a large stress is applied to the gate insulating film, which may affect transistor characteristics. It has been found. (1987, Autumn, Proceedings of the 48th Annual Conference of the Japan Society of Applied Physics, Vol. 2, p. 572゜Yokoyama et al.) One way to avoid this negative effect is to reduce the stress of the refractory metal or refractory metal silicide. One possible method is to reduce the thickness of the high melting point metal or its silicide.As in the region where the titanium silicide film thickness is 1100 nm or less in Fig. 2, in a thin film -.
Generally, there is a region where the amount of warpage of the film does not depend on the film thickness. This is thought to be because there is a discontinuous region in the film when it is initially formed, and if only this region is present, grain growth in the film is suppressed even after heat treatment. ing.

However, in this method, since the film thickness is thin, it is impossible to sufficiently reduce the resistance of the wiring. Another possible method is to combine two types of conductor films with stress applied in opposite directions to reduce the stress of the entire film.

However, in this method, since the stress difference between the films is large, problems such as peeling between the films and local stress remain. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, alleviate stress in gate electrodes or interconnections using high-melting point metals or silicides thereof, and prevent increases in resistance.

Means for Solving the Problems In order to achieve such objects, the present invention includes the following:
In order to prevent the reaction between the high-melting point metal or its silicide and the film due to heat treatment], the rear conductor film is thinned to a thickness below which the amount of warpage of each film does not depend on the film thickness. This is to create a multi-layered structure in which layers are alternately repeated.

Effect: By adopting the above-described structure of the present invention, the respective film thicknesses of the high-melting point metal or its silicide and the reaction barrier conductor film can be reduced to a film thickness where the amount of warpage of the film does not depend on the film thickness. This allows the stress of each film to be reduced. Furthermore, even if the high melting point metal or its silicide and the reactive barrier conductor film are repeatedly laminated in multiple layers in order to lower the resistance, the reactive barrier conductor metal prevents interaction between the films. Stress in the gate electrode and wiring can also be reduced while maintaining low resistance. As a result, the stress applied to the gate insulating film is also reduced, making it easier to improve the performance and reliability of the semiconductor device.

EXAMPLE The structure of a multilayer gate N-channel MO3!1 circuit of titanium silicide (TiSi)-titanium nitride (TiN)-titanium silicide (TiSi)-cutin nitride (TiS)-polycrystalline silicon according to the present invention will be described below, and its manufacturing process will be described. This will be explained in order with reference to the drawings. In this example, titanium nitride (TiN) is used as the reaction barrier conductor film, titanium silicide (TiSi) is used as the low resistance conductor film, and each film is alternately repeated twice to form a structure on polycrystalline silicon. It shows.

First, as shown in FIG. 1(a), a field silicon oxide film 2 is formed on one surface of a p-type silicon substrate 1 by a well-known selective oxidation method.
A thin gate silicon oxide film 3 is further formed in the active region.

Next, a polycrystalline silicon film 4 is formed on the entire surface by chemical vapor deposition (CVD), and then impurities such as phosphorus (P) are diffused to make the polycrystalline silicon film 4 a low resistance material. In this case, the impurity diffusion may be omitted if a doped polycrystalline silicon film, which becomes a low resistance film by heat treatment, is grown by the CVD method.

Next, a titanium nitride (TiN) film 5 is formed on the entire surface by, for example, sputtering, and then a titanium silicide (TiSi) film 6 and a titanium nitride (TiN) film 7 are formed. A titanium silicide (T i S ix) film 8 is continuously formed. In this case, in order to reduce stress in each film, the thickness of each film is set to 1100 nm or less.

Next, as shown in FIG. 1(b), the above TiSi-TiN-TiSi-
TiN-polycrystalline silicon is sequentially etched to form a gate electrode pattern and, if necessary, a wiring pattern. As a result, a predetermined pattern of TiS i 8,8a
-TiN 7,7a-TiSi6.6a-TiN
Electrodes and wiring made of 5,5a-polycrystalline Sinocon 4.43 can be formed.

Next, impurities such as arsenic (As) and phosphorus (P) are ion-implanted into the entire surface, and as shown in FIG. A implanted layer 8 is formed.

Next, as shown in FIG. 1(C), an interlayer insulating film 9 is formed on the entire surface. Subsequently, heat treatment is performed to activate the ion-implanted impurities and form the source layer and drain layer 10.

Next, as shown in FIG. 1(d), contact holes 11 are formed on the source and drain using a resist pattern formed using the well-known photolithography technique as an etching mask. Next, an aluminum film is formed on the entire surface by sputtering, for example, and an aluminum electrode pattern 12 is formed using a resist pattern formed using a well-known photolithography technique as an etching mask.
S integrated circuits can be formed.

In this example, the reaction barrier conductor film and the low-resistance conductor film are formed alternately and consecutively two times each in an even number of times, but this may be done two or more times. It goes without saying that the same effect can be obtained even if the conductor film is formed an even number of times and the low resistance conductor film is formed an odd number of times, one less than the number of times the reaction barrier conductor film is formed. In this case, the process remains the same even if the order of forming the reaction barrier conductor film and the low resistance conductor film is reversed.

Furthermore, it goes without saying that the more times the reaction barrier conductor film and the low resistance conductor film are formed, the lower the resistance becomes possible.

In addition, if the material used for the low-resistance conductor film is made thinner than the film thickness at which the amount of warpage of the film does not depend on the film thickness, the material formed the -th time and the material formed the second time onwards will be different. Needless to say, the same effect can be obtained even if the reaction barrier conductor film is used as a low-resistance conductor film.

By forming a MOS integrated circuit with the structure described above, the stress on the gate electrodes 4 to 8 and the interconnections 4a to 8a is alleviated, and as a result, the stress on the gate silicon oxide film 3 is alleviated, and the stress on the gate silicon oxide film 3 is also alleviated. It also prevents peeling.

Effects of the Invention According to the present invention, a high melting point metal or its silicide;
The thickness of each reaction barrier conductor film can be reduced to a thickness where the amount of warpage of the film does not depend on the film thickness, so the stress of each film can be reduced.Also, in order to lower the resistance value. The reason why it is necessary to repeatedly form multiple layers of the high melting point metal or its silicide and the reaction barrier conductor film is that even with such a laminated structure, the reaction barrier conductor metal prevents the interaction between the films. is prevented,
The stress of gate electrodes and wiring can also be reduced while keeping the resistance low.Also, as mentioned above, since the stress of each film in the WI layer structure is small, the stress difference between each film is small, and the The problems of peeling and local stress concentration are also eliminated.

As a result, the influence of stress on the element is alleviated, and gate electrodes and wiring can be formed stably and easily.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show a high melting point metal silicide gate MOS according to an embodiment of the present invention! FIG. 2 is a cross-sectional view of the manufacturing process showing the manufacturing method of the integrated circuit in the order of steps, and a characteristic diagram showing the thickness of the titanium-silicon 4-noid film and the amount of warpage of the film. 4... Polycrystalline silicon film for gate electrode, 5, 7
・・・・・・Game 1・TiN film for electrode, 6.8・・
...TiSi, film, 4a for gate electrode...
Polycrystalline silicon film for wiring, 5a, 7a...TiN film for wiring, 6a. 8a... TiSix film for wiring, 9...
Interlayer insulating film, 10... Source, drain layer, 1
2...Aluminum electrode. Name of agent: Patent attorney Shigetaka Awano (1 person) Is Sisokon-z also a stone? Diagram

Claims (3)

[Claims] (1) The gate electrode and wiring formed on the semiconductor substrate have a structure in which a low-resistance conductor film and a reaction barrier conductor film are alternately and consecutively laminated multiple times, and the low-resistance conductor film and the 1. A semiconductor device, wherein the thickness of the reaction barrier conductor film is set to be less than or equal to the thickness of each region where the consistency with the underlying layer is discontinuous. (2) The film thickness of the low-resistance conductor film and the reaction barrier conductor film in regions where the consistency with the base is discontinuous is 100%.
2. The semiconductor device according to claim 1, wherein the semiconductor device has a particle size of 1 nm or less. (3) Claim 1 having a polycrystalline gate electrode and wiring having a low resistance conductor film and the reaction barrier conductor film as upper layers and polycrystalline silicon as a lower layer.
3. The semiconductor device according to item 1 or 2.