JPS59208773A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59208773A
JPS59208773A JP58083087A JP8308783A JPS59208773A JP S59208773 A JPS59208773 A JP S59208773A JP 58083087 A JP58083087 A JP 58083087A JP 8308783 A JP8308783 A JP 8308783A JP S59208773 A JPS59208773 A JP S59208773A
Authority
JP
Japan
Prior art keywords
formed
si
film
layer
mo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58083087A
Inventor
Mitsutaka Morimoto
Eiji Nagasawa
Hidekazu Okabayashi
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP58083087A priority Critical patent/JPS59208773A/en
Publication of JPS59208773A publication Critical patent/JPS59208773A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To enable to obtain a low resistance wiring layer by a method wherein a high melting point metal silicide layer is covered on a shallow impurity diffusion layer and a thin poly Si layer. CONSTITUTION:An N-well region 404 and a field oxide film 405 are formed on a P type single crystal Si substrate 401. Then, a gate insulating film 406 is formed on the surface of the substrate 401 of an active region. Subsequently, an aperture is provided on the film 406 located on the region where a direct contact will be formed, and after an Si face has been exposed, poly Si is coated, and a gate electrode 407g and an output wiring 407c are formed by doping N type and P type impurities respectively. Then, the film 406 is removed using a poly Si pattern as a mask. Then, after an Mo film 410 has been coated on the whole surface, an N type doped layer 408 is formed by implanting N type impurities, and a P type doped layer 409 is formed by implanting P type impurities and Si. The interface where Mo comes in contact with Si is mixed by the above-mentioned implantation. Then, a smooth and uniform Mo silicide 411 is formed by performing a heat treatment at 400-600 deg.C in hydrogen gas. Subsequently, non-reacted Mo is removed, and a heat treatment is performed at 800 deg.C or above in nitrogen gas.
JP58083087A 1983-05-12 1983-05-12 Manufacture of semiconductor device Pending JPS59208773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58083087A JPS59208773A (en) 1983-05-12 1983-05-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58083087A JPS59208773A (en) 1983-05-12 1983-05-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59208773A true JPS59208773A (en) 1984-11-27

Family

ID=13792396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58083087A Pending JPS59208773A (en) 1983-05-12 1983-05-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59208773A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197162A (en) * 1983-04-22 1984-11-08 Nec Corp Semiconductor device
JPS6421950A (en) * 1987-06-22 1989-01-25 American Telephone & Telegraph Integrated circuit with improved tab tie
JPH04162563A (en) * 1990-10-25 1992-06-08 Nec Corp Manufacture of semiconductor device
CN103762215A (en) * 2013-12-30 2014-04-30 北京宇翔电子有限公司 Aluminum gate CMOS phase inverter and CMOS semiconductor device strengthened through radiation resistance

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5660063A (en) * 1979-10-23 1981-05-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5780721A (en) * 1980-09-15 1982-05-20 Gen Electric Method of forming low resistance contact in semiconductor device
JPS57192079A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5660063A (en) * 1979-10-23 1981-05-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5780721A (en) * 1980-09-15 1982-05-20 Gen Electric Method of forming low resistance contact in semiconductor device
JPS57192079A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197162A (en) * 1983-04-22 1984-11-08 Nec Corp Semiconductor device
JPS6421950A (en) * 1987-06-22 1989-01-25 American Telephone & Telegraph Integrated circuit with improved tab tie
JPH04162563A (en) * 1990-10-25 1992-06-08 Nec Corp Manufacture of semiconductor device
CN103762215A (en) * 2013-12-30 2014-04-30 北京宇翔电子有限公司 Aluminum gate CMOS phase inverter and CMOS semiconductor device strengthened through radiation resistance

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