JPS59208773A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to obtain a low resistance wiring layer by a method wherein a high melting point metal silicide layer is covered on a shallow impurity diffusion layer and a thin poly Si layer. CONSTITUTION:An N-well region 404 and a field oxide film 405 are formed on a P type single crystal Si substrate 401. Then, a gate insulating film 406 is formed on the surface of the substrate 401 of an active region. Subsequently, an aperture is provided on the film 406 located on the region where a direct contact will be formed, and after an Si face has been exposed, poly Si is coated, and a gate electrode 407g and an output wiring 407c are formed by doping N type and P type impurities respectively. Then, the film 406 is removed using a poly Si pattern as a mask. Then, after an Mo film 410 has been coated on the whole surface, an N type doped layer 408 is formed by implanting N type impurities, and a P type doped layer 409 is formed by implanting P type impurities and Si. The interface where Mo comes in contact with Si is mixed by the above-mentioned implantation. Then, a smooth and uniform Mo silicide 411 is formed by performing a heat treatment at 400-600 deg.C in hydrogen gas. Subsequently, non-reacted Mo is removed, and a heat treatment is performed at 800 deg.C or above in nitrogen gas.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit using a complementary Mis (hereinafter abbreviated as CMO8 including MIS) FET.

Semiconductor integrated circuits, whose basic circuit is a CMOS inverter, take advantage of their features of low power consumption, low voltage operation, and large noise margin to create large-capacity memories and large-scale logic. For example, in a conventional CMOS inverter as shown in a schematic partial cross-sectional view in FIG. P channel MO
An A wiring 105c is required to interconnect the north end of the 8FET with the p-type impurity dope layer 10.4. This wiring usually also serves as the output line to the next stage inverter.
It extends to the contact area with the next stage gate polysilicon. This wiring is also GND line (ground line) 1
Since the AJ layer common to the 05aX power supply line 105b is used, there are many restrictions in designing the mask pattern.

Besides, these A! The wiring is a relatively thick interlayer insulating film 10
It is necessary to contact the NFF1 doped layer, the p-type dope layer, and the gate polysilicon of the next stage inverter through the contact hole opened in 6. A sufficient overlap margin is required between the contact hole and the AI wiring (6.6), and the contact hole itself also needs to be large enough to embed AA', which limits the integration density. Improvement was difficult.

The structure shown in FIG. 2 was proposed to solve some of the drawbacks of the structure shown in FIG. That is, N channel MO8l
An n-type doped layer 201 that becomes the drain of i'BT and a p-type doped layer 20 that becomes the source of the P-channel MO8FET.
2 and the polysilicon layer 203c in the same layer as the gate 203g.
It is an attempt to interconnect with each other.

The advantage of this is that the polysilicon can be extended to the next gate as it is, so that l can basically be used exclusively for power supply wiring, increasing the degree of freedom in mask design and allowing higher integration. Also, polysilicon 203C and silicon doped J@201'
, 202' (hereinafter referred to as direct contact) occupies an area of A! in FIG. Output wiring 105
Another advantage is that it is sufficiently small compared to the area occupied by the contact between C and p- or n-type doped layer 1 (14, 102). Insulating film] 06 side etch margin is required, and the contact hole between AI and doped layer is AA.
This is because it is necessary to design a pattern with a sufficient overlap margin inside the doped layer region to prevent junction short-circuit accidents caused by the γ-loy spikes. On the other hand, in the case of direct contact, since the gate polysilicon 203g and the output wiring polysilicon 203c are in the same layer, there is no need for an overlap margin between them, and the doped layer 2 (
This is because the formation of J 1202 and the diffusion of impurities from the polysilicon 203c are carried out in a self-aligned manner, so no separate alignment margin is required. Furthermore, when wiring is made of polysilicon in the next stage, at least one contact hole between the gate polysilicon in the next stage and Al is reduced, which is also advantageous for improving the degree of integration. However, the structure of FIG. 2 also has drawbacks. Normally, the gate polysilicon of the CMO8 and the N-channel MO8 button are doped with n-type impurities (203g), and the nP-channel InO3 is doped with pm impurities (203g, J). Therefore, the wiring polysilicon 203c is also connected to the drain of the N-channel MO8 through a direct contact, 2o3c, n, and the p-type 203c, p is connected to the source of the P-channel MO8.
Two areas are created, and a pn image is created outside the field of view. In this way, two regions with different potentials are created in the output wiring, so it is necessary to short-circuit them, and the Al bridge 2
04c is still required. This person is 7! Although this occupies a small area, it still becomes a constraint on the AJ pattern design.

In addition, recent general trends include the miniaturization of element dimensions in order to increase the flexibility of MOS integrated circuits, the thickness of special polysilicon layers, and the junction depth of p-type and ng-todo single layers that serve as sources and drains. The increase in net resistance due to the miniaturization in the depth direction increases the time constant when these layers are used as wiring between elements, which prevents high-speed operation as an integrated circuit.
Furthermore, the increase in voltage drop at various parts causes a reduction in the operating margin, which poses a major problem.

For example, at present, a relatively shallow nM dope layer with a junction depth of about 0.3 .mu.m can be formed by arsenic ion implantation, but its sheet resistance is quite large at 30 to 50 .OMEGA.4.

If a doped layer with a junction depth of 01 to 02 .mu.m, which will be required in the near future, is created by ion implantation, the layer will have a junction depth of 100 .OMEGA./or more and cannot be used as a wiring.

Furthermore, it is OK for shallow junction regions of about o, i ~ 0.2 μm.
In ohmic contacts made of l-based metals, local diffusion and alloying reactions called alloy spikes occur, which can easily penetrate shallow junctions and cause electrical shorts with the substrate.

In this way, forming shallow junctions using only conventional ion implantation or doping polysilicon with impurities is unfavorable in terms of electrical resistance and ohmic contact, and cannot be avoided when miniaturizing the structure shown in Figure 2. There are no drawbacks.

These problems include the necessity of shorting the pn junction in the output polysilicon wiring, the increase in sheet resistance of thin polysilicon and shallow impurity doped layers, and the problem of alloy spikes at the contact with the aluminum thread wiring. In order to solve the problem all at once, it is conceivable to form metal silicide on the surface of the polysilicon and the surface of the shallow impurity doped layer. However, when silicides of noble metals such as platinum and palladium are formed, the resistance value increases significantly due to heat treatment at about 850C because the thermal stability of these noble metal silicides is insufficient. It is difficult to put it into practical use because it tends to have the problem of reaction with metals. On the other hand, in the case of so-called high melting point silicides such as molybdenum, tungsten, tantalum, and titanium, there is no problem in terms of the heat resistance of these materials themselves. Therefore, using conventional technology, we used silicides of these high melting point metals as sources.
Conventionally, the following two methods have been considered for application to the purpose of forming on the drain region to reduce resistance.

The first method is to deposit a high melting point metal silicide film itself with a desired composition ratio using a method such as sputtering or X-nitrogen deposition. However, in this method, 800
By high-temperature heat treatment at temperatures above about °C, the silicide film of the refractory metal is bonded to the source layer, which is doped with impurities at a high concentration.
The ohmic properties at the interface with the drain region deteriorate, resulting in an increase in the effective series resistance of the north drain region.

Furthermore, this method has the disadvantage that since a film having a metal silicide composition is deposited in advance, it is not easy to form the film in a self-aligned manner only in desired regions such as source/drain regions.

In the second method, instead of depositing the high melting point metal silicide itself, after depositing a high melting point metal film, the high melting point metal and silicon are reacted by heat treatment to form a silicide layer. . In this method, a high melting point metal film is deposited after exposing the silicon surface in desired areas such as the north drain region. ! By performing R, a sieve melting point metal layer can be formed in a self-aligned manner only in desired portions. However, when this method was attempted to remove the pods, it was found that the reproducibility and uniformity of the reaction between the high melting point metal and silicon doped with high concentration impurities was extremely poor. That is, high melting point metal J:
In some cases, almost no silicide reaction with silicon occurred, and in some cases, a weak reaction occurred between samples or within the sample. Ko 1. ．． It is thought that the silicide formation reaction is sensitively influenced by the interface between the high melting point metal and silico/and the state of the high melting point metal or silicon, resulting in fc.

Furthermore, in such a method, the silicide-forming reaction force between the melting point pottery and silicon; It has also been found that there is a problem in that the metal film protrudes into the insulating e+ -1: +C region, and the silicide of the high melting point metal is formed only in the desired region in a self-aligned manner.

Furthermore, in the case of high-melting point metal silicides formed by either of the above two methods, the crystal grain size becomes polycrystalline on the order of In this way, the surface smoothness and homogeneity are not good, and a high-temperature heat treatment is performed after forming a polycrystalline high-melting-point metal silicide layer on the highly doped silicon crystal surface. In this case, a phenomenon occurs in which impurities doped into the silicon crystal diffuse into the grain boundaries of the silicide layer and escape from the silicon crystal, or when an aluminum-based metal for ohmic contact is deposited. It was found that aluminum and silicon easily interdiffused through grain boundaries, resulting in so-called spikes.

As described above, it has been found that the conventional method or the refractory metal silicide layer formed by the conventional method is unsuitable for application to the purpose of lowering the resistance of the source/drain regions.

In order to eliminate the drawbacks of the conventional structure described above, the present inventor has proposed a semiconductor device having a structure as shown schematically in cross section in FIG.

A P-channel MO8F'ET is formed in an n-well 302 formed on a p-ML single-crystal silicon substrate 301, and an N-channel MO8FET is formed on a p-type silicon substrate. 303 is a gate insulating film, 304g is a gate electrode made of polysilicon, 305c is N-chai, #MO8F
nfi-doped layer 306 which becomes the drain of 'ET' and p-doped layer 307 which becomes the source of P-channel MO8FET.
This is a polysilicon output wiring that interconnects the two and further extends to the gate of the next stage inverter.The n-doped and pm-doped regions have a υ boundary, which forms a pn junction J.

A smooth and homogeneous molybdenum silicide film 308 is formed on the entire surface of a shallow n-type doped layer 306 which becomes the north drain of the N-channel transistor, and polysilicon 305c of the output wiring of the P-channel transistor.

By covering shallow impurity diffusion layers and thin polysilicon with molybdenum silicide in this way, the sheet resistance of these shallow diffusion layers and thin polysilicon can be made very low. -18
For n-type doped JrJ with a junction depth of μm (the thickness of the n-type part is 0.08 μm), a value of 13 to 14 Ω gold is achieved. Using such low-resistance wiring improves operating speed.

In addition, the voltage drop in the wiring is small and the reverse operation margin is widened. Furthermore, the resistance of the 111-force polysilicon surface where an sil-n junction is formed between the p-type and nd4 regions can be lowered by using molybdenum silicide, and the potential can be made the same. Since there is no need for ohmic contact with the Al-based interconnection, the degree of freedom in designing the AIi-based wiring pattern is improved, and high integration becomes possible.

An object of the present invention is to provide a method for manufacturing such a semiconductor device.

According to the present invention, after forming an island-like second conductivity type well region, a silicon substrate region, and a field region of a thick insulating film separating them on the surface of a single-crystal silicon substrate of a first conductivity, After depositing a gate insulating film on the silicon surface and making an opening in the gate insulating film in a part of the well region and a part of the silicon substrate region, which are the regions where direct contact between the polysilicon and the silicon substrate will be formed later. , a polysilicon film is deposited, and the polysilicon film on the region where the S-channel MISFET is to be formed later is doped with an n-type impurity, and the polysilicon film on the region where the P-channel MISFET is to be later formed is doped. is doped with p-type impurities and formed into gate electrodes and inter-element interconnections, and then using the polysilicon pattern as a mask, the gate insulating film remaining on the silicon surface other than that covered with the polysilicon is removed, and then a high After depositing a melting point metal thin film by sputtering method etc., N-channel MIS
In the region where the FET is to be formed, n-type impurities are implanted, or electrically inactive ions and n-disc impurities are superimposed in the silicon crystal, and in the region where the P-channel MISFET is to be formed, p-type impurities or Injecting electrically inert ions and p-type impurities in a silicon crystal in a layered manner under conditions sufficient to mix the interface between the high-melting point metal film and the single-crystalline or polycrystalline silicon in contact with it, Next, a heat treatment is performed at 400 to 600°C in a non-oxidizing gas to turn the mixed layer into a smooth and homogeneous high melting point metal silicide layer.Then, the remaining unreacted metal is removed, and then a non-oxidizing gas is applied. A method for manufacturing a semiconductor device is obtained, which is characterized by applying heat treatment at 800° C. or higher.

Next, the present invention will be explained using one embodiment thereof.

This embodiment is a method for manufacturing the CMOS Impark shown in FIG. .

Figure 4 (aj, (b), (C1, (C1), (el,
(Q is a series of schematic cross-sectional views of the inverter at the main steps in manufacturing this CMOS impaque.

First, a PFFI single crystal silicon substrate 4 with a specific resistance of Ω・硼
01 is prepared, and the film thickness is 6000X by normal thermal oxidation method.
An oxide film 402 is formed. An opening is made in the oxide film in the area where the so-called N-well region is to be formed using a normal photoetching method, and then an oxide film 40 with a thickness of 1000× is formed on the surface of the opening.
3, the phosphorus ions were accelerated at a voltage of 150 Ke.
Vl is implanted at a dose of 7 x 10'' tx=, and heat treatment is performed at 1200° C. for 19 hours in nitrogen gas to form an N well region 404 with a depth of about 7 μm.

(Figure (a)) Next, after removing all the oxide films, a fee-noside oxide film 405 is formed in a region (field region) other than the active region where a transistor is formed by a normal selective oxidation method. Next, I numb 30 on the silicon board surface of the active area.
A gate insulating film 406 of 0x is formed. (Figure (b)) Next, a hole is opened in the gate insulating film 406 in the region where the direct contact is to be formed, and the silicon surface is exposed, and then the thickness is 3.
000 A polysilicon is deposited.

After the polysilicon is deposited, the polysilicon on the region where the N-channel 108FI)T is to be formed is doped with an n-type impurity, and the polysilicon on the region where the P-channel MO8FET is to be formed is doped with a p-type impurity.

Next, this polysilicon film is used as a gate electrode 407g.

It is formed as an output distribution 407c. Here, it is expressed as a region where an N-channel or P-channel MO8FET is formed, but it also includes the output wiring 407c. This means that not only the Kuuma Shigade Senpoku 407g but also the output terminal and 407c are doped with n/p type impurities.

Next, gate polysilicon 407gn, 407g p
Since the silicide obtained by the method of the present invention can form shallow junctions and at the same time self-align with the polycrystalline silicon surface any pattern of single crystals, it is extremely effective in improving yield.

In addition, in the method of the present invention, after performing ion implantation, 4
A two-stage heat treatment method is used in which heat treatment is performed at a relatively low temperature of 00 to 600 °C in a non-oxidizing atmosphere, and then heat treatment is performed at a temperature of 800 °C or higher after removing unreacted metals with a melting point. However, this two-stage heat treatment is extremely important in forming a uniform and smooth high melting point metal silicide in a self-aligned manner with respect to the opening. That is, if the first annealing after ion implantation is performed at a high temperature of, for example, about 800° C. or higher, silicide will be formed protruding from the opening. Therefore, after first annealing at low temperature, 1.
By removing unreacted high melting point metal, silicide is formed in self-alignment with the opening. If this annealing is performed in an oxidizing atmosphere, the high melting point metal film on the surface may be oxidized and sublimated.

After this, heat treatment at about 800"C or higher is carried out for the purpose of reducing the resistivity of the silicide layer and electrically activating the implanted ions. This heat treatment is performed using a reducing heat treatment containing H2 gas. If the process is carried out in a gas atmosphere, the uniformity and smoothness of the silicide formed by the low-temperature heat treatment will be lost, resulting in the formation of many defects such as pinholes, making it difficult to use it in integrated circuits. i-j: first not. Therefore,
It is important to perform heat treatment at 80,000 or more in a non-reducing gas atmosphere, such as an inert gas, oxygen, water vapor, or a combination of these gases, or in a pure wall to maintain the uniform and smooth properties of the silicide. be.

In this example, M is used as the F'i high melting point metal machine.

As for the case using W 3 Ta ) T
Similar effects were confirmed for other high melting point metals.

In fact, the 11-type doped layer f'iA s which becomes the source and drain of the N-channel MO8FET was ion-implanted only, but in order to form a very shallow junction, the amount of 5P for doping was As<on. It is also possible to combine the implantation of metal and silicon with the implantation of ions. In this case, the order of ion implantation may be either first. The same applies to the combination of B ions and Si ions. Further, the ions for interfacial mixing are not limited to Si, but may be inert elements such as Ar.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a conventional CMOS inverter, FIG. 2 is a schematic cross-sectional view of a CMOS inverter proposed to solve part of the problem, and the third factor is a CMOS inverter according to the present invention. FIG. 4 is a schematic sectional view showing an embodiment of an inverter, and FIG. 4 is a schematic sectional view showing main steps of an embodiment of the manufacturing method according to the present invention. 101.301,401...p-type silicon substrate, 10
3,302゜404...n well, 102,201,
306,408,201,408'''nnTodo-1 layer 1
042o2307,409,202,409 horn...-p-type doped layer, 105,204...AAI,
106, 412... interlayer insulating film, 203, 304,
305,407...Polysilicon, 308411...
- High melting point metal silicide, 303406... Gate insulating film, 410... High melting point metal film, 405... Field oxide film, 402... Thick silicon oxide film, 403...
・Thin silicon oxide film, C... Subscript indicating output wiring,
g... A subscript indicating gate electrode, n... A subscript indicating n-type impurity doping, p... A subscript indicating no pm impurity doping. Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 406 4D'1 Procedural Amendment 59.8. i Director General of the Patent Office 1, 1981, Indication of Case 1982 Patent Application No. 08308
No. 7, No. 2, Title of the invention: Method for assembling semiconductor devices 3, Relationship to the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4; Agent 5, Drawing 6 to be amended, Contents of amendment: (c) and fdl in Figure 4 of the drawings attached to this application will be amended as shown in the attached drawings. Illustration 4

Claims (1)

[Claims] An island-shaped second
After forming a well region and a silicon substrate region as well as a field region of a thick insulating film to separate them, a gate insulating film is deposited on the silicon surface other than the field region, and a gate insulating film is quickly formed between the polysilicon and the silicon substrate. After openings are made in the gate insulating film in a part of the well region and a part of the silicon substrate region, which are the regions where direct contacts are to be formed, a polysilicon film is deposited, and then an n-cha?・Le MI
The polysilicon film on the region where SI"ET is to be formed is doped with n-containing material, and later, p The polysilicon pattern is then doped with mold impurities and formed into gate electrodes and interlayer wiring, and the gate insulating film remaining on the silicon surface other than that covered with the polysilicon is removed using the polysilicon pattern as a mask. After depositing the N-channel MISFET
Nu impurities or electrically inactive ions and nji impurities are implanted in the silicon crystal in the region where the transistors are to be formed, and pm impurities or pm impurities in the silicon crystal are implanted in the regions where the P channel M18FF and T are to be formed. Electrically inactive ions and p-type impurities are implanted in layers to mix the interface between the high-melting point metal film and the single crystal or polycrystalline silicon in contact with it, and then heated for 400 min in a non-oxidizing gas.
A heat treatment is performed at ~600°C to make the mixed layer a smooth, homogeneous high melting point metal silicide layer, and then residual unreacted metal is removed, followed by a heat treatment at 800°C or higher in a non-reducing gas. A method for manufacturing a semiconductor device characterized by the addition of Iban and Tonafuharu.