JPH03220772A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of defective conductance by providing a barrier metal layer comprising a high-melting-point metal layer or a high- melting-point metal silicide layer on electrodes on the diffused region of a semiconductor substrate, and providing a metal wiring layer on the barrier metal layer. CONSTITUTION:Electrodes 108 and 113 are provided on diffused regions 109 and 110 provided on a semiconductor substrate 100. A barrier metal layer 117 comprising a high-melting-point metal layer or a high-melting-point metal silicide layer is provided on the electrodes 108 and 113. A metal wiring layer 115 is provided on the barrier metal layer. When the barrier metal layer 117 comprising the high-melting-point metal layer or the high-melting-point metal silicide layer is provided between the electrodes 108 and 113 and the metal wiring 115 provided on the diffused regions 109 and 110 of a bipolar transistor element and a MOS transistor element which are provided on the semiconductor substrate 100 in this way, the defective contact between the electrodes 108 and 113 and the metal wiring 115 is prevented, and the reliability of the semiconductor device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device (hereinafter referred to as a BiCMO3 semiconductor device) having a bipolar transistor element and a CMO8 transistor element on the same semiconductor substrate.

[Conventional technology]

In recent years, the miniaturization of gate electrodes in MO8 type LSIs has been progressing as a means of achieving higher density, higher integration speed, and higher speed. When the gate electrode is used as part of a wiring layer, the material constituting the gate electrode is generally doped polysilicon, which has a layer resistance of about 20 Ω/hole.

Therefore, the wiring resistance value increases with miniaturization, and in order to reduce this wiring resistance value, high melting point metal silicide such as tungsten silicide is used as the material of the gate electrode.

On the other hand, in bipolar LSI, P of single crystal silicon
It may be necessary to have a diode that conducts at a voltage lower than that required for the N-junction to conduct in the forward direction. As such a diode, a metal-semiconductor diode (hereinafter abbreviated as SBD) is easy to manufacture and has good high frequency characteristics.

> is widely used.

The optimal electrode for the SBD is a platinum silicide layer, which has an SBD area of 100 μm 2 and requires a voltage of approximately 400 mV for forward conduction. With a high melting point metal silicide layer such as tungsten silicide, the forward voltage is lower than 400 mV, and the SBD area can be small, but the SBD area is too small to obtain the desired forward voltage as a semiconductor device, making it difficult to manufacture. This causes problems in the controllability of the directional voltage.

In addition, when the forward voltage becomes larger than 400mV,
Forward voltage of single crystal silicon PN junction is approximately 600m
There is no difference with V, and the need for SBD becomes meaningless.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, in order to ohmically connect each electrode to a wiring layer made of, for example, aluminum, it is necessary to alloy each electrode and the aluminum layer by heat treatment or the like. It is well known that in this process, if each electrode is made of a material containing silicon or the like, silicon will diffuse into the aluminum wiring layer and recrystallize. The size of silicon due to this recrystallization can reach 1 to 2 μm. In the above-mentioned high-density, highly integrated semiconductor device, it is desired to reduce the size of the electrode numbering window and the opening window for connecting lower and upper layer wiring.

However, as mentioned above, the size of the aperture window etc. is set to 2.
When it is 0 μm or less, the contact resistance value between the ohmically connected electrode portion and the aluminum wiring layer contact portion increases,
There was a problem in that poor conduction occurred.

Furthermore, because the SBD electrode also undergoes an alloying reaction with the wiring layer such as aluminum due to heat treatment for ohmic connection, the SBD forward voltage changes over time, resulting in a problem that the semiconductor device no longer functions.

[Means to solve the problem]

The semiconductor device of the present invention is a semiconductor device having a bipolar transistor element and a MOS transistor element provided on the same semiconductor substrate, in which a high melting point metal layer or It has a barrier metal layer made of a high melting point metal silicide layer, and a metal wiring layer provided on the barrier metal layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are a sectional view and an enlarged view of part A of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

First, as shown in FIG. 1 (a), a P-type silicon substrate 1
00, an N+ type buried region 101 and a P+ type buried region 102 are formed on the P type silicon substrate 100 including the N+ type buried region 101 and the P+ type buried region 102.
A type epitaxial layer 103 is grown. Next, bipolar transistor (hereinafter referred to as B i pTR) elements and MOS transistor (hereinafter referred to as MOS TR)
P-type silicon substrate 10 for electrically insulating and separating the
P-type line edge region 104 reaching 0 and N-channel MOS
P-type well regions 105 are respectively formed to reach the P-type silicon substrate 100 for forming the TR. Next, selective oxidation is performed using the oxidation-resistant film as a mask to form a field oxide film and define an element formation region. Next, the oxidation-resistant film is removed, and the surface of the element formation region is thermally oxidized to form a gate oxide film 106. Next, the substrate concentration is controlled by ion implantation in order to control the desired threshold voltage of the MOS TR. Next, a silicon oxide film is formed to a thickness of about 0.2 μm by vapor phase growth or the like to form a P-type base region 107 of B i pTR. Next, a polycrystalline silicon layer is applied to the entire surface of the substrate to a thickness of approximately 50 mm.
N-type impurities are added to the polycrystalline silicon layer by thermal diffusion or the like, and a tungsten silicide layer with a thickness of approximately 0.2 μm is formed on the upper layer by sputtering or the like.

Next, the tungsten silicide layer and the polycrystalline silicon layer are selectively and sequentially etched using the photoresist film as a mask to form a gate electrode 108. Next, for example, arsenic ions are implanted by ion implantation using the aluminum layer as a mask to form the source/drain diffusion layers 1 and 09 of the N-channel MOS TR, and boron ions are implanted to form the source/drain diffusion layers 110 of the P-channel MO8TR.
formal precepts. Incidentally, when implanting boron ions, the resistance can be reduced by implanting the boron ions also into the base part outside the emitter region assembly of BipTR.

Next, as shown in FIG. 1(b), a silicon oxide film 11 with a thickness of approximately 0.2 μm is formed over the entire surface by vapor phase growth or the like.
1, and the gate electrode of the MO3TR and B i p
Insulate the electrodes of the TR. Next, in order to form the emitter region 112 of BipTR, the silicon oxide film 111 is selectively etched to form an opening. Next, a polycrystalline silicon layer is deposited to a thickness of 0.25 μm on the surface including the openings,
N-type impurities are added to the polycrystalline silicon layer by ion implantation or the like, and the impurities are diffused from the polycrystalline silicon layer to the surface of the base region 107 to form the emitter region 1 of BipTR.
form 12. Next, the polycrystalline silicon layer is selectively etched to form an emitter electrode 113 of B i pTR. At this time, if necessary, the N+
A collector region of the mold and a collector electrode can also be formed.

Next, as shown in FIGS. 1(c) and 1(d), a silicon oxide film 114 containing impurity phosphorus is deposited to form opening windows for interconnecting elements and for forming SBDs. An aperture window is formed in the silicon oxide film 114. Next, a platinum film is deposited on the entire surface by vapor deposition or the like and sintered at 600° C., thereby forming a platinum silicide layer 116 in the opening window portion where the tungsten silicide gate electrode is not intended to be taken out.

Next, the unreacted platinum film is removed by etching with aqua regia. Next, a tungsten layer 117 containing several percent titanium is deposited by vapor deposition or the like, and selectively etched with a mixed aqueous solution of hydrogen peroxide and ammonium hydroxide to form a barrier metal layer on the platinum silicide layer 116 in the opening window. Form.

Next, an aluminum film is deposited using a vapor deposition method or the like and selectively etched to form an aluminum wiring layer 1 that interconnects the elements.
form 15. Next, each electrode and aluminum wiring layer 1
In order to connect 15 with an ohm, heat treatment is performed at, for example, 400° C. for about 20 minutes, and the BiCMO8 semiconductor device is completed.

Incidentally, further upper layer wiring can be formed if necessary.

FIGS. 2(a) and 2(b) are a sectional view and an enlarged view of part B of a semiconductor chip according to a second embodiment of the present invention.

As shown in FIGS. 2(a) and (b), until each transistor region is formed and the platinum silicide layer 116 is formed in the opening window portion, the steps described in FIGS. 1(a) to (c) are performed. It is formed in the same process as in Example 1. Next, a tungsten silicide layer 118 is deposited by a sputtering method, an aluminum layer 215 is deposited on the tungsten silicide layer 118 by a vapor deposition method, etc., and the aluminum layer 215 and the tungsten silicide layer 218 are selectively and sequentially etched to form an interconnect between the elements. Form a wiring layer to connect the Next, in order to establish an ohmic connection between each electrode and the wiring layer, a heat treatment is performed at 400° C. for about 20 minutes to complete a BiCMO8 semiconductor device.

〔Effect of the invention〕

As explained above, the present invention provides a barrier made of a high melting point metal layer or a high melting point metal silicide layer between an electrode provided on a diffusion region of a bipolar transistor element and a MOS transistor element provided on a semiconductor substrate and a metal wiring. Providing the metal layer has the effect of preventing poor contact between the electrode and the metal wiring and improving the reliability of the semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are a cross-sectional view and an enlarged view of part A of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention, and FIGS. b) is a sectional view and an enlarged view of part B of a semiconductor chip according to a second embodiment of the present invention. 100...P type silicon substrate, 101...N+ type buried region, 102...P+ Mold embedding area, 103...
- N type epitaxial layer, 104... P type line edge region,
105... P type well region, 106... Gate oxide film, 107... P type base region, 108... Gate electrode, 109... N type diffusion region, 110... P type diffusion region 10 area, 111, 114... silicon oxide film, 112...
・Emitter region, 113... Emitter electrode, 115・
...Aluminum wiring layer, 116...Platinum silicide layer, 117...Tungsten layer, 118...Tungsten silicide layer.

Claims (1)

[Claims] In a semiconductor device having a bipolar transistor element and a MOS transistor element provided on the same semiconductor substrate, from a refractory metal layer or a refractory metal silicide layer provided on an electrode provided on a diffusion region provided on the semiconductor substrate. What is claimed is: 1. A semiconductor device comprising: a barrier metal layer; and a metal wiring layer provided on the barrier metal layer.