JPS6347962A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the decrease in a manufacturing yield due to an aluminum alloy spike and to accelerate a bipolar transistor by composing electrodes connected to bonded parts in a multilayer of an upper layer aluminum and an aluminum diffused barrier metal provided on the lower layer of the aluminum. CONSTITUTION:Electrodes connected to the bonded parts of transistors in a semiconductor device in which a bipolar transistor, an N-channel MOS transistor and a P-channel MOS transistor are integrally formed on the same semiconductor substrate 1 are composed in a multilayer of at least an upper layer aluminum 24 and an aluminum diffused barrier metal 23 provided on the lower layer of the aluminum 24. A lowermost layer metal layer 21 made of a platinum silicide layer ohmically contacted with a diffused layer for generating a Schottky barrier for a semiconductor substrate is, for example, formed on the lower side of the metal 23. Titanium is, for example, used as the metal 23. Thus, a Bi-CMOS semiconductor device having a shallow junction is miniaturized to improve its operating speed and its reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a MOS transistor and a bipolar transistor coexist, and particularly relates to a semiconductor device that operates at high speed.

[Conventional technology]

Conventionally, a semiconductor device in which a MOS transistor and a bipolar transistor coexist on one semiconductor substrate, the so-called Bi
-CMO3 semiconductor devices have been proposed.

This type of semiconductor device will be explained according to the manufacturing process diagrams shown in FIGS. 3(a) to 3(e).

First, as shown in FIG. 3(a), for example, a P-type earth door body substrate 3
1, an N-type buried layer 32 and an N-type epitaxial device 35a are formed in a region where an NPN bipolar transistor is to be formed, and a P-type buried layer 34 and a P-type well 36 are formed in a region where an N-channel MOS transistor is to be formed. Furthermore, an N-type buried layer 33 and an N-type epitaxial layer 35b are formed in a region where a P-channel MOS transistor is to be formed.

Then, a selective oxidation method (LOCO) is applied to the surface of the semiconductor substrate 31.
An element isolation insulating film 37 is formed by method C) to isolate each transistor region, and a gate oxide film 38 is further formed.

Gate electrodes 45 and 47 are formed of polycrystalline silicon on this gate oxide film.

Furthermore, after forming the P-type base region 40 of the NPN bipolar transistor, an opening in the emitter region and a polycrystalline silicon emitter electrode 44 made of second polycrystalline silicon are formed, and an ion implantation mask material 55 such as aluminum is processed. Then, the emitter and collector electrode portions of the NPN bipolar transistor and the source/drain regions of the N-channel MOS transistor are exposed simultaneously, and a high dose of arsenic is ion-implanted to form the N-type diffusion layer 46 and the emitter 4.
2. A collector electrode 43 is formed.

Next, as shown in FIG. 5B, an ion implantation mask material 56 made of aluminum or the like is processed to simultaneously expose the base contact portion of the NPN bipolar transistor and the source/drain region of the P channel MOS transistor, and a high dose of boron is implanted. P-type diffusion layer 48 is formed by ion implantation.
and a base contact portion 41 is formed.

Thereafter, a phosphosilicate glass (PSG) film 49 is deposited as an interlayer insulating film, as shown in FIG. 4(C), and reflowed by heat treatment to reduce the level difference of the gate polycrystalline silicon electrode, etc. Next, as shown in FIG. ) A contact hole 52 is formed to form each electrode of a transistor and a bipolar transistor.

Next, as shown in the same figure (e), with aluminum 54,
For example, 450°C, N
Bi-C with the desired function is heat-treated in a 2 atmosphere for an appropriate time.
The MO3 semiconductor device has been completed.

[Problem that the invention seeks to solve]

In the conventional B r -CMO3 semiconductor device described above, the emitter 4 of the bipolar transistor is
2. N-type diffusion layers such as the collector contact portion 43 and the source/drain region 46 of the N-channel MOS transistor are formed at the same time, and P-type diffusion layers such as the base contact portion 41 of the bipolar transistor and the source/drain region 48 of the P-channel MOS transistor are formed at the same time. are formed simultaneously.

After that, contact holes 52 are opened in these diffusion layers, wiring and connections of aluminum 54 are applied thereto, and then heat treatment is performed.

The problem with the trowel is aluminum alloy spikes when contact holes are opened on the N-type diffusion layer and aluminum wiring is provided.

That is, in order to increase the speed of Bi-CMO3 semiconductor devices, it is necessary to simultaneously reduce the size of both bipolar transistors and MOS transistors, and to achieve this, the junctions that make up each element must be made shallower. . However, if the emitter junction of the bipolar transistor in a Bi-CMO3 semiconductor device is made shallow and the junction of the N-type diffusion layer of the N-channel MO3I-transistor is made shallow at the same time, the probability that the above-mentioned aluminum alloy spike will occur is extremely high. becomes larger.

When this aluminum alloy spike occurs, the junction at that part is destroyed, inducing unnecessary leakage current in circuit operation, reducing the reliability of the B i -CMO3 semiconductor device, and extremely reducing the manufacturing yield. There is a problem.

[Means for solving problems]

The semiconductor device of the present invention does not cause a decrease in manufacturing yield due to the aluminum alloy spikes of bipolar transistors and MOS transistors having extremely shallow junctions, and in addition, a Schottky clamp diode is formed at the same time to form bipolar transistors. This aims to increase the speed and prevent an increase in contact resistance due to miniaturization of contact holes.

In the semiconductor device of the present invention, electrodes connected to respective junctions of bipolar transistors, N-channel MOS transistors, and P-channel MOS transistors formed on the same semiconductor substrate are formed of at least an upper layer of aluminum and an aluminum diffusion layer provided below. It has a multilayer structure with barrier metals.

Preferably, a lowermost metal layer such as a platinum silicide layer is formed below the aluminum diffusion barrier metal to create a Schottky barrier to the semi-solid substrate and to make ohmic contact with the diffusion layer. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(Example 1) FIGS. 1(a) to 1(e) are cross-sectional views showing a first example of the present invention in the order of manufacturing steps, and the semiconductor device of this example will be explained according to these manufacturing process diagrams.

First, as shown in the same figure (a), high concentration N type buried layers 2 and 3 and high concentration P type buried layer 4 are formed on a P type silicon substrate l.
After that, an N-type epitaxial layer 5a is formed.

5b is grown, and a P well 6 for forming an N-channel MOS transistor is formed so as to be connected to the heavily doped P-type buried layer 4. There are element bones on the surface of this silicon substrate 1! An iI oxide film 7 and a thin oxide film 8 are formed, and this thin oxide film 8 is configured as a gate oxide film in the MO3I transistor region.

In the epitaxial layer 5a of the bipolar transistor region, a P-type base diffusion layer 10. P-type diffusion layer 11 in the base contact portion. An emitter 12 and a collector N-type diffusion layer 13 are formed, and an emitter polycrystalline silicon electrode 14 is formed.
form.

In addition, a gate polycrystalline silicon electrode 15 and a high-density N-type diffusion layer 16 are formed in the P-type well 6 of the N-channel MOS transistor region. Similarly, a gate polycrystalline silicon electrode 17 and a heavily doped P-type diffusion layer 18 are formed in the N-type epitaxial layer 5b of the P-channel MOS transistor region, respectively.

Thereafter, a 1 μm thick PSG film 19 is deposited as an insulating film between the eyebrows by CVD.

Next, as shown in FIG. 3B, the PSG film 19 is selectively etched in a region including both the highly doped P-type base contact portion 11 and the N-type epitaxial layer 5a of the bipolar transistor to open a Schottky contact hole 20. do.

Next, as shown in FIG. 4(c), platinum was deposited to a thickness of 1000 on the entire surface of the substrate by sputtering or the like, and heated at 500°C.

By performing heat treatment in an N2 atmosphere for about 20 minutes, a platinum silicide layer 21 as a lowermost metal layer is formed only in the portion of the Schottky contact 20 where the silicon surface is exposed. This platinum silicide layer 21 functions as a Schottky barrier diode between it and the N-type epitaxial layer 5a, and makes a low-resistance ohmic connection to the heavily doped P-type base contact portion 11.

Next, as shown in FIG. 3(d), the emitter, collector and MO3I-
Contact holes 22 are opened in each part of the transistor.

Then, as shown in FIG. 3(e), 1000 layers of titanium, for example, is formed as a barrier metal 23 on the entire surface by sputtering, aluminum 24 is vapor deposited on this, and the aluminum layer and barrier metal layer are formed by photoetching. Remove unnecessary parts by etching and complete the aluminum electrode wiring.

Therefore, in order to reduce the contact resistance between the metal and the silicon layer, for example, 20
Even if alloying is performed for several minutes, the barrier metal 23 can prevent aluminum from diffusing into the silicon semiconductor, and is in ohmic contact with the high concentration N and P diffusion layers.

Furthermore, for the Schottky barrier diode formed of the platinum silicide layer 21, the barrier metal 23 can also prevent aluminum from diffusing and penetrating through the alloy, thereby stabilizing the collector-to-base clamp voltage VF of the bipolar transistor.

(Example 2) Figures 2 (a) to (d) are cross-sectional views showing the second embodiment of the present invention in the order of manufacturing steps, and in the figures, the same or equivalent parts as in the first embodiment are denoted by the same reference numerals. It is attached.

First, as in the first embodiment, as shown in FIG.
A high concentration N type buried layer 2.3 and a high concentration P type buried layer 4 are formed on a type silicon substrate 1, and then an N type epitaxial layer is formed.
5a and 5b, and a P-type well 6 for forming an N-channel MOS transistor is formed in the heavily doped P-type buried layer 3.
form to connect with. Further, an element isolation oxide film 7 and a thin oxide film 8 are formed on the surface.

Thereafter, the epitaxial layer 5a of the bipolar transistor region is coated with a base layer JU 10 and a high/one P type diffusion layer 11 . Emitter 12. A collector high concentration N-type diffusion layer 13 and an emitter polycrystalline silicon electrode 14 are formed.

Furthermore, a gate polycrystalline silicon electrode 15 and a heavily doped N-type diffusion layer 16 are formed in the P-type well 6 of the N-channel MOS transistor. Furthermore, a gate polycrystalline silicon electrode 17 and a high temperature P type diffusion layer 18 are formed in the epitaxial layer 5b of the P transistor region, respectively. After that, the PSG film 19 is coated with C as an interlayer insulating film.
Deposit 1 μm by VD method.

Next, as shown in FIG. 4B, the PSG film 19 is selectively etched to form a Schottky contact hole 20 in a region including both the high/τ degree P type base contact portion 11 and the N type epitaxial layer 5a. Open a hole. At this time, contact holes 22 for the emitter and collector of the bipolar transistor and each part of the MOS transistor are also opened at the same time.

Next, as shown in the same figure (C), platinum is applied to the entire substrate surface to a thickness of 1,000 yen by sputtering or heat treatment is performed in a CN2 atmosphere at 500°C for about 20 minutes, and the Schottky film with the silicon surface exposed is then heated. A portion of the contact hole 20 and the emitter of the bipolar transistor.

A platinum silicide layer 21 is formed on the collector and the contact hole 22 of the MOS transistor.

This platinum silicide layer 21 is an N-type layer 5.
It acts as a Schottky barrier diode between a and the high? P-type base contact portion i1 and emitter of the bipolar transistor 12. Collector contact part 1
3. Furthermore, contact 16.1 of each part of MOS transistor
8, a low resistance ohmic connection is made.

Then, as shown in Figure (d), a barrier metal 23 of 1,000 layers, for example, titanium, is formed on the entire surface by sputtering or the like, and alumina L24 is applied on top of this, and a photo-etching method is used to eliminate the need for an aluminum layer and a barrier metal bottom layer. The aluminum electrode wiring is completed by etching away the portion.

Thereafter, in order to lower the contact resistance between the barrier metal 23 and the silicide layer 21, the
Alloying is carried out for 0 minutes, but at this time the barrier metal 23 prevents aluminum from diffusing and penetrating into the silicide layer 21.
It is possible to make ohmic contact with the highly doped N-type and P-type diffusion layers formed by ultra-shallow junctions, and to stabilize the clamp voltage (2) of the Schottky barrier diode.

〔Effect of the invention〕

As explained above, in the present invention, the electrodes provided at the junctions of semiconductor devices are made up of two layers: an upper layer made of aluminum and a lower layer made of an aluminum diffusion barrier metal. We aim to miniaturize a Bi-CMO5 semiconductor device in which a bipolar transistor and a MOS transistor formed by a shallow junction coexist on the same substrate.
Improved operating speed and reliability can be achieved.

In addition, since the electrode is composed of three layers: an upper layer made of aluminum, a lower layer made of aluminum diffusion barrier metal, and a bottom layer made of platinum silicide layer, bipolar transistors formed with shallow junctions and A high-speed and highly reliable Bi
- A CMO8 semiconductor device can be realized.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are sectional views showing the first embodiment of the present invention along with its manufacturing process, and FIGS. 2(a) to (d) are sectional views showing the second embodiment of the present invention along with its manufacturing process. FIGS. 3(a) to 3(e) are sectional views showing the conventional structure together with its manufacturing process. 1.31...P-type silicon substrate, 2,3.32.33
... N-type buried layer 1, 4, 34... P-type buried layer, 5a
. 5b, 35a, 35b...N-type evixial layer, 6
．． 36... P-type well, 7, 37... Element isolation oxide film, 8.38... Gate oxide film, 10.40... Base diffusion layer, 11.41... Base contact portion,
12.42... Emitter diffusion N 1. 13.43・
... Collector diffusion layer, 14.44 ... Emitter polycrystalline silicon layer, 15.45 ... Gate electrode, 16.46
...N type source/drain region, 17.47...Gate electrode, 18.48...P type source/drain region, 19.49...Interlayer insulating film, 20...Schottky contact, 21 ...Platinum silicide layer, 22. :+
2... Opening, 23... Barrier metal layer, 24.54.
··aluminum. Agent Patent Attorney Akira Suzuki

Claims (3)

[Claims] (1) Bipolar transistor, N
In a semiconductor device in which a channel MOS transistor and a P-channel MOS transistor are integrally formed, an electrode connected to a junction of each transistor is formed in a multilayer structure including at least an upper layer of aluminum and an aluminum diffusion barrier metal provided below the upper layer. A semiconductor device characterized by: (2) The semiconductor according to claim 1, wherein a lowermost metal layer is formed below the aluminum diffusion barrier metal, causing a Schottky barrier to the semiconductor substrate and making ohmic contact with the diffusion layer. Device. (3) The semiconductor device according to claim 2, wherein the lowest metal layer is a platinum silicide layer.