JPS61194764A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the performance of a bipolar transistor while reducing the size of the element by forming an emitter region by an impurity diffusion from a conductive layer as an emitter electrode shaped to one part on a semiconductor region as a base region while introducing an impurity in high concentration to an external base region section while using the conductive layer as a mask. CONSTITUTION:In a process in which a bipolar transistor and a MISFET are shaped onto the same semiconductor substrate, a gate electrode for the MISFET is formed while an emitter electrode is shaped, and an emitter region is formed through the diffusion of an N-type impurity from the emitter electrode while a P-type impurity is introduced to an external base region at the same time as ion implantation for shaping source-drain regions in the P channel type MISFET as employing the emitter electrode as an ion implanting mask. Accordingly, the emitter region and the external base region can be shaped in a self- alignment manner, thus lowering the resistance of the external base region and improving the performance of the bipolar transistor while reducing the size of an element for the bipolar transistor, then enhancing the degree of integration.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and to the formation of bipolar transistors in semiconductor integrated circuits. The present invention relates to a technique that can be effectively used to form an emitter region in a semiconductor integrated circuit in which a field effect transistor (type field effect transistor) is formed.

[Background technology] The memory array is composed of high-resistance load type memory cells made of MISFETs (see Figure 2), and the peripheral circuits such as the turnout buffer and readout circuit (sense amplifier) are composed of bipolar transistors. An invention related to a static RAM has been proposed. In addition, in order to form such a static RAM, various technologies have been proposed regarding a process (hereinafter referred to as the FB1-CMOS process) for forming a bipolar transistor and a MISFET on the same semiconductor substrate (Japanese Patent Application No. 1983-1989). 143869
issue).

In the B i -CMOS process according to the above-mentioned prior application, after forming the base region, for the external base region,
P-channel MIS FET source.

At the same time as the ion implantation for forming the drain region, P-type impurities are introduced to lower the base resistance. Further, the emitter region is formed by diffusion of N-type impurities from a polysilicon electrode formed at the same time as the polysilicon layer constituting the load resistance in the memory cell.

However, when the above process is followed, the emitter region and the external base region are not self-aligned, so there is a problem that the base resistance cannot be sufficiently reduced and the element size of the bibolar transistor cannot be reduced.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that improves the performance of bipolar transistors, reduces the element size, and enables high integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in the process of forming bipolar transistors and MISFETs on the same semiconductor substrate, MTSF
An emitter electrode is formed simultaneously with the formation of the gate electrode of the ET, and an emitter region is formed by diffusion of N-type impurities from this emitter electrode. Using this emitter electrode as an ion implantation mask, a P-channel type MIS is formed.
By introducing P-type impurities into the external base region at the same time as the ion implantation for forming the source and drain regions of the FET, the emitter region and the external base region can be formed in a self-aligned manner. The present invention achieves the above-mentioned objects of improving the performance of bipolar transistors by lowering the region resistance, and reducing the device dimensions of bipolar transistors to enable high integration.

[Example 1] Figures 1 (A) to (E) show a manufacturing process of an example in which the present invention is applied to a semiconductor integrated circuit in which a bipolar transistor and a MISFET are formed on the same semiconductor substrate. They are shown in order.

First, a semiconductor substrate 1 such as a P-type crystal silicon substrate is prepared, and its surface is oxidized to form a silicon oxide film.
Using this silicon oxide film or the like as a mask, an N type impurity such as antimony is introduced and diffused onto the main surface of the semiconductor substrate 1 by thermal diffusion or the like to form N+ type buried layers 2a and 2b.

Then, by the same method, a P+ type buried layer 3 is formed between the N+ type buried layers 2a and 2b, and after removing the oxide film that served as a mask, the entire surface is deposited on the semiconductor substrate 1 by vapor phase epitaxy. An N-type epitaxial layer 4 is formed as shown in FIG.
).

Next, the surface of the N-type epitaxial layer 4 is oxidized to form a silicon oxide film, and then photoetching is performed, and using this silicon oxide film as a mask, N-type impurities are added to the locations where the bipolar transistor and P-channel MISFET are to be formed. is diffused to form an N-well region 5. Then, in a similar manner, the N-channel MI
A P-well region (not shown) is formed by diffusing P-type impurities in a location where an S FET is to be formed.

Then, after removing the silicon oxide film that served as a well region formation mask, the surface of the substrate 1 is again thinly oxidized to form an oxide film 7a, and then CVD (chemical vapor deposition) is performed.
A silicon nitride film 6 is formed by a deposition method or the like. Thereafter, photoetching is performed so that the silicon nitride film 6 remains only on the regions where elements such as bipolar transistors and MISFETs are to be formed. Then, the bipolar transistor formation region and the MIS
P-type impurity ion implantation for forming a channel stopper layer is performed at the boundary of the FET forming region, for example, at the same time as or in a separate step from ion implantation for forming a P well.

Next, using the silicon nitride film 6 as an oxidation-resistant mask,
A relatively thick field insulating film 7 is formed by selectively thermally oxidizing the surface of the semiconductor substrate 1 in an oxidizing atmosphere. At this time, since silicon nitride film 6 does not allow oxygen to pass through, the main surface of the substrate below silicon nitride film 6 is not oxidized. Also, through this heat treatment, the P-type impurity implanted in advance is diffused, and the bipolar transistor and M I S FE
A P-type semiconductor region 8 is formed as a channel stopper layer directly under the field insulating film 7 at the T boundary, resulting in the state shown in FIG. 1(B).

After the state shown in FIG. 1(B), first, the silicon nitride film 6 serving as an oxidation-resistant mask is removed, and then the silicon oxide film 7a on the main surface of the substrate is removed and then thermal oxidation is performed to remove the exposed parts. A silicon oxide film 11, which will become a gate insulating film, is formed on the main surface of the substrate. Using the photoresist film as a mask, an N-type impurity is implanted and diffused into the portion that will become the collector pull-up port by ion implantation or the like, thereby forming an N-type semiconductor region 9 that reaches the N+ type buried layer 2a. Thereafter, the collector pull-up port (9) and the portion where the MISFET is to be formed are covered with a photoresist film or the like, and P-type impurities are implanted and diffused onto the main surface of the substrate by ion implantation or the like to form a base region. A P-type semiconductor region 10 is formed, resulting in the state shown in FIG. 1(C).

Then, the silicon oxide film 11 on the surface of the portion where the collector pull-up port 9 and the emitter are to be formed is removed by wet etching or the like to form openings 11a and 11b, and then the silicon oxide film 11 is etched using a CVD method. A polysilicon layer is formed over the entire surface. This polysilicon layer is then treated with N such as arsenic or phosphorus.
After introducing type impurities by ion implantation, a thin layer of a high melting point metal such as molybdenum or tungsten is deposited thereon. Then, heat treatment is performed. Then, the upper layer of the polysilicon layer changes to a metal silicide (compound of metal and silicon) layer, and a two-layer film (polycide film) structure 12 consisting of the polysilicon layer and the metal silicide layer thereon is formed. , N-type impurities are diffused from the polysilicon layer onto the main surface of the substrate to form a base region (10).
An N-type semiconductor region 13 serving as an emitter region is formed thereon, resulting in the state shown in FIG. 1(D).

Thereafter, the polycide layer (12) is photoetched to form the gate electrode 12a, emitter electrode 12b, and collector electrode 12c of the MISFET, and then the upper part of the bipolar transistor and the P-channel MISFET is etched. N-type impurity ions are implanted using the gate electrode as a mask while covered with a photoresist film to form an N-channel MIS FET.
Form the source and drain regions.

Next, with the collector pull-up port 9 and the N-channel MIS FET formation region (not shown) covered with a photoresist film 14, a P-type ion implant such as boron is implanted using the gate electrode 12a and emitter electrode 12b as ion implantation masks. Impurities are introduced into the main surface of the semiconductor substrate.

As a result, a P-channel MISFET is formed on the N-well region 5, self-aligned with the gate electrode 12a.
P-type semiconductor regions 15 are formed as source and drain regions, and N-type semiconductor regions 13 are formed as emitter regions.
An external base region lOa, which is self-aligned with the emitter electrode 12b and into which P-type impurities are implanted at a high concentration, is formed in the outer base region of FIG. 1E.

That is, in this embodiment, the emitter region (13) and the external base region 10a are formed in a self-aligned manner. As a result, the distance between the emitter region (13) and the external base region 10a becomes very short, and the resistance value of the external base decreases.
The performance of bipolar transistors is improved. Also,
Since the emitter region (13) and the external base 10a are formed in a self-aligned manner, the base region and thus the element size of the transistor can be reduced, thereby making it possible to achieve high integration.

Furthermore, in the above embodiment, since a part of the emitter electrode 12b and the collector electrode 12c are formed of metal silicide, the contact resistance and the resistance of the lead wiring are lower than when they are made of polysilicon electrodes. The operating speed of the transistor is improved.

Moreover, since the metal silicide layer that becomes the emitter electrode 12b has a low resistance, it can be extended as it is to form a wiring. Therefore, wiring layout design becomes easier.

Then, in the process of Bi-CMO3 type static RAM, etc., a second polysilicon layer is formed on the entire surface using the CVD method, and then patterned to form polysilicon layers for the source and drain of the N-channel MIS FET. In addition to forming electrodes, N-channel MI
A polysilicon layer for forming a resistance element is left above the gate electrode 12a of the S FET with an insulating film interposed therebetween.

Next, with only the upper part of the polysilicon layer forming the resistance element covered with a photoresist film, N-type impurity ions are implanted and annealed to reduce the thickness of the polysilicon layer other than the polysilicon layer forming the resistance element. Become a resistance.

Thereafter, an interlayer insulating film such as a PSG film (phosphorus silicate glass film) is formed over the entire semiconductor substrate, and a contact window is opened in this interlayer insulating film by dry etching. Then, after depositing an aluminum layer on the entire surface, patterning is performed to form the emitter electrode, base electrode, collector electrode and source of the MTSFET.
A completed state is achieved by forming a drain electrode and a wiring layer, and finally forming a final passivation film over the entire surface of the aluminum electrode and wiring layer.

In the above embodiment, a collector electrode made of metal silicide is also formed on the surface of the collector pull-up port (9), but the present invention is not limited thereto.
It is also possible to have a structure in which the aluminum electrode is brought into direct contact, or a collector electrode made of a second polysilicon layer is brought into contact.

By the way, in a Bi-CMO3 type static RAM using a high resistance load type memory cell as shown in FIG. 2, the input/output node n1 (or node n2) of the memory cell
Then, drive M I S F E T Q 1 (or Q
l) and the source and drain regions of transfer MIS FETQ3 (or Q4) and the MIS on the opposite side.
The gate electrode of FET Q2 (or Ql) and one end of load resistor R1 (or R2) are connected to each other. In that case, contact them intensively in one place. In other words, MISFETQ.

(Ql) and Q3 (Q4) have a common source and drain region, which is the diffusion layer, and a polysilicon layer (or polycide layer) which is the gate electrode of MISFET Q2 (Ql) and a polysilicon layer which constitutes the load resistance. By adopting a structure in which one end is extended and brought into contact with each other, it is possible to reduce the area occupied by the memory cell.

FIG. 3 shows an example of the contact structure at the input/output node n1 or R2.

That is, the field insulating film 7 on the main surface of the semiconductor substrate 1
On a part of the surface of the area 20 surrounded by.

With the gate insulating film once formed on its surface removed, one end of the polycide layer 12 serving as the gate electrode of the MI S FET is brought into direct contact. Then, an N-type diffusion region 21 is formed by diffusion of an N-type impurity (phosphorus or arsenic) from this polycide layer 12 (particularly a polysilicon layer). Using the polycide layer 12 as an ion implantation mask, an N-type semiconductor region 22 is simultaneously formed on the surface of the region 20 not covered with the polycide layer at the same time as the source and drain regions of an N-channel MIS FET (not shown) are formed.
form. The N-type regions 21 and 22 formed in this way are connected to the MISFETs Ql and Qa shown in FIG.
(or Ql and 04) so as to be continuous with the source and drain regions.

Then, the above-mentioned region 20 is
The opening 23a is formed slightly larger than the opening 23a. Then, one end of the polysilicon layer 24 for configuring the load resistance R1 (R2) is extended thereon and brought into contact with the surface of the N-type semiconductor region 22 and the surface of the polycide layer 12. As a result, the connection structure at the memory cell input/output nodes n1 and B2 in FIG. 2 can be realized with an extremely small area. Also, contact resistance is low.

Furthermore, the contact structure shown in FIG. 3 can be formed by the same method as the emitter region 13 in the previous embodiment, as can be seen by comparing it with FIG. 1(E).

Therefore, Bi-C using high resistance load type memory cells
In an MOS type static RAM in which a contact structure as shown in FIG. The external base region 10a can be formed in a self-aligned manner.

Alternatively, the structure of the bipolar transistor of the above embodiment and the contact structure of the input/output node (nlln2) that occupies a small area as shown in FIG. 3 can be realized by a common process, and the chip size can be reduced. Become.

Although the above embodiment has been described as being applied to a semiconductor integrated circuit using the B1-CMOS process, the present invention can also be applied to a bipolar integrated circuit consisting only of bipolar transistors, thereby achieving the excellent effects as described above. A bipolar transistor with high performance can be obtained.

[Effect] Bipolar transistor and MI on the same semiconductor substrate
In the process of forming S FET, MISFET
Simultaneously with the formation of the gate electrode, an emitter electrode is formed, and an emitter region is formed by diffusion of N-type impurities from this emitter electrode, and the source and drain regions of a P-channel MISFET are formed using this emitter electrode as an ion implantation mask. Since the P-type impurity is introduced into the external base region at the same time as the ion implantation for the This has the effect that the resistance of the external base region is lowered to improve the performance of the bipolar transistor, and the element size of the bipolar transistor is reduced, making it possible to achieve high integration.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment described above, the emitter electrode is formed of the same metal silicide layer as the gate electrode of the MISFET, but it may be formed of the same polysilicon layer as the gate electrode or a conductive layer different from the gate electrode.

[Field of Application] In the above description, the invention made by the present inventor has been mainly applied to the process of static RAM of B1-CMOS configuration, which is the field of application that formed the background of the invention, but the present invention is not limited thereto. Without, B
It can be used for i-CMOS processes and even bipolar processes in general.

[Brief explanation of drawings]

FIGS. 1(A) to (E) are cross-sectional views showing an embodiment of the present invention applied to the B1-CMo5 process in the order of manufacturing steps. FIG. 2 is a high-resistance load type memory cell in static RAM. FIG. 3 is a sectional view showing an example of the contact structure of the input/output nodes of the memory cell. 1... Semiconductor substrate, 2a, 2b... N+ type buried layer, 3... P medium buried layer, 4... N type epitaxial layer, 5... P well region , 6... silicon nitride film, 7... field insulating film, 8... P
type semiconductor region (channel stopper layer), 9...N
type semiconductor region (collector pull-up port), 10... P-type semiconductor region (base region), 10a... external base region, 11... silicon oxide film (gate insulating film),
lla, llb...opening. ]2...Metal silicide layer, 12a...Gate electrode, 12b...Emitter electrode, 12c...Collector electrode, 13...N-type semiconductor region (emitter region), 14... ...Photoresist coating, 20...
Contact region, 21.22...N+ type semiconductor region, 23
...Interlayer insulating film, 24...polysilicon layer. Figure 1 Figure 1 Figure 1 (E)

Claims (1)

[Claims] 1. A conductive layer that will become an emitter electrode is formed on a part of the semiconductor region that will be the base region of the bipolar transistor formed on the main surface of the semiconductor substrate, and impurities will be diffused from this conductive layer. A method of manufacturing a semiconductor device, characterized in that an emitter region is formed by using the conductive layer as an ion implantation mask, and impurities are introduced at a high concentration into an external base region by using the conductive layer as an ion implantation mask. 2. The conductive layer serving as the emitter electrode is formed at the same time as the conductive layer serving as the gate electrode of an insulated gate field effect transistor formed in another region of the same semiconductor substrate. A method for manufacturing a semiconductor device according to scope 1. 3. The conductive layer constituting the gate electrode and the emitter electrode is formed of a high-melting point metal or its silicide layer, and an electrode is provided on the surface of the collector pull-up port of the bipolar transistor at the same time as these conductive layers. A method of manufacturing a semiconductor device according to claim 2, characterized in that: