JPS61125165A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the complication of a process by a method wherein ions aer implanted to the whole surface, one condution type region is coated with a mask and an impurity is introduced to the region, a previously formed conduc tion type is denied and the conduction type is changed into a reverse conduction type. CONSTITUTION:N<+> buried layers 2a, 2b and P<+> buried layers 3a, 3b are shaped to the surface of a P type sngle crystal silicon substrate 1, and an N type epitaxial layer 4 is formed on the whole surface. A mask is shaped selectively on the surface, and a P type impurity is diffused to form a P well region 5. A thick field insulating film 7, gate electrodes 12a, 12b and an N type diffusion layer 9 are formed, and N type impurity ions are implanted to the whole surface in the quantity of a dose of 1X10<13>/cm<2> and thermally treated. A partial region is coated with a mask, P type impurity ions are implated in the quantity of a dose of approximately 1.5X10<14>/cm<2>, and N<-> is denired, thus forming P<-> type regions 10a, 14a.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and to the formation of transistors in semiconductor integrated circuits. The present invention relates to a technique that is effective for use in the process of semiconductor integrated circuits in which field-effect transistors (field-effect transistors) are formed.

[Background Art] In a MOS integrated circuit in which MISFETs are integrated on a semiconductor substrate, hot carrier injection into the gate insulating film occurs as MISFETs become more highly integrated due to miniaturization. The problem is that characteristics deteriorate over time. This is because as the channel length becomes shorter, the potential gradient between the source and drain becomes steeper, and the carriers flowing from the source to the drain are accelerated and acquire high energy, and some of them reach the silicon substrate and the insulating film on its surface. This is because it crosses the barrier at the interface and enters the insulating film and is captured by the internal trap level.

In order to prevent the hot carrier injection phenomenon into the gate insulating film as described above, for example, as shown in FIG. A sidewall 102 made of material is formed.

Then, before and after forming this sidewall 102, impurities are introduced for forming the source and drain regions to form a lightly doped semiconductor region 103b inside the highly doped source and drain region 103a. The so-called LDD (Lightly Doped Dr.
Ain) structure M I S FET has been proposed (
Published by Nikkei McGraw-Hill, "Nikkei Electronics (Special Issue Micro Devices) J, August 22, 1983 issue, pages 83 and 84, IEEE Trans, Elec.
tron, Derices, VoL, ED-29, PP
, 590-595. April, 1982) L as above
Using technology related to DD structure MISFET, 0M
N-channel type MISFET and P-channel type MISFET in O8 (complementary MO8) integrated circuit,
As a method for forming both into an LDD structure, the present inventor has developed the following process technology. After the formation, a thick field oxide film 106 for isolation is formed on the substrate surface at the boundary between the two.

After forming a silicon oxide film 107 to serve as a gate insulating film on the main surface of the substrate, a conductive layer such as a polysilicon layer is formed entirely on this silicon oxide film 107 by the CVD method, and then photoetching is performed. Do M I S
Gate electrodes 108a and 108b of the FET are formed.

Then, as shown in Figure 3 (B), the P channel MISF
With the upper part of the element region where the ET is formed covered with a mask 110 such as a photoresist film, N-type impurity ions are implanted and diffused using the gate electrode 108b made of a polysilicon layer as a mask. Then, low concentration N- type semiconductor regions 109a are formed on the substrate surface on both sides of gate electrode 108b in a self-aligned manner with respect to gate electrode 108b.

Next, after removing the photoresist film 110, in the same manner as above, P-type impurities are added while covering the upper part of the element region where the N-channel MISFET is to be formed with the photoresist film as shown by the chain line A. It is implanted and diffused by ion implantation or the like. Then, the gate electrode 108
P-type semiconductor regions (112
a) is formed in self-alignment with the gate electrode 108a.

Therefore, after removing the photoresist film (A),
A relatively thick silicon oxide film is formed over the entire main surface of the substrate by the CVD method, and then the silicon oxide film is removed by reactive ion etching or the like. After thinly oxidizing the insulating film 11 called the sidewall, as shown in FIG. 3(C), the upper part of the element region where the P-channel MISFET is formed is covered with a photoresist film 110', and N-type impurity ions are implanted. and spread it.

Then, it is self-aligned with the insulating film 11 constituting the sidewall, and a high concentration N+ type semiconductor region 109b is formed outside the N- type semiconductor region 109a.

After the state shown in FIG. 3(C), the photoresist coating 11O
′, and then the N-channel M I S
P-type impurity ions are implanted while the FET forming region is covered with a photoresist film. Then, a high concentration P+ type semiconductor region is formed outside the P− type semiconductor region 112a by self-alignment with the sidewall (111), and an LD similar to an N-channel MIS FET is formed.
It becomes D structure.

However, in the above process, the source and drain regions of an LDD structure consisting of a low concentration semiconductor region and a high concentration semiconductor region are connected to an N-channel MISFET and a P-channel MISFET using a photoresist film as a mask.
Since each is formed separately from the I S FET,
This has the disadvantage that the process becomes slow and complicated.

Therefore, so-called B1CM, which forms bipolar transistors as well as MISFETs on the same semiconductor substrate,
In the OS process, M I S FE with LDD structure
Utilizing the above process to form T-BiC
It becomes a MOSB1CMOS process.

[Object of the invention] The object of the invention is to improve the B1CMOS process or CM
In the OS process, LDD structure N-channel/L'MISFET can be used without complicating the process too much.
It is an object of the present invention to provide a semiconductor manufacturing technology that can form a P-channel/I/MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, when performing ion implantation to form a low concentration semiconductor region of an MTSFET of one conductivity type, the ion implantation is performed over the entire surface of the MISFET formation region of the other conductivity type without covering it with a mask. MIS of conductivity type
During ion implantation to form a low concentration semiconductor region of an FET, the MiSFET formation region of one conductivity type is covered with a mask to cancel out the previously formed low concentration conductivity type and change it to the opposite conductivity type. By performing such ion implantation, at least one mask can be omitted, and in addition, in the B1CMOS process,
By performing ion implantation to form the source and train regions of the P-channel MISFET at the same time as forming the base region of the bipolar transistor, it is possible to form the LDD structure N-channel MISFET and the P-channel MISFET along with the bipolar transistor in a simple process.
This achieves the above objective of making it possible to form an FET.

[Embodiment] FIGS. 1A to 1I show a static RAM (Random Access RAM) in which the memory array section is a CMOS circuit and the peripheral circuit is a bipolar transistor and a CMOS circuit, taking the present invention as an example. An example of the case where the present invention is applied to the process of (memory) is shown in the order of manufacturing steps.

In this embodiment, a semiconductor substrate 1 such as a P-type crystalline silicon substrate is prepared, its surface is oxidized to form a silicon oxide film, and using this silicon oxide film as a mask, an N-type impurity such as phosphorus is added. The N+ buried layers 2a and 2b are introduced and diffused onto the main surface of the semiconductor substrate 1 by thermal diffusion or the like. Then, by the same method, P+ buried layers 3a and 3b are formed between N+ buried layers 2a and 2b, and after removing the oxide film that served as a mask, the entire surface is formed on the semiconductor substrate 1 by vapor phase epitaxy. Then, an N-type epitaxial layer 4 is formed to obtain the state shown in FIG. 1(A).

Next, the surface of the N-type epitaxial layer 4 is oxidized to form a silicon oxide film, and then photoetching is performed, and using this silicon oxide film as a mask, an N-channel M
A P well region 5 is formed by diffusing P type impurities in a location where an I S FET is to be formed, reaching the P buried layer 3b. In addition, the bipolar transistor formation region and the MI
P-type impurity ion implantation for forming a channel stopper layer is performed at the boundary of the SFET forming region, for example, at the same time as or in a separate step from ion implantation for forming a P well. Then, after removing the silicon oxide film that served as a mask, the surface of the substrate 1 is again thinly oxidized to form an oxide film 7a, and then a silicon nitride film 6 is formed using a CVD method (chemical vapor deposition method) or the like. Form.

Thereafter, photoetching is performed so that the silicon nitride film 6 remains only on regions where elements such as bipolar transistors and MISFETs are to be formed.

Using the silicon nitride film 6 as an oxidation-resistant mask, the surface of the semiconductor substrate 1 is selectively thermally oxidized in an oxidizing atmosphere to form a relatively thick field insulating film 7. At this time,
Since the silicon nitride film 6 does not allow oxygen to pass through, the main surface of the substrate under the silicon nitride film 6 is not oxidized. Also, by this heat treatment, the P-type impurity implanted in advance is diffused, forming a boundary between the bipolar transistor and the MISFET. Directly below the field insulating film 7, a P type semiconductor region 8 is formed as a channel stopper layer reaching the P+ buried layer 3a, resulting in the state shown in FIG. 1CB).

After the state shown in FIG. 1(B), the silicon nitride film 6 serving as an oxidation-resistant mask on the main surface of the substrate and the silicon oxide film 7a therebelow are removed and then thermal oxidation is performed to remove the exposed substrate. A silicon oxide film 11 serving as a gate insulating film is formed on the main surface. Then, a conductive layer such as a polysilicon layer is formed entirely on this silicon oxide film 11 by the CVD method,
Furthermore, after forming a coexisting layer of molybdenum and silicon on top of that, photoetching is performed to create a double-structured MIS.
FET gate electrodes 12a and 12b are formed.

Thereafter, using a photoresist film or the like as a mask, an N-type impurity such as phosphorus is implanted into the portion that will become the collector pull-up port by ion implantation or the like, and then heat treatment is performed. Through this heat treatment, the gate electrodes 12a, 12. The upper layer of b, in which molybdenum and silicon coexist, is completely silicided.

The ion-implanted impurity is diffused into the portion that will become the collector pull-up port to form an N-type diffusion layer 9 that reaches the N+ buried layer 2a, resulting in the state shown in FIG. 1 (CC).

Then, using the gate electrodes 12a and 12b as a mask, ions of an N-type impurity such as phosphorus, such as LXIO13/cnf, are implanted into the entire surface through the silicon oxide film 11 serving as a gate insulating film, and heat treatment is performed. Then, 1.N-channel M which is originally desired to be an N-type region
The surface of the P-well region 5 where the source and drain regions of the ISFET are to be formed, and the surfaces of the N-type epitaxial layers 4a and 4b as the N-well region where the base of the bipolar transistor and the source and drain of the P-channel MISFET are to be formed. , the concentration is I×101'/c
N-type semiconductor regions 15a, 15b, 1 with a low concentration of about 4
5c is formed in a self-aligned manner with respect to the gate electrodes 12a and 12b, resulting in the state shown in FIG. 1(D).

After the state shown in FIG. 1(D), as shown in FIG. 1(E), the device region where the N-channel MISFET is formed and above the collector pull-up port (9) are covered with a photoresist film 13.
While covered with a mask, ions of a P-type impurity such as boron are implanted at a dose of about 1.5×1014/cJ to form the base region of a bipolar transistor, and then heat treatment is performed to diffuse it. let Then, the ion implantation for forming the base region is performed using the N
Therefore, the conductivity type (N- type) of the N- type semiconductor regions 15c and 15a that were already formed in the base region and the source and drain regions of the N-channel MISFET is changed.
is canceled out by the P-type impurity and changed to the opposite conductivity type, forming P- type semiconductor regions 10a and 14a.

Then, after removing the photoresist film 13, a relatively thick silicon oxide film is formed over the entire main surface of the substrate by CVD, and then the silicon oxide film is removed by reactive ion etching or the like. Then, since the reactive ion etching proceeds in parallel from above, the relatively thick portions, that is, the gate electrodes 12a and 12b
Insulating films 17 called sidewalls remain on both sides of the substrate. Therefore, in this state, after thinly oxidizing the surfaces of the N-type and P-type semiconductor regions, the base forming region (1
The periphery of 0a) and the upper part of the element region where the P-channel MISFE'T is formed are covered with a photoresist film 18, and ions of an N-type impurity such as arsenic are implanted at a dose of, for example, 5X101 s/d. Spread it.

Then, it is self-aligned with the insulating film 17 constituting the sidewall, and as shown in FIG. X 102' /c+
A medium-sized N semiconductor region T9 with a high concentration of approximately j is formed.

After the state shown in FIG. 1(F), the bipolar element region and the N-channel MISFET formation region are covered with a photoresist film 18' as shown in FIG. 1(G).
For example, P-type impurity ions are implanted at a dose of about 3XIO15/crI. Then, the side wall (
17) and is self-aligned with the P-type semiconductor region 14a.
A high concentration P+ type semiconductor region 14b is located outside of the P- type semiconductor region 10a which is an intrinsic base region (li!).
! Highly doped external base region 10b is formed [on the right side]. , □ Next, after forming a silicon oxide film 20 over the entire surface of the semiconductor substrate by, for example, a CVD method under high temperature and low pressure, this silicon oxide film 2o is selectively etched to form an intrinsic base region (10a). Upper and N channel M r
Contact window 2 on the source and drain regions of S FET
1a and 21b are formed. Thereafter, a second polysilicon layer is formed on the entire surface using the CVD method, and then patterned to form the emitter polysilicon electrode 22a.
And polysilicon electrodes 22b for the source and drain of the N-channel MISFET are formed, and a polysilicon layer 22c for forming a resistance element is left above the gate electrode 12b of the N-channel MISFET via the silicon oxide film 20. .

Then, a polysilicon layer 2 for forming a resistance element is formed.
With only the upper part of 2c covered with a photoresist film,
After ion implantation of type impurities and annealing, the polysilicon layer (
22a, 22b) to have lower resistance. At this time, an N+ type semiconductor region 23, which is a relatively shallow emitter region, is formed on the intrinsic base region (10a) by impurity diffusion from the polysilicon electrode 22a, resulting in the state shown in FIG. 1(H).

After the state shown in FIG.
4 is formed, contact windows 25a to 25a are opened in this interlayer insulation film 24 by dry etching. Then, after depositing an aluminum layer on the entire surface,
After patterning, the emitter electrode 26a, the base electrode 26b, the collector electrode 26c and the M I S FE
Forming source and drain electrodes 25d and 25e of T,
The state shown in FIG. 1(I) is reached.

Thereafter, a final passivation film is entirely formed on the aluminum electrodes (25a to 25e) to complete the structure.

In the above embodiment, an LDD structure N-channel MI
The N-type semiconductor region L5b for obtaining the SFET is formed without a mask. Sonotame, N-type semiconductor region (1
5b, 109a) and P- of the P-channel MISFET.
Compared to the method shown in FIG. 3 in which the type semiconductor regions (14a, 112a) are formed using separate photoresist masks, one less mask is required, and the photoresist mask forming process can be simplified. Can be omitted.

In addition, in the above embodiment, P channel M of LDD manufacturing
The formation of the P-type semiconductor region 14a for obtaining an I S FET is performed by the P-type semiconductor region 14a for forming the base of a bipolar transistor.
This is done in the same process as the introduction of the type impurity, and the P- type semiconductor region 14a is formed by compensating the N- type of the pre-formed low concentration N- type semiconductor region 15a with the high concentration P type impurity introduced later. is forming.

Therefore, the base region 10a of the bipolar transistor
Since it is not necessary to separately form the P-type semiconductor region 14a of the P-channel MIS FET and the B1CMOS
In the process, without complicating the process,
A MI S FET having an LDD structure can be obtained.

This allows bipolar transistors and MISFETs to
In semiconductor integrated circuits such as static RAMs, it is possible to achieve high integration and high functionality by miniaturizing MrSFETs.

Moreover, P+ of P-channel MISFET with LDD structure
When the type semiconductor region 14b is formed, P-type impurity ions are implanted into the external base region 1°b of the bipolar transistor at the same time, so the resistance value of the external base region can be effectively increased without increasing the number of steps. can be reduced to improve the performance of bipolar transistors.

In the above embodiments, the description has been given of the application to the B i CM OS process, but even in the CMOS process, the formation of the P-type semiconductor region of the P-channel MISFET is performed in advance by forming the N-type semiconductor region of the N-channel MISFET.
The number of masks can be reduced by forming - type semiconductor regions without a mask and then implanting P-type impurity ions to cancel out the N- type in the source and drain regions of the P-channel MIS FET formed thereby. can be reduced.

Further, in the above embodiment, the emitter region (23) is formed by impurity diffusion from the polysilicon layer 22a, but the present invention is not limited thereto.

For example, it can be formed by direct diffusion or ion implantation on the main surface of a semiconductor substrate, or it can be formed by
The formation of the N+ type semiconductor region 19, which is the source and drain region of the SFET, is
It is also possible to form the emitter region at the same time as the source and drain regions (19) of the N-channel MI S FET by bringing it to a later step than the formation of the type semiconductor region 14b.

Furthermore, in the above embodiment, the P-channel MISFET also has sidewalls (1
7) to form an LDD structure in which the source and drain regions are composed of a P+ type semiconductor region 14b and a P− type semiconductor region 14a. However, P channel MI
SFETs are relatively unlikely to suffer characteristic deterioration due to hot carrier injection into the gate oxide film, so P-channel MTS FETs can have a general MI S FET structure instead of an LDD structure. .

[Effect (1) During ion implantation to form a low concentration semiconductor region of MISFET of one conductivity type, M of the other conductivity type is
Ion implantation is performed on the entire surface of the I S FET formation region without covering it with a mask, and the M I S FET of the other conductivity type is implanted.
During ion implantation to form a low concentration semiconductor region of an FET, the MISFET formation region of one conductivity type is covered with a mask to cancel out the previously formed low concentration conductivity type and change it to the opposite conductivity type. Since such ion implantation is performed, there is an effect that at least one mask can be omitted when forming a MISFET having an LDD structure.

(2) When performing ion implantation to form a low concentration semiconductor region of a MISFET of one conductivity type, M
Ion implantation is performed on the entire surface of the I S FET formation region without covering it with a mask, and the M I S FET of the other conductivity type is implanted.
During ion implantation to form the low concentration semiconductor region of the FET, the Ml5FET formation region of one conductivity type is covered with a mask to cancel out the previously formed low concentration conductivity type and change it to the opposite conductivity type. In addition to performing ion implantation to form the source and drain regions of the P-channel MISFET, the ion implantation was performed at the same time as the base region of the bipolar transistor.
DD structure N-channel MISFET and P-channel M
This has the effect of making it possible to form an IS FET.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment,
Embedded layers 2a, 2b and 3a, 3b are formed on a semiconductor substrate, an N-type epitaxial layer 4 is formed thereon, a P-well region 5 is formed therein, and then an N-type epitaxial layer 4 is formed on the P-well region 5. Also epitaxy the channel MISFET.

A base region of a bipolar transistor and a P channel MISFET are formed on the N well regions 4a and 4b consisting of a
However, a CMO5 or CMO5 in which a P-well region or a P-well region and an N-well region are directly formed on the main surface of the substrate without forming the epitaxial layer 4, and each element is formed on the P-well region or the P-well region and the N-well region. It can also be applied to B1CMOS process.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the process of static RAM with BiCMO5 configuration, which is the field of application that formed the background of the invention, but the present invention is not limited thereto. B1CMO
S process or CMOS process can generally be used.

[Brief explanation of the drawing]

FIGS. 1(A) to (I) are cross-sectional views showing an example of the case where the present invention is applied to a B1CMOS process in the order of steps; FIG. 2 is a cross-sectional view showing an example of a MISFET with a conventional LDD structure; - FIGS. 3(A) to 3(C) are cross-sectional views showing an example of a procedure for forming a MISFET with an LDD structure in a CMOS process. 1...Semiconductor substrate, 2a, 2b...N+ buried layer 3a, 3b...P+ buried layer, 4...N type epitaxial layer, 5...P well region, 6...Silicon nitride film, 7°°°゛field insulating film, 8...
P-type semiconductor region (channel stopper layer), 9...
N-type semiconductor region (collector pull-up port), 10a...
P-type semiconductor region (base region), 10b... external base region, 11... silicon oxide film (gate insulating film), 12a, 12b... gate electrode, 13, 18.
18'...Photoresist coating, 14a...P
− type semiconductor region, 14b...P medium type semiconductor region, 1
5 a, 15 b, 15C...N-type semiconductor region, 17... Insulation 11% (side wall),
19...N+ type semiconductor region, 20...Silicon oxide film, 2La, 21b, 25a-25e...Contact window, 22a...Polysilicon electrode for emitter, 22b...Source . Polysilicon electrode for drain, 24... interlayer insulating film (PSG film), 26a to 26e... aluminum electrode. Figure 2 f Figure 3 (A) Figure 3 (C)

Claims (1)

[Claims] 1. Complementary insulated gate field effect transistors are formed on the same semiconductor substrate, and a source of at least an N-channel insulated gate field effect transistor;
In the semiconductor device process, the drain region has a double structure in which a lightly doped semiconductor region is formed inside a highly doped semiconductor region. When introducing impurities to form a semiconductor region, the impurity is completely introduced without covering the insulated gate field effect transistor formation region of the other conductivity type with a mask, and the insulated gate field effect transistor of the other conductivity type is doped. When introducing impurities to form a low concentration semiconductor region of a transistor, the insulated gate field effect transistor formation region of one conductivity type is covered with a mask to cancel out the conductivity type of the previously formed low concentration semiconductor region. By introducing impurities that change the conductivity type to the opposite,
A method of manufacturing a semiconductor device, characterized in that source and drain regions having a double structure are formed. 2. In a process in which a bipolar transistor as well as a complementary insulated gate field effect transistor is formed on the same semiconductor substrate, for forming a low concentration semiconductor region of an N-channel type insulated gate field effect transistor. Impurity introduction is carried out without a mask, and P
The low concentration semiconductor region of the channel type insulated gate field effect transistor is formed by introducing P type impurities into the base region of the bipolar transistor while covering the N channel type insulated gate field effect transistor formation region with a mask. The pre-formed low concentration of N-type is canceled out and P
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by changing a mold. 3. The high concentration semiconductor region of the double structure P-channel insulated gate field effect transistor is formed by introducing impurities at the same time as introducing P-type impurities into the external base region of the bipolar transistor. A method for manufacturing a semiconductor device according to claim 2, characterized in that: