JP2578417B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a joint gate complementary MOS field-effect transistor including a lower N-channel transistor and an upper P-channel transistor, the P ⁺ -type polycrystalline silicon layer constituting the upper P-channel transistor has A P ^- type channel region is formed by doping only the upper portion of the gate with a donor impurity.

[Industrial applications]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a joint gate complementary MOS field effect transistor.

[Conventional technology]

N-channel MOS field-effect transistor (hereinafter referred to as _n MO
SFET referred to as) and the P-channel MOS field effect transistor _(p MOSFET) and more joint gate complementary field effect transistors are common ones to gates of the FET has a (CMOSFET) is as follows 2
Species types are known.

One of them is a joint gate CMOSFET in which channel regions are formed on both sides on the gate electrode side as shown in FIG. 3c. In this case, as shown in FIG. 3a, a gate oxide film 2 is formed on a P-type silicon substrate (wafer) 1.
Then, an N ⁺ polycrystalline silicon gate electrode 3 is formed, and an N ⁺ source region 4 and an N ⁺ drain region 5 are formed by self-alignment by ion implantation of As ⁺ ions using the gate electrode 3 as a mask. SiO ₂ insulating layer 6 by oxidizing the surface of the gate electrode 3 and the silicon substrate 1 by thermal oxidation treatment
Is formed on the entire surface (FIG. 3b). A polycrystalline silicon layer 7 is formed on the SiO ₂ layer 6, and an SiO ₂ layer 8A is further formed thereon. Next, reactive ion etching (RIE)
Etch the SiO ₂ layer 8A by directional (anisotropic) etching until the polycrystalline silicon layer 7 is exposed.
3c). During this etching, the SiO ₂ layer portion 8B corresponding to the side wall of the gate electrode 3 remains without being etched. Then, B ⁺ ions or BF ⁺ ions are implanted into the polycrystalline silicon layer 7 by an ion implantation method, and P ⁺ regions 7A, 7B and 7C are formed in portions not covered with the SiO ₂ layer portion 8B (FIG. 3c).
Is formed. The SiO ₂ layer portion 8B functions as a mask, and the polycrystalline silicon layer 7 into which the acceptor impurity has not been implanted.
Injection region 7D and 7E is the channel region of the _p MOSFET, and the P ⁺ region 7A, 7B, 7C serves as the source or drain region of. The lower _n- MOSFET and upper _p- MOSF thus formed
That is, the CMOSFET composed of ET has a common gate electrode.

Another type is a joint gate CM in which a channel region is formed above a gate electrode and source and drain regions are formed on both sides of the gate electrode as shown in FIG. 2c.
OSFET. In this case, FIG. 2a is the same as FIG. 3a, and a gate oxide film 2 is formed on a P-type silicon substrate (wafer) 1.
And N ⁺ polycrystalline silicon gate electrode 3 are formed, and N ⁺ source region 4 and N ⁺ drain region 5 are formed by ion implantation of As ⁺ ions. As shown in FIG. 3b, the surfaces of the gate electrode 3 and the silicon substrate 1 are thermally oxidized to form the SiO ₂ insulating layer 6. A polycrystalline silicon layer 21 is formed on this SiO ₂ layer 6, and a boron glass (BSG) layer 22A is further formed thereon. Next, the boron glass layer 22A is etched by directional (anisotropic) etching to leave a boron glass layer portion 22B at a position corresponding to the side wall of the gate electrode 3, as shown in FIG. 2c. The crystalline silicon layer 21 is exposed. Then, by heating (annealing), B (boron) contained in the boron glass layer portion 22B is introduced into the polycrystalline silicon layer 21 which is in contact by thermal diffusion, and the P ⁺ regions (source and drain regions) are formed. ) 21A and 21B
To form Thus, portions of the polycrystalline silicon layer 21 with boron glass layer is not on B are non-doped region 21C, 21D and 21E undoped, undoped region 21D is the channel region of the _p MOSFET gate electrode 3 upper of this Becomes CMOSFET having such a lower _n MOSFET and an upper _p MOSFET in the is formed as having a common gate electrode.

[Problems to be solved by the invention]

In the joint gate CMOSFET described above, the upper _p
When forming a MOSFET, B is doped (introduced) into the polycrystalline silicon layer by ion implantation or solid phase thermal diffusion.
Doped B has a large diffusion coefficient (velocity) compared with As (fast), especially in polycrystalline silicon (fast).
For this reason, the P ⁺ region is likely to expand during annealing or thermal diffusion heat treatment after ion implantation. Therefore, in forming a fine _p MOSFET to achieve high integration of the CMOSFET, becomes effective channel length is shorter than a predetermined length, the breakdown voltage decreases and the short channel effect due to punch-through becomes significant. Thus, a problem occurs in the formation of the P channel.

An object of the present invention, _p MOSFET joint gate CMOSFET
To provide a method for forming a P channel at a predetermined length with good reproducibility.

Another object of the present invention is to provide a manufacturing method capable of achieving high integration of a joint gate CMOSFET.

[Means for solving the problem]

The above-mentioned problem is caused by a lower N-channel transistor in which an N-type source region and a drain region are formed in a semiconductor substrate and a polycrystalline silicon gate electrode is formed on a gate oxide film, and using the polycrystalline silicon gate electrode as a gate. In a method of manufacturing a joint gate complementary MOS field effect transistor comprising a semiconductor substrate and an upper P-channel transistor formed on an electrode of the gate, an oxide formed on the semiconductor substrate from above the polycrystalline silicon gate. Forming a P + -type polycrystalline silicon layer so as to extend over the film; and forming an insulating layer on the P + -type polycrystalline silicon layer so as to cover the P + -type polycrystalline silicon layer. From above the polysilicon gate to around the polysilicon gate A step of said insulating layer etched away, followed by terminating the the etching at the time when the P + -type polycrystalline silicon layer is exposed,
Selectively exposing the P + -type polycrystalline silicon layer above the polycrystalline silicon gate without using a patterning mask; and an extent that the exposed P + -type polycrystalline silicon layer does not lose the P impurity type. N-type impurities are added to
Forming a P-channel region.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1a to 1e show a joint gate according to the invention.
FIG. 4 is a schematic cross-sectional view of a joint gate CMOSFET in a step according to a method for manufacturing a CMOSFET.

As shown in FIG. 1a, a P-type silicon substrate (wafer) 31
Gate oxide 32 on top and N ⁺ polysilicon gate electrode
33 is formed by a usual process. Using the gate electrode 33 as a mask, P ⁺ ions are ion-implanted to form N ⁻ -type regions (for example, 1 × 10 ¹³ cm ⁻² ) 34 and 35 having a low impurity concentration.

Next, an SiO ₂ layer is formed on the entire surface by chemical vapor deposition (CVD), and is subjected to directional etching such as RIE to leave an SiO ₂ layer portion 36 on the side wall surface of the gate electrode 33 (FIG. 1b). ). A to form the source and drain of the lower _n MOSFET
By performing ion implantation of s ⁺ ions, N ⁺
Regions (eg, 1 × 10 ¹⁵ cm ⁻² ) 37 and 38 are formed.
In this way, a source region of the N ⁻ region 34 and the N ⁺ region 37 and a drain region of the N ⁻ region 35 and the N ⁺ region 38 are formed.
This is a light dose drain structure (double drain structure)
This is effective for suppressing hot carriers. The source and the drain shown in FIG. 2a may be used instead of the source and the drain.

As shown in FIG. 1c, the gate electrode is
33 and silicon substrate 31 are oxidized to form SiO ₂ layers 39A and 39B
Are formed, and these are integrated with the remaining SiO ₂ layer portion 36 to form an insulating layer. A polycrystalline silicon layer on top of this insulating layer
Form 41. Then, after the polycrystalline silicon layer 41 is thermally oxidized to form the SiO ₂ film 42, B ⁺ ions or BF ⁺ ions are implanted into the polycrystalline silicon layer 41 by ion implantation to form a P ⁺ type (for example, 1 × 10 ¹⁵ cm ^-2 ). This SiO ₂ film 42 contributes to stabilization of characteristics by shortening the ion range in silicon, but need not be formed.

Next, as shown in 1d diagram form a SiO ₂ film 43 by a CVD method on the entire surface of the SiO ₂ film 42. In FIG. 1d, although the SiO ₂ film 42 and the SiO ₂ film 43 are formed by the same material, although they are formed by different methods, they are integrally shown by reference numeral “43”. If the growth temperature in this CVD method is high (800 ° C), B ⁺
This also serves as annealing after ion implantation. On the other hand, if the growth temperature is as low as 420 ° C., annealing after B ⁺ ion implantation is performed after formation of the SiO ₂ layer 43. Then, a resist layer 44 is formed on the entire surface of the SiO ₂ layer 43.

The resist layer 44 and the SiO ₂ layer 43 etching rate of the resist layer 44 and the etching rate of the SiO ₂ layer 43 with substantially similar etchant, without using a patterned mask, as shown in 1e Figure multilingual The etching is performed until the crystalline silicon layer 41 is exposed. When the resist is removed, the portion of the polysilicon layer above the gate electrode 33 is exposed, and the other portion of the polysilicon layer is covered with the SiO ₂ layer 43.
Then, donor impurity As ⁺ ions are implanted into the exposed crystalline silicon layer by ion implantation, and the implantation amount is reduced.
Without the polycrystalline silicon, which is a P ⁺ -type N-type P ^- degree ^{(e.g., 1 × 10 12 ~10 13 cm} -2) to the mold is performed to control to. Therefore, the P ⁻ type portion 45 into which As is implanted is P ⁻ polycrystalline silicon and becomes a channel region, and the polycrystalline silicon layer 41 covered with the SiO ₂ layer 43 and not implanted with As is P ⁺ type, and the source and drain Area. Annealing after As ion implantation is performed. In this way, CMOSFET consisting of lower _n MOSFET and an upper _p MOSFET is obtained in the joint-gate.

〔The invention's effect〕

The channel region of the _p MOSFET in the present invention are P and donor impurity (As ions) implantation in B-doped P ⁺ polysilicon ^- since it is formed by a mold, there is no problem that attributed to the diffusion of B. The length of the P channel is defined by a photomask at the time of forming the polycrystalline silicon gate electrode by the self-alignment method, and a large channel length of a predetermined length can be obtained with high reproducibility since there is no large diffusion of the implanted As ions. This
contributes to miniaturization of the _p MOSFET, effectively attained higher integration of CMOSFET.

[Brief description of the drawings]

FIGS. 1a to 1e are schematic cross-sectional views illustrating a manufacturing process of a joint gate CMOSFET according to a method of manufacturing a field effect transistor according to the present invention. FIGS. 2a to 2c are conventional joint gate CMOSFETs. 3a to 3c are schematic cross-sectional views illustrating the manufacturing process of another conventional joint gate CMOSFET.
It is a schematic sectional drawing explaining the manufacturing process of. 31 ...... silicon substrate, 33 ...... polysilicon gate electrode, 36,39A, 39B ...... SiO ₂ layer, 41 ...... polycrystalline silicon layer, 43 ...... SiO ₂ layer, 45 ...... P ^- -type portion.

Claims (1)

(57) [Claims] 1. A lower N-channel transistor in which an N-type source region and a drain region are formed on a semiconductor substrate and a polycrystalline silicon gate electrode is formed on a gate oxide film, and the polycrystalline silicon gate electrode is used as a gate. A method of manufacturing a joint gate complementary MOS field-effect transistor comprising the semiconductor substrate and an upper P-channel transistor formed on the gate electrode, comprising: forming a polycrystalline silicon gate on the semiconductor substrate; Forming a P + type polycrystalline silicon layer so as to extend over the oxide film; forming an insulating layer on the P + type polycrystalline silicon layer so as to cover the P + type polycrystalline silicon layer; At least from above the polysilicon gate to around the polysilicon gate; And removing the insulating layer by etching. Then, when the P + type polycrystalline silicon layer is exposed, the etching is terminated, so that the P + type polycrystalline silicon layer can be removed without using a patterning mask. Selectively exposing above the polycrystalline silicon gate; and adding an n-type impurity to the exposed p + type polycrystalline silicon layer so as not to lose the p-type impurity to form a p-channel region. A method for manufacturing a field-effect transistor, comprising: