JPH0637106A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an MOS transistor having an LDD structure without using any oxide film depositing and etching back methods by forming an oxide film on the upper surface and side face of a gate electrode by thermal oxidation. CONSTITUTION:Low-concentration diffusion layers 4 are formed by implanting P ions at an angle of 45 deg.. A thermally oxidized film 5 is formed by oxidizing the upper surface and side face of a polycrystalline silicon gate electrode 3 in a pyro-atmosphere of 900 deg.C. After source-drain layers 6 are formed by implanting As ions under a condition of 6.0E15cm<-2> in dose and 40KeV in acceleration energy by using the gate electrode 3 and film 5 as masks, heat treatment is performed for 30 minutes in a 850 deg.C nitrogen atmosphere. Therefore, a transistor having an LDD structure can be formed without forming side walls by an etching back method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Gate length 0.8-
The biggest problem in the development of a 1.0 μm MOS transistor is the deterioration of transistor characteristics due to hot carriers. The hot carrier deterioration occurs when carriers accelerated by an electric field in the channel length direction of the transistor generate high-energy electrons or holes that exceed the barrier of the silicon / oxide film interface by impact ionization. Therefore, suppressing the generation of hot carriers is the best solution to this problem. Therefore, a proposal was made for a lightly doped diffusion layer (LDD) between the source / drain diffusion layer and the gate edge.
in) transistor. In the transistor of the LDD structure, the electric field in the lateral direction is relaxed by the low-concentration diffusion layer, which is excellent in hot carrier deterioration. further,
By increasing the implantation angle during low concentration implantation, a transistor (LATID:
Large Angle Tilt Implanted Drain) has also been proposed. The carriers injected into the gate oxide film deplete the low concentration diffusion layer and increase the parasitic resistance of the transistor. However, since the LATID transistor is controlled by the gate electrode on the low-concentration diffusion layer, it is not easily affected by hot carriers.

FIG. 7 is a cross sectional view showing a conventional LDD structure N-channel MOS transistor.

In FIG. 7 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose amount of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing the polycrystalline silicon film, the photoresist is used as a mask to perform patterning by dry etching to form a polycrystalline silicon gate 3. Next, P ions are implanted at an angle of 45 ° under the conditions of a dose amount of 4.0E13 cm- ² and an acceleration energy of 40 KeV to form a low concentration diffusion layer 4.

In FIG. 7B, a 150 nm oxide film 8 is deposited on the semiconductor device by a known vapor phase growth method.

In FIG. 7 (c), the oxide film 8 on the semiconductor device and the gate oxide film 2 on the source and drain diffusion layers are etched by using the etch back method to form the sidewall 9.
Then, using the polycrystalline silicon gate 3 and the side wall 9 as a mask, As ions are implanted under the conditions of a dose amount of 6.0E15 cm-2 and an acceleration energy of 40 KeV to form a source / drain diffusion layer 6, and then a nitrogen atmosphere at 850 ° C. Complete heat treatment for 30 minutes.

The N-channel MO configured as described above
In the S-type transistor, since a low-concentration diffusion layer exists between the source / drain diffusion layer and the gate, the electric field in the lateral direction is relaxed, and the reliability of hot carriers is improved.

[0008]

However, in the above structure, two steps of oxide film deposition and oxide film etchback must be added to form the side wall, which increases the number of steps. In addition, over-etching must be performed to prevent the etching residue of the oxide film. For this reason, since the silicon on the source / drain diffusion layer is also etched, the junction surface of the source / drain diffusion layer becomes deep, and there is a risk that the short channel effect is deteriorated.

In view of the above problems, the present invention is directed to oxide film deposition,
Provided is a method for manufacturing a semiconductor device, which can form a MOS transistor having an LDD structure without using an etchback method.

[0010]

In order to solve the above problems, a method of manufacturing a semiconductor device according to a first aspect of the present invention comprises a step of forming a gate electrode on a semiconductor substrate via an oxide film,
Impurities are implanted using the gate electrode as a mask to form a low-concentration diffusion layer, a step of forming an oxide film on the upper surface and side surfaces of the gate electrode by thermal oxidation, the gate electrode and the thermal oxide film Impurities are implanted using as a mask,
And a step of forming a source / drain diffusion layer.

According to a second aspect of the present invention, in the method of manufacturing the semiconductor device according to the first aspect, the gate electrode is formed on the semiconductor substrate via the oxide film, and then the impurity is implanted using the gate electrode as a mask. A low concentration diffusion layer is formed.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, after the thermal oxide film is removed, impurities are implanted using the gate electrode as a mask to form a low concentration diffusion layer. Is characterized by.

A method of manufacturing a semiconductor device according to claim 4 is
A step of forming a gate electrode on a semiconductor substrate through an oxide film, and implanting impurities using the gate electrode as a mask,
Forming a source / drain diffusion layer; forming an oxide film on the upper and side surfaces of the gate electrode by using thermal oxidation; and removing the thermal oxide film, and then implanting impurities with the gate electrode as a mask And a step of forming a low-concentration diffusion layer.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first or fourth aspect, wherein the gate electrode comprises two layers of a first-layer conductive film and a second-layer insulating film. To do.

[0015]

According to the present invention, the LDD structure transistor can be formed without using oxide film deposition and oxide film etching.

Further, according to the third and fourth aspects, the size of the gate electrode which serves as a mask at the time of implanting the low-concentration diffusion layer is smaller than the size of the photomask by the amount of oxidation on the side surface. It is possible to form short transistors.

According to the fifth aspect of the invention, since the upper surface of the gate electrode is covered with the insulating film, the gate electrode can be prevented from being thinned by thermal oxidation, and the thickness of the gate electrode before oxidation can be reduced to the necessary minimum. Since the thickness can be reduced, the steps can be eliminated as much as possible.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing an N-channel MOS type transistor according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the manufacture of an N-channel MOS transistor according to the first embodiment of the present invention.

In FIG. 1 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing the polycrystalline silicon film, the photoresist is used as a mask to perform patterning by dry etching to form a polycrystalline silicon gate 3. Next, P ions are implanted at an angle of 45 ° under the conditions of a dose amount of 4.0E13 cm- ² and an acceleration energy of 40 KeV to form a low concentration diffusion layer 4.

In FIG. 1B, thermal oxidation is performed in a pyro atmosphere at 900 ° C. to oxidize the upper surface and side surfaces of the polycrystalline silicon gate electrode to form a thermal oxide film 5.

In FIG. 1C, the polycrystalline silicon gate 3,
With the thermal oxide film 5 as a mask, the dose amount is 6.0E15cm-2,
After As ions are implanted under the condition of acceleration energy of 40 KeV to form the source / drain diffusion layer 6, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

The N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . Further, since the side wall of the gate electrode is oxidized, the overlap between the low concentration diffusion layer and the gate electrode is small, and the capacitance between the gate and the drain can be reduced.

(Embodiment 2) FIG. 2 is a sectional view showing the manufacturing of an N-channel MOS transistor according to a second embodiment of the present invention.

In FIG. 2 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose amount of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing the polycrystalline silicon film, the photoresist is used as a mask to perform patterning by dry etching to form a polycrystalline silicon gate 3. Next, 900 ℃
The thermal oxidation is performed in the pyro atmosphere to oxidize the upper surface and the side surface of the polycrystalline silicon electrode to form the thermal oxide film 5. Next, dose 6.0E15cm- ^2, implanting As ions with an acceleration energy 40 KeV, to form a source, a drain diffusion layer 6. Next, heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes to activate the impurities in the source and drain diffusion layers.

In FIG. 2B, the thermal oxide film 5 and the gate oxide film 2 on the source and drain diffusion layers are removed by using hydrofluoric acid.

In FIG. 2C, the polycrystalline silicon gate 3 is used as a mask and the dose amount is 4.0E13 cm −2 and the acceleration energy is 40.
Under the condition of KeV, P ions are implanted at an angle of 45 ° to form the low concentration diffusion layer 4. Next, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

The N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . In addition, the size of the gate electrode that serves as a mask at the time of implanting the low-concentration diffusion layer is smaller than the size of the photomask by the amount of oxidation on the side surface, so that a transistor with a short effective channel length can be formed. Further, since the low-concentration diffusion layer is formed after the source / drain implantation, there is no influence of accelerated diffusion due to defects generated at the source / drain implantation. As a result, the low-concentration diffusion layer can be formed shallowly, and a transistor with an excellent short channel effect can be formed.

(Embodiment 3) FIG. 3 is a sectional view showing the manufacture of an N-channel MOS type transistor according to a third embodiment of the present invention.

In FIG. 3 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing the polycrystalline silicon film, the photoresist is used as a mask to perform patterning by dry etching to form a polycrystalline silicon gate 3. Next, dose 6.0E15cm- ^2, implanting As ions with an acceleration energy 40 KeV, to form a source, a drain diffusion layer 6.

In FIG. 3B, thermal oxidation is performed in a pyro atmosphere at 900 ° C. to oxidize the upper surface and the side surface of the polycrystalline silicon electrode to form a thermal oxide film 5, and in the source and drain diffusion layers. The impurities of are activated.

In FIG. 3C, the thermal oxide film 5 and the gate oxide film 2 on the source and drain diffusion layers are removed by using hydrofluoric acid. Next, using the polycrystalline silicon gate 3 as a mask, P ions are implanted at an angle of 45 ° under the conditions of a dose amount of 4.0E13 cm-2 and an acceleration energy of 40 KeV to form a low concentration diffusion layer 4. Next, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . In addition, the size of the gate electrode that serves as a mask at the time of implanting the low-concentration diffusion layer is smaller than the size of the photomask by the amount of oxidation on the side surface, so that a transistor with a short effective channel length can be formed. Further, since the low-concentration diffusion layer is formed after the source / drain implantation, there is no influence of accelerated diffusion due to defects generated at the source / drain implantation. As a result, the low-concentration diffusion layer can be formed shallowly, and a transistor with an excellent short channel effect can be formed.

(Embodiment 4) FIG. 4 is a sectional view showing the manufacture of an N-channel MOS transistor according to a fourth embodiment of the present invention.

In FIG. 4 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing a polycrystalline silicon film of, and further depositing an oxide film 7 having a thickness of 150 nm by a known vapor phase growth method, patterning is performed by using dry etching using a photoresist as a mask to form a polycrystalline silicon gate 3. To do. next,
P under conditions of a dose of 4.0E13cm- ² and an acceleration energy of 40 KeV
Ions are implanted at an angle of 45 ° to form the low concentration diffusion layer 4.

In FIG. 4 (b), thermal oxidation is performed in a pyro atmosphere at 900 ° C. to oxidize the side surfaces of the polycrystalline silicon gate electrode to form a thermal oxide film 5.

In FIG. 4C, the polycrystalline silicon gate 3,
With the thermal oxide film 5 as a mask, the dose amount is 6.0E15cm-2,
After As ions are implanted under the condition of acceleration energy of 40 KeV to form the source / drain diffusion layer 6, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . Further, since the side wall of the gate electrode is oxidized, the overlap between the low concentration diffusion layer and the gate electrode is small, and the capacitance between the gate and the drain can be reduced. Further, since the upper surface of the gate polycrystalline silicon is covered with the oxide film, it is possible to prevent the gate electrode from being thinned by thermal oxidation, and the thickness of the gate electrode before oxidation can be set to the minimum necessary thickness. Steps can be eliminated as much as possible.

Although the upper surface of the gate polycrystalline silicon is covered with the oxide film in this embodiment, an insulating film such as a nitride film may be used. In particular, the use of a nitride film as the insulating film is superior in that the gate polycrystalline silicon has a high antioxidation ability.

(Embodiment 5) FIG. 5 is a sectional view showing the manufacture of an N-channel MOS transistor according to a fifth embodiment of the present invention.

In FIG. 5 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ under the conditions of a dose amount of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and further 150 n is formed using the well-known vapor phase growth method.
After depositing the oxide film 7 of m, the well-known vapor phase growth method is used.
After depositing a 300 nm polycrystalline silicon film, patterning is performed by dry etching using a photoresist as a mask to form a polycrystalline silicon gate 3. Next, thermal oxidation is performed in a pyro atmosphere at 900 ° C. to oxidize the upper surface and the side surface of the polycrystalline silicon electrode to form a thermal oxide film 5. Next, dose 6.0E15cm- ² , acceleration energy 40
As ions are implanted under the condition of KeV to form the source / drain diffusion layer 6. Next, heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes to activate the impurities in the source and drain diffusion layers.

In FIG. 5B, the thermal oxide film 5 and the gate oxide film 2 on the source and drain diffusion layers are removed by using hydrofluoric acid.

In FIG. 5 (c), the polycrystalline silicon gate 3 is used as a mask and the dose amount is 4.0E13 cm −2 and the acceleration energy is 40.
Under the condition of KeV, P ions are implanted at an angle of 45 ° to form the low concentration diffusion layer 4. Next, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . In addition, the size of the gate electrode that serves as a mask at the time of implanting the low-concentration diffusion layer is smaller than the size of the photomask by the amount of oxidation on the side surface, so that a transistor with a short effective channel length can be formed. Further, since the low-concentration diffusion layer is formed after the source / drain implantation, there is no influence of accelerated diffusion due to defects generated at the source / drain implantation. As a result, the low-concentration diffusion layer can be formed shallowly, and a transistor with an excellent short channel effect can be formed.
Further, since the upper surface of the gate polycrystalline silicon is covered with the oxide film, the gate electrode can be prevented from being thinned by thermal oxidation.

(Embodiment 6) FIG. 6 is a sectional view showing the manufacture of an N-channel MOS transistor according to a sixth embodiment of the present invention.

In FIG. 6 (a), B ions are implanted into a P-type silicon substrate 1 having a B concentration of 3.0E16 cm- ³ at a dose amount of 3.0E12 cm- ² and an acceleration energy of 30 KeV to obtain a threshold voltage. Take control. Next, a 10 nm gate oxide film 2 is formed using thermal oxidation, and then 300 nm is formed using the well-known vapor phase growth method.
After depositing a polycrystalline silicon film of, and further depositing an oxide film 7 having a thickness of 150 nm by a known vapor phase growth method, patterning is performed by using dry etching using a photoresist as a mask to form a polycrystalline silicon gate 3. To do. next,
As under the conditions of a dose of 6.0E15cm- ² and an acceleration energy of 40 KeV
Ions are implanted to form the source / drain diffusion layer 6.

In FIG. 6B, thermal oxidation is performed in a pyro atmosphere at 900 ° C. to oxidize the upper surface and the side surface of the polycrystalline silicon electrode to form a thermal oxide film 5, and in the source and drain diffusion layers. The impurities of are activated.

In FIG. 6C, the thermal oxide film 5 and the gate oxide film 2 on the source and drain diffusion layers are removed by using hydrofluoric acid. Next, using the polycrystalline silicon gate 3 as a mask, P ions are implanted at an angle of 45 ° under the conditions of a dose amount of 4.0E13 cm-2 and an acceleration energy of 40 KeV to form a low concentration diffusion layer 4. Next, heat treatment is performed in a nitrogen atmosphere at 850 ° C. for 30 minutes to complete the process.

The N-channel MO configured as described above
In the S-type transistor, an LDD-structured device can be formed without performing the gate electrode sidewall formation by depositing an oxide film and etching back the oxide film, which is a conventional technique, and the manufacturing process can be shortened. . In addition, the size of the gate electrode that serves as a mask at the time of implanting the low-concentration diffusion layer is smaller than the size of the photomask by the amount of oxidation on the side surface, so that a transistor with a short effective channel length can be formed. Further, since the low-concentration diffusion layer is formed after the source / drain implantation, there is no influence of accelerated diffusion due to defects generated at the source / drain implantation. As a result, the low-concentration diffusion layer can be formed shallowly, and a transistor with an excellent short channel effect can be formed.
Further, since the upper surface of the gate polycrystalline silicon is covered with the oxide film, the gate electrode can be prevented from being thinned by thermal oxidation.

The manufacturing method of the N-channel MOS type transistor has been described above.
It goes without saying that it is also applied to S-type transistors. Furthermore, it is also applied to a CMOS device having both N-channel MOS type transistors and P-channel MOS transistors. Further, in a CMOS device, an N channel MOS type transistor and a P channel M
By selecting each method of forming the OS type transistors, the effective channel length, the gate and the drain capacitance of both type transistors can be optimized independently.

[0051]

As described above, according to the present invention, it is possible to form a transistor having an LDD structure without forming a side wall using a conventional etchback method. Further, by selecting the forming method, it is possible to change the junction positions of the source, drain diffusion layer and the low concentration diffusion layer, and it is possible to adjust the effective channel length and the gate-drain capacitance.

[Brief description of drawings]

FIG. 1 is an N-channel MO according to a first embodiment of the present invention.
Process sectional view showing the manufacturing process of the S-type transistor

FIG. 2 is an N-channel MO according to a second embodiment of the present invention.
Process sectional view showing the manufacturing process of the S-type transistor

FIG. 3 is an N channel MO according to a third embodiment of the present invention.
Process side view showing the manufacturing process of the S-type transistor

FIG. 4 is an N-channel MO according to a fourth embodiment of the present invention.
Process sectional view showing the manufacturing process of the S-type transistor

FIG. 5 is an N channel MO in the fifth embodiment of the present invention.
Process sectional view showing the manufacturing process of the S-type transistor

FIG. 6 is an N-channel MO according to a sixth embodiment of the present invention.
Process sectional view showing the manufacturing process of the S-type transistor

FIG. 7 is a process cross-sectional view showing a manufacturing process of an N-channel MOS type transistor according to a conventional technique.

[Explanation of symbols]

 1 P-type silicon substrate 2 Gate oxide film 3 Polycrystalline silicon 4 Low concentration diffusion layer 5 Thermal oxide film 6 Source / drain diffusion layer 7 Oxide film

Claims (6)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of implanting an impurity using the gate electrode as a mask to form a low concentration diffusion layer, and a step of thermally oxidizing the gate. A method of manufacturing a semiconductor device comprising: a step of forming an oxide film on an upper surface and a side surface of an electrode; and a step of implanting impurities by using the gate electrode and the thermal oxide film as a mask to form a source / drain diffusion layer. 2. A method of manufacturing a semiconductor device according to claim 1, wherein after forming a gate electrode on the semiconductor substrate with an oxide film interposed therebetween, impurities are implanted using the gate electrode as a mask to form a low concentration diffusion layer. A method of manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein after the thermal oxide film is removed, impurities are implanted using the gate electrode as a mask to form a low concentration diffusion layer. Production method. 4. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of implanting impurities using the gate electrode as a mask to form a source / drain diffusion layer, and a step of using thermal oxidation. A semiconductor device including a step of forming an oxide film on an upper surface and a side surface of a gate electrode, and a step of removing impurities by using the gate electrode as a mask after removing the thermal oxide film to form a low concentration diffusion layer. Manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1 or 4, wherein the gate electrode comprises two layers of a first-layer conductive film and a second-layer insulating film. 6. The method for manufacturing a semiconductor device according to claim 4, wherein after the thermal oxide film is removed, impurities are implanted using the gate electrode as a mask to form a low concentration diffusion layer. Production method.