JP3058981B2 - Method for manufacturing transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor which operates at a high withstand voltage, and more particularly to a method of manufacturing an offset type MOS transistor.

[0002]

2. Description of the Related Art A conventional manufacturing process for a semiconductor device of this type will be described with reference to FIG.

First, as shown in FIG. 4A, a silicon oxide film (hereinafter, referred to as an SiO ₂ film) 403 and a silicon nitride film (hereinafter, referred to as a silicon nitride film) are formed on a P-type silicon substrate (hereinafter, referred to as an Si substrate) 401. , it says the Si ₃ N ₄ film) 405 is sequentially formed. Then, the SiO ₂ film 403 and Si ₃ N ₄
The film 405 is patterned, and the patterned SiO
₂ film 403 and Si ₃ N ₄ film 405 as a mask,
An N-type impurity layer 407 is formed in the substrate 401.

Next, as shown in FIG. 4B, a field oxide film 409 is formed by thermal oxidation in a steam atmosphere. At this time, the N-type impurity layer 407 is activated, and the offset diffusion layer 411 is formed. At the end of the field oxide film 409 (indicated by X in the drawing), a lateral extension of the oxide film called bird's beak occurs.

[0005] Next, as shown in FIG. 4 (C), Si ₃ N
After sequentially removing the ₄ film 405 and the SiO ₂ film 403, a gate oxide film 413 is formed by a thermal oxidation method, and a CV
A gate electrode 415 is formed and patterned by the method D. Using the patterned gate oxide film 413 and gate electrode 415 as a mask, N
By implanting a type impurity, a source diffusion layer 417 and a drain diffusion layer 419 are formed.

Next, as shown in FIG. 4D, an intermediate insulating film 421 is formed, and a contact hole 423 is opened.
When the wiring metal 425 is deposited and patterned, an offset MOS transistor is formed.

[0007]

In the semiconductor device obtained by the above-described method of manufacturing a semiconductor device, the charge electrons move from the source diffusion layer side to the channel portion below the gate electrode and the offset diffusion layer during the operation of the transistor. Flows to the drain diffusion layer side. However, the resistance of the contact portion (indicated by Y in FIG. 4) between the drain diffusion layer and the offset diffusion layer is large, and the conductance (hereinafter, referred to as gm) decreases.
As a solution to the reduction in gm, it is conceivable to change the concentration or depth of the offset diffusion layer. However, this not only changes the device characteristics but also causes the offset diffusion layer to diffuse below the gate oxide film. In addition, the effective gate length becomes short, which hinders the reduction of the device.

[0008]

According to the present invention, in order to solve the above-mentioned problems, an offset diffusion layer is extended toward a drain diffusion layer, and a large junction is formed.

[0009]

By forming a large junction between the offset diffusion layer and the drain diffusion layer, gm is improved and a transistor with a high breakdown voltage can be obtained.

Further, when a high voltage is applied, the strong electric field is relaxed, and the generation of the substrate current is suppressed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, a P-type Si substrate 101 containing boron having a substrate concentration of 1 × 10 ¹⁶ cm ^−3.
A 500 ° thick SiO ₂ film 103 is formed thereon by thermal oxidation, and a Si ₃ N ₄ film 105 is formed thereon by a CVD method, and is patterned by photolithography. Then, using the SiO ₂ film 103 and the Si ₃ N ₄ film 105 as masks, phosphorus is removed by a known ion implantation technique.
Si substrate 101 at a dose of × 10 ¹² ions / cm ²
To form an N-type impurity layer 107. At this time,
By using appropriate acceleration energy, Si ₃ N ₄
No phosphorus is introduced into the portion where the film remains.

Next, as shown in FIG. 1B, heat treatment is performed at 1000 ° C. for 400 minutes in a water vapor atmosphere.
A field oxide film 109 of 000 ° is formed. In this case, the bird's beak at the end of the field oxide film 109 is S
It extends about 0.8 μm from the edge of the i ₃ N ₄ film 105. The offset diffusion layer 111 formed simultaneously under the field oxide film 109 has a vertical dimension of 1.0 μm.
Since the light is diffused in the lateral direction by about 0.8 μm, the edge of the bird's beak and the edge of the offset diffusion layer are formed at substantially the same position.

Next, as shown in FIG. 1C, Si ₃ N
_{After the fourth} film 105 and the SiO ₂ film 103 are sequentially removed, the bird's beak 115 in a region where a drain diffusion layer is to be formed later is removed by about 0.4 μm by a known photolithographic etching using a photoresist 113.

Next, as shown in FIG. 1D, a gate oxide film 117 is formed by a thermal oxidation method, and a gate electrode 119 is formed thereon by a CVD method and patterned. Using the patterned gate oxide film 117 and gate electrode 119 as masks, arsenic As ⁺ is implanted into Si substrate 101 at a dose of 1.0 × 10 ¹⁶ ions / cm ² by a known ion implantation technique. 1000 ° C
Is performed for 30 minutes to form a source diffusion layer 121 and a drain diffusion layer 123 having a depth of about 0.5 μm.
At this time, since the drain diffusion layer 123 is diffused by about 0.4 μm in the lateral direction, the junction between the offset diffusion layer 111 and the drain diffusion layer 123 is about 0.8 μm.

Next, as shown in FIG. 1E, an intermediate insulating film 125 is formed, and a contact hole 127 is opened.
When the wiring metal 129 is formed, the offset type MOS transistor is completed.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 2A, a P-type Si substrate 201 containing boron having a substrate concentration of 1 × 10 ¹⁶ cm ^-3.
The first SiO ₂ film 20 having a thickness of 500 ° is formed thereon by thermal oxidation.
3 is formed and patterned by photolithographic etching.

Next, as shown in FIG. 2B, after forming a _second SiO ₂ film 205 having a thickness of 300 mm by thermal oxidation, a 2000 nm thick Si ₃ N ₄ film 207 is formed by a CVD method.
Is formed and patterned by photolithography.

Next, as shown in FIG. 2C, Si ₃ N
After removing the first SiO ₂ film 205 and the second SiO ₂ film 207 using the ₄ film 207 as a mask, 5 × 10 ¹² ions / cm of phosphorus is removed by a known ion implantation technique.
^An N-type impurity layer 209 is formed in the Si substrate 201 at a dose of ² .

Next, as shown in FIG. 2D, heat treatment is performed in a water vapor atmosphere to form a 10000 ° field oxide film 211. At this time, the bird's beak on the side where the drain diffusion layer was formed later was 0.4 μm, and the bird's beak on the side where the gate electrode was formed later was 0.8 μm. Therefore, the offset diffusion layer 213 formed under the field oxide film 211 diffuses 1.0 μm in the vertical direction and 0.8 μm in the horizontal direction, so that the side on which the gate electrode is to be formed later reaches the edge of the bird's beak and the drain diffusion layer later. On the side where the layer is formed, it is formed to extend about 0.4 μm outside the edge of the bird's beak.

Next, in the same manner as in the first embodiment, FIG.
As shown in (E), a gate oxide film 215 and a gate electrode 217 are sequentially formed, a source diffusion layer 219 and a drain diffusion layer 221 are formed, an intermediate insulating film 223 is formed, and a contact hole 225 is formed. , Wiring metal 225
Is formed, an offset type MOS transistor is completed.

Next, a third embodiment of the present invention will be described with reference to FIG.

First, as in the first embodiment, FIG.
As shown in FIG. 3A, a 300-mm thick SiO ₂ film 30 is formed on a P-type Si substrate 301 containing 1 × 10 ¹⁶ cm ⁻³ of boron.
₃ , forming a Si ₃ N ₄ film 305 having a thickness of 2000 mm in order,
After patterning, an N-type impurity layer 307 is formed.

Next, as shown in FIG. 3B, by using a photoresist 309 and performing wet etching with hydrofluoric acid (HF), Si ₃ on which a gate electrode is to be formed later is formed.
The SiO ₂ film 303 under the N ₄ film 305 is etched in the lateral direction 311 by about 0.4 μm.

Next, as in the first embodiment, FIG.
As shown in (C), 10,000 field oxide films 313 are formed. At this time, the offset diffusion layer 315 formed below the field oxide film 313 is vertically offset by 1.
0 μm, 0.8 μm in the lateral direction. On the other hand, bird's beak is 0.4 μm on the side where the drain diffusion layer is formed later.
m, on the side where the gate electrode is to be formed later, the SiO ₂ film 3
03 and the lateral direction 311 are etched by about 0.4 μm, so that they are formed to extend 0.8 μm. Therefore, the offset diffusion layer 315 is formed so as to extend to the edge of the bird's beak on the side where the gate electrode is to be formed later, and to extend about 0.4 μm outside the edge of the bird's beak on the side where the drain diffusion layer is to be formed later.

Next, as in the first embodiment, FIG.
As shown in (D), after forming a gate oxide film 317 and a gate electrode 319, a source diffusion layer 321 and a drain diffusion layer 323 are formed. After that, as shown in FIG. 3E, when an intermediate insulating film 325, a contact hole 327, and a wiring metal 329 are formed, an offset transistor is completed.

The embodiments of the present invention have been described with reference to the N-channel transistor formed on the P-type Si substrate. However, the P-channel transistor formed on the N-type Si substrate and the CMOS transistor formed with a well are described. Can also be applied.

[0029]

According to the present invention, the junction between the drain diffusion layer and the offset diffusion layer formed below the field oxide film can be enlarged, so that the conductance of the transistor is improved and a high breakdown voltage transistor can be obtained. .

Further, the strong electric field when a high voltage is applied is reduced, and the generation of the substrate current is suppressed, so that the reliability of the device is improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing a first embodiment of the present invention.

FIG. 2 is a process chart showing a second embodiment of the present invention.

FIG. 3 is a process chart showing a third embodiment of the present invention.

FIG. 4 is a process chart showing a conventional manufacturing method.

[Explanation of symbols]

Reference Signs List 101 P-type Si substrate 103 SiO ₂ film 105 Si ₃ N ₄ film 107 N-type impurity layer 109 Field oxide film 111 Offset diffusion layer 117 Gate oxide film 119 Gate electrode 121 Source diffusion layer 123 Drain diffusion layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] A first electrode region formed on a surface of the semiconductor substrate;
A step of implanting impurities into the surface of the semiconductor substrate between the first electrode region and the second electrode region, wherein the impurity is implanted by heat treatment. Forming an impurity diffusion region from the impurity and forming an insulating film on the impurity diffusion region; removing a part of the insulating film located in the vicinity of the first electrode region; Forming a gate electrode extending from the electrode region to another part of the insulating film. 2. A first electrode region and a second electrode region on a surface of a semiconductor substrate.
In the method of manufacturing a transistor in which the first electrode region is formed, a first mask film is formed in the first electrode region, and a second mask film thicker than the first mask is formed in the second electrode region. And implanting impurities into the surface of the semiconductor substrate between the first electrode region and the second electrode region using the first and second mask films, and performing a heat treatment. Forming an impurity diffusion region from the implanted impurity and forming an insulating film on the impurity diffusion region; removing the first and second mask films; and removing the insulating film from the second electrode region. Forming a gate electrode extending on another part of the film.