JPH0274042A - Manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To eliminate a fact that an effective channel length becomes shorter than the originally formed gate electrode length and to make it possible to manufacture stably a semiconductor element designed on the basis of a submicron dimension by a method wherein the diffused layers in the source and drain regions of a MIS transistor are formed in a poly Si layer. CONSTITUTION:An insulating film 2 and a gate electrode pattern are formed and thereafter, the surface of said gate electrode 3 is covered with an insulating film 22. After that, parts 10 of a semiconductor substrate 1 are selectively exposed, a poly Si layer 30 is formed on the surface of the substrate 1 and metal ions are implanted in the film 30. Thereby, as the spread of source and drain diffused layers to the lower part of the gate electrode, which is already formed, is eliminated, an effective channel length of a MIS transistor does never become shorter than the originally formed gate electrode length and a semiconductor element designed on the basis of a submicron dimension can be stably manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming an MIS type transistor with a submicron gate length in order to cope with ultra-miniaturization of MIS type semiconductor devices.

BACKGROUND OF THE INVENTION In the manufacturing process of conventional semiconductor devices, ion implantation is widely used to form impurity regions. For example, a MOS structure field effect transistor (hereinafter abbreviated as MOS transistor)
In order to form the source and drain regions, an impurity ion implantation method using a self-line method is carried out using a polycrystalline silicon film serving as an insulating film and a gate electrode layer as a mask. FIGS. 2a and 2b are process-order cross-sectional views for schematically explaining the manufacturing process of a MOS transistor using the self-line method. That is, at the stage shown in FIG. 2a, a silicon dioxide film 2 is formed on the surface of a silicon substrate 1, and a polycrystalline silicon film 3 which will become a gate electrode layer is further patterned in a predetermined shape on this film, and then a well-known ion film is formed. An impurity implantation layer 4 is formed in a predetermined surface region of the silicon substrate 1 by an implantation method. Then, at the stage of Figure 2, 90
Heat treatment is performed at 0°C to 1000°C to diffuse the impurity injection layer 4 and form the source region 5 and drain region 6.
form.

Problems to be Solved by the Invention In the conventional structure, as the dimensions of semiconductor elements become smaller and the minimum dimension becomes 1 micron or less, the standard is submicron, as shown in Figure 2. Due to the diffusion plate of the source region 5 and drain region 6 below the gate electrode, the effective channel length e of the MOS transistor becomes shorter than the originally formed gate electrode length, and the M
This causes inconveniences such as a fluctuation in the threshold voltage of the OS transistor and a drop in breakdown voltage between the source and drain. To reduce this effect, it is called an offset gate structure,
A structure in which the gate electrode near the drain region is separated to eliminate the overlapping part has been put into practice in the field of high voltage MOS transistors, but such an offset gate structure has the disadvantage of making it difficult to finely pour Wt into the device, and it is also difficult to achieve self-fabrication. Since it is not a line method, it adds complexity to the manufacturing process.

Means for Solving the Problems The method for manufacturing an MIS transistor of the present invention includes forming an insulating film and a gate electrode pattern, then covering the surface of the gate electrode with an insulating film, and then selecting a part of the semiconductor substrate. This method involves the steps of exposing the surface of the semiconductor substrate to a polycrystalline silicon layer, forming a polycrystalline silicon layer on the surface of the semiconductor substrate, and implanting metal ions into the polycrystalline silicon layer. These are used as the source and drain electrodes of the transistor.

Effect: According to the method for manufacturing an MrS type transistor of the present invention, the spread of the source and drain diffusion layers to the lower part of the formed gate electrode is eliminated, so that the effective channel length of the MIS type transistor is longer than the originally formed gate electrode length. The length does not become too short, and it is possible to stably manufacture semiconductor devices based on submicron dimensions.

Embodiment An embodiment of the method for manufacturing an MrS type transistor according to the present invention will be described with reference to step-by-step sectional views of FIGS. 1(a) to 1(d). FIGS. 1(a) to 1(d) are schematic cross-sectional views in order of steps for explaining the present invention in detail. First, by selective oxidation technology, as shown in FIG. 1(a), a silicon dioxide film 2 is formed to a thickness of about 20 nm on the surface of a P-type silicon substrate 1 on which an element isolation insulating film 7 is formed. Furthermore, after patterning a polycrystalline silicon film 3 that will become a gate electrode in a predetermined shape on this, the silicon dioxide film 2 is removed by etching with an aqueous solution containing hydrofluoric acid, and then etched at 900°C to 100°C.
When a silicon dioxide film 2 is formed to a thickness of about 20 ni on a silicon substrate 1 in a high-temperature steam atmosphere at 0° C., a silicon dioxide film 22 with a thickness of about 60 rv is formed on the surface of the polycrystalline silicon film.
is formed. Thereafter, the silicon dioxide 112 with a thickness of approximately 20 ns is removed by etching with an aqueous solution containing a hydrogen fluoride film to selectively expose a portion 10 of the semiconductor substrate, and then the surface is etched as shown in FIG. A polycrystalline silicon layer 30 is formed to a thickness of about 200 ns, and then arsenic for impurity diffusion is deposited at 3×10 at an acceleration voltage of 20 key.
About "ix-" is implanted into the polycrystalline silicon layer 30 by a well-known ion implantation method. Then, the temperature is 900°C to 1000°C.
Then, as shown in FIG. 1(C), a resist pattern 20 for selectively etching the polycrystalline silicon layer 30 is formed by a photolithography process, and then, as shown in FIG. ), a polycrystalline silicon layer 30 is used to form a source electrode 40 and a drain electrode 50 of an MIS type transistor.

In the above embodiment, a polycrystalline silicon film was used as the gate electrode, but any gate material that can be used in the self-line method, such as refractory metal silicide, can be used. Further, although arsenic was used as an example of ion implantation into the polycrystalline silicon layer, metal ions such as boron, phosphorus, aluminum, antimony, and compound ions thereof can be used, and ion implantation is not limited to this. The accelerating voltage and injection amount are not limited to the examples.

Furthermore, ion implantation may be divided into multiple steps, and different metal ions may be implanted multiple times.

Effects of the Invention According to the present invention, the thickness of the polycrystalline silicon layer to be formed, the metal ion species to be implanted, and the implantation conditions are appropriately determined in order to form the diffusion layers of the source and drain regions of an MIS type transistor in polycrystalline silicon. By combining this, it is possible to eliminate the spread of the source and drain diffusion layers to the lower part of the gate electrode formed, so MIS
The effective channel length of the type transistor does not become shorter than the originally formed gate electrode length. Furthermore, the manufacturing process is simple because the source and drain diffusion regions can be formed using self-alignment lines.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are schematic cross-sectional views in the order of steps for explaining the present invention in detail, and FIGS. 2(a) to (b) are schematic cross-sectional views in the order of steps for explaining the conventional example. be. 1... P-type semiconductor substrate, 2... silicon dioxide film, 3... polycrystalline silicon film, 4...
. . . Impurity implantation layer, 5 . . . Source region, 6
. . . Drain region, 7 . . . Inter-element isolation insulating film, 10 . . . Selectively exposed part of semiconductor substrate, 20 . . . Resist pattern. , 22・
...Silicon dioxide film formed on the surface of the polycrystalline silicon film, 30...Polycrystalline silicon layer, 40.
...Source electrode, 50...Drain electrode, e...Channel effective length, L...Gate electrode length. Name of agent: Patent attorney Shigetaka Awano and 1 other person (CL)

Claims (1)

[Claims] a step of forming a gate insulating film and a gate electrode on a semiconductor substrate; a step of covering the surface of the gate electrode with an insulating film;
The method includes the steps of selectively exposing a part of the semiconductor substrate, forming a polycrystalline silicon layer on the exposed surface of the semiconductor substrate, and implanting metal ions into the polycrystalline silicon layer. Characteristic method for manufacturing MIS transistors.