JPH0316150A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0316150A JPH0316150A JP1025975A JP2597589A JPH0316150A JP H0316150 A JPH0316150 A JP H0316150A JP 1025975 A JP1025975 A JP 1025975A JP 2597589 A JP2597589 A JP 2597589A JP H0316150 A JPH0316150 A JP H0316150A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- layer
- oxide film
- photosensitive material
- areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000463 material Substances 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 230000008595 infiltration Effects 0.000 claims description 2
- 238000001764 infiltration Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 4
- 230000003213 activating effect Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子の製造方法に関するものであり、更
に詳しくは、半導体素子を製造する時に選択的エビタキ
シャルＮ戊長技法を使用してバイボーラ１・ランジスク
、ＮＭＯＳトランジスタ、ＰＭＯＳトランジスタ等を同
一のＩＣチップ上に高密度に内蔵することができる半導
体素子の製造方法に関するものである．半導体の製造工
程が進行し、種々の層とパターンが形成されることによ
って、シリコン基板上に多数機種の素子等が形成される
が、複雑な回路を構或する場合には、もっと多い層とパ
ターンとが要求される。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a bibolar 1-Landisque, NMOS transistor, This invention relates to a method of manufacturing a semiconductor device that allows PMOS transistors and the like to be built in high density on the same IC chip. As the semiconductor manufacturing process advances and various layers and patterns are formed, many types of devices are formed on a silicon substrate, but when constructing a complex circuit, many more layers and patterns are formed. pattern is required.
また、このように複雑な回路を構戒する場合、素子が形
成される有効面積を殖やすほど、高密度化を期して同一
半導体素子内に多くの回路を内蔵させることができる．
しかしながら、従来の半導体素子の製造工程において素
子間の側面を分離する時に行う絶縁は、ＬＯＧＯＳ（選
択的酸化技法） ： Ｌｏｃａｌ Ｏｘｉｄａｔｉｏ
ｎ ｏｆ Ｓｉｌｉｃｏｎ）法を使用しているので、半
導体素子が形成される有効面積が大きく減少するもので
あった．即ち、第ｌ図において、選択的酸化方法では、
半導体基仮３１の上に薄い酸化膜層３２を形戊し、この
酸化膜層３２の上部に窒化膜Ｊｉ３３を塗布する．
また、素子間の分離のための領域を形成するため、フメ
トレジス１・３４を窒化膜層３３の上部に塗布した後、
写真ｉｉ！Ｉｔ刻工程によって窒化膜層３３の一部をは
刻させて開口３８を形成する。Furthermore, when constructing such a complex circuit, the more the effective area on which the element is formed, the more circuits can be built into the same semiconductor element to achieve higher density. However, in the conventional semiconductor device manufacturing process, the insulation performed when separating the sides between devices is called LOGOS (Local Oxidation Technique).
Since this method uses the 300 nm (n of Silicon) method, the effective area on which semiconductor elements are formed is greatly reduced. That is, in FIG. 1, in the selective oxidation method,
A thin oxide film layer 32 is formed on the semiconductor substrate 31, and a nitride film Ji 33 is applied on top of this oxide film layer 32. Further, in order to form a region for isolation between elements, after coating the fumetresis 1.34 on the upper part of the nitride film layer 33,
Photo ii! A part of the nitride film layer 33 is carved out by the It etching process to form an opening 38.
その後、前記シリコン半導体基板３ｌの導電形と同一導
電形の不′４ＦＡ物を高濃度に・イオン注入して、イオ
ン注入領域３５を形成した後、前記フォトレジスト層３
４を除去する．
次に、高温の炉で酸化工程に付すと、第ＩＢ図に示すよ
うに、厚いフィールド酸化マスクとして働く窒化膜［３
３の存在しない部分で急速に戒長して、フィールド酸化
膜１５３６を形成し、前記窒化膜層３３の端部でも側面
酸化が起こって、鳥嘴状３９のような形状が生じ、前記
イオン注入した不純物が活性化されるとともに拡散が起
こってチャネルストソバ領域３７が形戊される．
その後、窒化膜層３３を蝕刻除去し、酸化１１１１ｗ３
２も選択的に除去すると、第ＩＣ図のようになる。従っ
て、第１Ｃ図に示すように、後に半導体素子（ＰＭＯＳ
トランジスタ，ＮＭＯＳトランジスタ等）が形成される
半導体素子領域３０ａ．３０ｂが互いにフィールド酸化
膜層３６とチャネルストソバ領域３７とによって分離さ
れる。After that, ions of non-4FA having the same conductivity type as that of the silicon semiconductor substrate 3l are implanted at a high concentration to form an ion implantation region 35, and then the photoresist layer 3
Remove 4. Next, when subjected to an oxidation process in a high-temperature furnace, a nitride film [3
A field oxide film 1536 is formed in the area where the nitride layer 33 is not present, and lateral oxidation also occurs at the end of the nitride film layer 33, resulting in a bird's beak shape 39. The impurities are activated and diffused to form the channel strike region 37. After that, the nitride film layer 33 is removed by etching, and the oxidized 1111w3
If 2 is also selectively removed, the result will be as shown in Fig. IC. Therefore, as shown in FIG. 1C, later a semiconductor device (PMOS)
transistor, NMOS transistor, etc.) are formed in the semiconductor element region 30a. 30b are separated from each other by a field oxide layer 36 and a channel buckle region 37.
しかしながら、このようなｉ！沢的な酸化方法は、フィ
ールド酸化膜層３６の成長ずる時に形成される嘴部３９
の拡張と、チャネルストソバ領域３７の仰１面の拡敗に
よる素子領域３０ａ．３０ｂの縮小という問題点がある
。特に、メガビソト級以上の素子の！！！遣工程の時に
は、ｌμｍ以下を制御することができる製造技｛・ト１
が必要なので、高集積を要求する半導体素子では、選択
的な酸化方法を使用することが出来なかった。However, such i! The most common oxidation method is to remove the beak 39 formed during the growth of the field oxide layer 36.
, and the element region 30a. There is a problem of reduction of 30b. Especially for elements of megavisoto class or higher! ! ! During the shipping process, manufacturing technology that can control the thickness of 1μm or less is used.
Therefore, selective oxidation methods cannot be used in semiconductor devices requiring high integration.
本発明は、このような問題点を解決するために案出した
ものであり、本発明の目的は、半導体素子が形成される
有効領域の減少という問題を解決して高集積化すること
ができる半導体素子の製造方法を提供することにある．
このような目的は、半導体素子等の間の絶縁のため純枠
な酸化層を形成し、及び半導体素子等が形成される領域
層としてのエビクキンヤル層を選択的に成長させて、半
導体素子等の有効領域の減少を防止するとともに素子間
の絶縁距離を減少することによって達戊することができ
る。The present invention has been devised to solve these problems, and an object of the present invention is to solve the problem of reducing the effective area in which semiconductor elements are formed and to achieve high integration. The objective is to provide a method for manufacturing semiconductor devices. The purpose of this is to form a pure oxide layer for insulation between semiconductor devices, etc., and selectively grow an oxidized layer as a region layer where semiconductor devices, etc. are formed. This can be achieved by preventing a reduction in the effective area and reducing the insulation distance between elements.
本発明の特徴は、シリコン基板上に酸化膜層を形成した
後、第【感先物質を塗布し写真蝕刻工程によって窓を形
成する工程と、
第ｌ感光物質を除去した後、第２感光物質を塗布し写真
工程によってｎ＋理没層を形成する工程と、砒素等の５
価不純物をイオン注入してイオン注入領域を形成し、次
いで熱処理酸化及び′ｌ３：透方法によってｎ＋領域を
形戊する工程と、
蝕刻によって０４ ，ｌ域上部の酸化膜層を除去し、Ｐ
形エビタキシャル層を戒長させる工程とから戒る半導体
素子の製造方法にある。The features of the present invention include the steps of forming an oxide film layer on a silicon substrate, applying a second photosensitive material and forming a window by a photolithography process, and removing the first photosensitive material and then applying a second photosensitive material. The process of coating and forming an n+ sink layer by photo process, and the process of applying 5
ion implantation of valence impurities to form an ion implantation region, then forming an n+ region by heat treatment oxidation and a transparent method, and removing the oxide film layer above the 04 and l regions by etching;
The method of manufacturing a semiconductor device includes a step of lengthening an epitaxial layer.
以下、本発明の実施例を添付図面について詳細に説明す
る．
第２図は、本発明による実施例を示す製造工程であって
、ＢｉＣＭＯＳ素子の製造工程図である．第２Ａ図に示
すように、結晶方向が〈１００〉であり、比抵抗率０．
２〜３オームｃｍのＰ形Ｌｉｌ桔品のシリコン基板ｌの
上部に、酸化処理工程によって厚さ１．５μｍ程度の酸
化膜層２を形成する。Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a manufacturing process diagram showing an embodiment of the present invention, and is a manufacturing process diagram of a BiCMOS device. As shown in FIG. 2A, the crystal direction is <100>, and the specific resistivity is 0.
An oxide film layer 2 having a thickness of about 1.5 .mu.m is formed on the top of a P-type silicon substrate 1 of 2 to 3 ohm cm by an oxidation process.
フォトレジスト５である第１感光物質３をその上に塗布
し、次いで写真工程による蝕刻方法によって素子を形成
する有効領域の形成のための窓４を形成した後、第１感
光物Ｔｔ３を除去する。ここで、第ｌ感光物質３は窓４
を形成するためのマスク層として働く。第２Ｂ図に示す
ように、次の工程で第２感光物質５を全体的に塗布し、
後になってｎ埋没層を形成するための窓６７．８．９を
、マスク層を使用した一般的な写真蝕刻工程によって現
像した後、部分的に第２感光物質５を残したまま第２感
光物質を除去する。その後、イオン注入装置によって砒
素等の５価不純物を８０Ｋｅν程度の注入エネルギー及
び約ＩＥ１５ １０ｍｓ／ ｃ−のドーズでイオン注入
し、♂イオン注入領域１０〜ｌ３を形成する．
また、第２Ｃ図に示すように、第３工程では、砒素等の
５価不純物をイオン注入する時にマスク層として使用さ
れた第２感光物質５を除去し、そして熱処理酸化及び浸
透方法によって、イオン注入した不純物を活性化させて
ｎ領域ｌ４を形成する．
その後、熱処理酸化方法により領域１５〜２０の上部に
形成された酸化膜層を、一般的な蝕刻工程により除去し
、第２Ｄ図のようにした後、領域１５〜２０の上部に５
ΩｃＩ１程度のＰ形エピタキシャル層２ｌを約ｌ．５μ
ｍ程度成長させると、第２Ｅ図のような構造になる。次
にこのＰ形エピタキシャル１１１２１に通常的な製造方
法によりＰＭＯＳトランジスタ、ＮＭＯＳｈランジスタ
、バイポーラトランジスタ等を形成させると、第３図の
ようになる。A first photosensitive material 3, which is a photoresist 5, is applied thereon, and then a window 4 for forming an effective area for forming a device is formed by etching using a photo process, and then the first photosensitive material Tt3 is removed. . Here, the first photosensitive substance 3 is the window 4
Acts as a mask layer for forming. As shown in FIG. 2B, in the next step, the second photosensitive material 5 is applied entirely,
After the windows 67.8.9 for later forming the n-buried layer are developed by a common photolithographic process using a mask layer, the second photosensitive material 5 is partially left and the second photosensitive material 5 is left. remove the substance; Thereafter, a pentavalent impurity such as arsenic is ion-implanted using an ion implantation device at an implantation energy of about 80 Keν and a dose of about IE15 of 10 ms/c- to form male ion-implanted regions 10 to 13. In addition, as shown in FIG. 2C, in the third step, the second photosensitive material 5 used as a mask layer when ion-implanting pentavalent impurities such as arsenic is removed, and the ions are removed by heat treatment, oxidation, and infiltration. The implanted impurities are activated to form n-region l4. Thereafter, the oxide layer formed on the regions 15 to 20 by the heat treatment oxidation method is removed by a general etching process to form the structure shown in FIG. 2D.
The P-type epitaxial layer 2l with a resistance of about ΩcI1 is about l. 5μ
When grown by about m, the structure becomes as shown in FIG. 2E. Next, when a PMOS transistor, an NMOSh transistor, a bipolar transistor, etc. are formed on this P-type epitaxial layer 11121 by a normal manufacturing method, the result is as shown in FIG.
即ち、本発明は、各素子等を分離するのに使用する絶縁
層を先ず写真工程によって形成した後、エビクキシャル
成長′層を形成させることによって、絶ｕＦＪを形成す
る酸化層の拡散及び鳥嘴状の廖状が生じることを防止す
ることができるものであって、第２図及び第３図を比較
して見ると、側聞絶縁層の酸化膜層２の側間距離が最初
と最後の工程を通して殆ど一定に維持されるので、酸化
膜Ｎ２の間に形成される半導体素子の有効領域の減少を
防止することができる。以上のように、本発明は、素子
等の間の絶縁方法を純枠な酸化膜の壁で形成し、選択的
なエビタキシャル層の威長方法を使用して、素子が形戊
される有効領域の減少という問題を解決するとともに素
子等の間の絶縁距離を１μｍ水準以下に形成することが
できるので、高集積素子等の製造工程の時に超微細力Ｕ
工を行うことができる効果がある．That is, the present invention first forms an insulating layer used to separate each element, etc. by a photo process, and then forms an evixaxial growth layer to prevent the diffusion and bird's beak shape of the oxide layer forming the absolute uFJ. Comparing FIGS. 2 and 3, it can be seen that the distance between the oxide film layers 2 of the lateral insulating layers is the same as that of the first and last steps. Since it is maintained almost constant throughout, it is possible to prevent the effective area of the semiconductor element formed between the oxide films N2 from decreasing. As described above, the present invention provides an effective method for forming devices by using a pure oxide film wall as an insulation method between devices, and using a selective epitaxial layer growth method. This solves the problem of area reduction and allows the insulation distance between elements to be less than 1 μm, which reduces ultrafine force U during the manufacturing process of highly integrated devices.
It has the effect of allowing you to carry out a lot of work.
第ｌ図は、従東の半導体素子の製造方法を示す工程図、
第２図は、本発明による実施例を示す製造工程図、第３
図は、本発明による半導体素子の内部断面図であう・
図面の各部に対する符号の説明
１：恭仮、 ２．３２＝酸化膜層、
３：第１感光物質、
４，６，７，８，９，１５，１６，１７，１８，１９．
２（ｌ窓、
５：第２感光物質、
１０， １１， １２
１４：ｎ領域●
１ ３ ： ｎ”イオン注入領域、
ＦＩＧ．１Fig. 1 is a process diagram showing the manufacturing method of a semiconductor device by Juto; Fig. 2 is a manufacturing process diagram showing an embodiment according to the present invention;
The figure is an internal cross-sectional view of a semiconductor device according to the present invention. Explanation of the symbols for each part of the drawing 1: Kyoukari, 2.32 = oxide film layer, 3: first photosensitive material, 4, 6, 7, 8, 9 , 15, 16, 17, 18, 19.
2 (l window, 5: second photosensitive material, 10, 11, 12 14: n region● 1 3: n” ion implantation region, FIG. 1
Claims (2)
第１感光物質３を塗布し写真蝕刻工程によって窓４を形
成する工程と、 第１感光物質３を除去した後、第２感光物質５を塗布し
写真工程によってｎ＾＋埋没層を形成する工程と、砒素
等の５価不純物をイオン注入してイオン注入領域１０、
１１、１２、１３を形成し、次いで熱処理酸化及び浸透
方法によってｎ＾＋領域１４を形成する工程と、蝕刻に
よって領域１５〜２０の上部の酸化膜層を除去し、Ｐ形
エピタキシャル層２１を成長させる工程と、から成る半
導体素子の製造方法。(1) After forming the oxide film layer 2 on the silicon substrate 1,
A step of applying a first photosensitive material 3 and forming a window 4 by a photolithographic process; and a step of removing the first photosensitive material 3 and then applying a second photosensitive material 5 and forming an n^+ buried layer by a photolithographic process. Then, a pentavalent impurity such as arsenic is ion-implanted to form an ion-implanted region 10,
11, 12, and 13, and then forming an n^+ region 14 by heat treatment oxidation and infiltration method, and removing the oxide film layer on the upper part of regions 15 to 20 by etching, and growing a P-type epitaxial layer 21. A method for manufacturing a semiconductor device, the method comprising:
絶縁を行った後、エピタキシャル層２１の上に一般的な
半導体製造工程によってＰＭＯＳトランジスタ、ＮＭＯ
Ｓトランジスタ、バイポーラトランジスタ等を形成させ
る請求項１に記載の半導体素子の製造方法。(2) After performing the above steps and performing side-to-side insulation between semiconductor elements, etc., a PMOS transistor, an NMO
2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming an S transistor, a bipolar transistor, or the like.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880005983A KR890017771A (en) | 1988-05-20 | 1988-05-20 | Semiconductor device manufacturing method |
| KR88-5983 | 1988-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0316150A true JPH0316150A (en) | 1991-01-24 |
Family
ID=19274581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1025975A Pending JPH0316150A (en) | 1988-05-20 | 1989-02-06 | Manufacture of semiconductor element |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0316150A (en) |
| KR (1) | KR890017771A (en) |
| DE (1) | DE3903512A1 (en) |
| FR (1) | FR2631741A1 (en) |
| GB (1) | GB2218848B (en) |
| NL (1) | NL8900241A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008506271A (en) * | 2004-07-15 | 2008-02-28 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Formation of active region using semiconductor growth process without STI integration |
| US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5010034A (en) * | 1989-03-07 | 1991-04-23 | National Semiconductor Corporation | CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron |
| GB2439357C (en) * | 2006-02-23 | 2008-08-13 | Innos Ltd | Integrated circuit manufacturing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6021560A (en) * | 1983-07-15 | 1985-02-02 | Toshiba Corp | Complementary type mos semiconductor device and manufacture thereof |
| JPS6231153A (en) * | 1985-08-02 | 1987-02-10 | Matsushita Electric Ind Co Ltd | Manufacture of mis semiconductor integrated circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4412868A (en) * | 1981-12-23 | 1983-11-01 | General Electric Company | Method of making integrated circuits utilizing ion implantation and selective epitaxial growth |
| US4566914A (en) * | 1983-05-13 | 1986-01-28 | Micro Power Systems, Inc. | Method of forming localized epitaxy and devices formed therein |
| GB2142185A (en) * | 1983-06-22 | 1985-01-09 | Rca Corp | Mosfet fabrication method |
| DE3478170D1 (en) * | 1983-07-15 | 1989-06-15 | Toshiba Kk | A c-mos device and process for manufacturing the same |
| JPS6118148A (en) * | 1984-07-04 | 1986-01-27 | Hitachi Ltd | Manufacture of semiconductor device |
| KR880005690A (en) * | 1986-10-06 | 1988-06-30 | 넬손 스톤 | BiCMOS manufacturing method using selective epitaxial layer |
-
1988
- 1988-05-20 KR KR1019880005983A patent/KR890017771A/en not_active Application Discontinuation
-
1989
- 1989-02-01 NL NL8900241A patent/NL8900241A/en not_active Application Discontinuation
- 1989-02-03 GB GB8902401A patent/GB2218848B/en not_active Expired - Lifetime
- 1989-02-03 FR FR8901437A patent/FR2631741A1/en active Pending
- 1989-02-06 JP JP1025975A patent/JPH0316150A/en active Pending
- 1989-02-06 DE DE3903512A patent/DE3903512A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6021560A (en) * | 1983-07-15 | 1985-02-02 | Toshiba Corp | Complementary type mos semiconductor device and manufacture thereof |
| JPS6231153A (en) * | 1985-08-02 | 1987-02-10 | Matsushita Electric Ind Co Ltd | Manufacture of mis semiconductor integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008506271A (en) * | 2004-07-15 | 2008-02-28 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Formation of active region using semiconductor growth process without STI integration |
| US7985642B2 (en) | 2004-07-15 | 2011-07-26 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
| US8173502B2 (en) | 2004-07-15 | 2012-05-08 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
| US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
| US9607986B2 (en) | 2005-12-23 | 2017-03-28 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| NL8900241A (en) | 1989-12-18 |
| FR2631741A1 (en) | 1989-11-24 |
| GB2218848B (en) | 1991-10-23 |
| GB2218848A (en) | 1989-11-22 |
| GB8902401D0 (en) | 1989-03-22 |
| DE3903512A1 (en) | 1989-11-30 |
| KR890017771A (en) | 1989-12-18 |
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