JPS6266678A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the steps and the manufacturing time of a semiconductor device by using two different impurities having large diffusion coefficient at the same temperature in a semiconductor substrate. CONSTITUTION:An element separating field oxide film 3, a gate oxide film 2 and a polycrystalline silicon gate 1 are formed on a semiconductor substrate 4. After a P<+> type diffused region is coated with a resist, phosphorus P<+> ions are implanted to form an N<-> type diffused region through a thin oxide film formed on source and drain forming regions, and a low density phosphorus-doped layer 13 is formed on the substrate 4, arsenic (As<+>) ions are similarly implanted through an oxide film 6 to form an N<+> type diffused region to form a high density arsenic-doped layer 14 in the vicinity of the surface of the substrate. Then, a heat treatment is executed to activate two impurities of phosphorus and arsenic having different diffusion coefficient, thereby simultaneously forming a high density N<-> type diffused region 15 and a high density N<+> type diffused region 16. Thereafter, a CVD film 10 is coated, a contacting hole 11 is opened, and a wiring pattern 12 is contacted therethrough with the N<+> type diffused region.

Description

Detailed Description of the Invention (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device.
It is used to form a diffusion layer with a heavy concentration distribution.

[Technical day before invention]

The MO8 type semiconductor device 1 is becoming more and more high-voltage and smaller, and in order to avoid deterioration of the device due to electric field concentration at the drain end, the channel region at the end of the drain region t4 is made larger than the conventional train region. A structure with a low concentration diffusion region (hereinafter referred to as GDD: Grade Disused Dr.
ain) has been adopted.

Hereinafter, a conventional method for manufacturing a semiconductor device having a GDD structure will be explained with reference to FIG. 2. FIG. As shown in FIG. 2(A), a gate oxide film 2, a field oxide film 3 for element isolation, and a polycrystalline silicon gate 1 are formed on the surface of a semiconductor substrate 4 by a well-known manufacturing method. As shown in 8), after oxidizing the polycrystalline silicon gate 1 and the planned source and drain regions to form a thin oxide film 6, the p+ diffusion region (not shown) is protected with a resist and the planned n- diffusion region is formed. In order to form phosphorus, ion implantation of P (phosphorus) is performed to form a phosphorus-doped layer 5.Then, as shown in FIG. Activates phosphorus (P) and converts it into n-
A diffusion region 7 is formed.

Next, as shown in FIG. 2(D), the same opening +
Perform ion implantation of A (arsenic) for forming + to n diffusion regions,
An arsenic doped layer 8 is formed.

At this time, the p 2 diffusion region (not shown) is covered with a resist, as in the case of forming the phosphorus-doped layer 5 shown in FIG. 2(B). After removing the resist, a heat treatment is performed in an N2 or 02'B atmosphere to activate the doped arsenic and form an n diffusion region 9 as shown in FIG. 2(E).
form. In the subsequent process, a CVD film 10 is deposited and a contact hole 11 is formed as shown in FIG. 2(F) by a well-known manufacturing method. Then, the wiring pattern 12 is connected to the n diffusion region 1ii through this contact hole 11.
t9 to complete the semiconductor device.

[Problems with background technology]

As explained above, in the manufacturing process of an MO8 type transistor having a GDD structure, it is necessary to form an n-diffusion region and an n-diffusion region, compared to a normal process.

For this reason, it is necessary to repeat similar steps, which has the disadvantage that the steps are longer than devices in which a single impurity is implanted into the source and drain.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and the GDD
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can shorten the manufacturing process of an MO8 type semiconductor device having an eM structure.

[Summary of the invention]

In order to achieve the above object, the present invention injects a first impurity having a large diffusion coefficient into the semiconductor substrate at a low concentration through an opening provided in an injection blocking film on the semiconductor substrate, and also implants a first impurity having a small diffusion coefficient into the semiconductor substrate. A semiconductor having a first step of implanting a second impurity at a high concentration through the same opening, and a second step of performing a single heat treatment to form a diffusion layer with a double concentration distribution. A method for manufacturing the device is provided.

[Embodiments of the invention]

The present invention will be described in detail below with reference to FIG.

FIG. 1 is a cross-sectional view of an element according to steps for explaining a manufacturing method according to an embodiment. Note that the same parts as shown in FIG. 2 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

Field oxide film 3 for element isolation shown in FIG. 1(A),
Gate oxidation plI! 2. The process of forming the polycrystalline silicon gate 1 on the surface of the semiconductor substrate 4 is similar to the conventional technique shown in FIG. 2(A). As shown in Figure 1 (B),
After covering the p+ diffusion region (not shown) with resist, a thin oxide film 6 is formed in the source and drain regions.
Phosphorus (P) ions are implanted to form an n-diffusion region through the semiconductor substrate 4 to form a lightly doped phosphorus layer 13 on the surface of the semiconductor substrate 4.

Next, thinly oxidized F is applied to the planned source and drain diffusion regions via the same opening. via 6+
Ion implantation of arsenic (A>) is performed for the +tn diffusion region to form a highly concentrated arsenic doped layer 14 near the surface of the semiconductor substrate 4.

Next, as shown in FIG. 1(C), after removing the resist, heat treatment is performed in an N2 atmosphere to activate two impurities, phosphorus and arsenic, which have different diffusion coefficients, and form a low-concentration n-diffusion region 15 and a high-concentration n-diffusion region 15. n+ diffusion region 1416 is formed at the same time. In this way, arsenic for the n+ region has a small diffusion coefficient, so the n+ diffusion region 16 is formed shallowly, and phosphorus for the n- region has a large diffusion coefficient, so the n- diffusion region 15 is formed deeply. Using the following well-known manufacturing technology,
As shown in FIG. 2(D), after CVD lulO is deposited, a contact hole 11 is opened, and the wiring pattern 12 is brought into contact with the n+ diffusion region through the contact hole 11, thereby completing the device.

In addition, when adopting the above-mentioned process, the acceleration voltage for ion implantation of phosphorus is lower than the acceleration voltage for implantation of arsenic ions, and the time between phosphorus implantations is lower than that of arsenic implantation m.
It is desirable to hold it low.

However, the present invention is not limited thereto, and can be adjusted depending on the diffusion coefficient of impurities and the depth of the diffusion layer.

Under these conditions, it is possible to form a diffusion layer with a double concentration distribution by injecting two impurities through the same opening and performing a single heat treatment.

In the embodiments described above, silicon was used as the semiconductor substrate and phosphorus and arsenic were used as the two impurities, respectively. However, by using two impurities with significantly different diffusion coefficients at the same temperature for the semiconductor substrate, The present invention can be similarly applied to other semiconductor substrates. Hey again.

Antimony etc. can also be used instead of the raw material.

It can be applied not only to n-type impurities but also to n-type impurities.

〔Effect of the invention〕

As described above, in the present invention, a first impurity having a large diffusion coefficient into a semiconductor substrate is implanted at a low concentration, a second impurity having a small diffusion coefficient is implanted at a high ig of 1 degree, and a single heat treatment is performed. Since a diffusion layer having a concentration distribution of 300 nm is formed, a direct manufacturing method for semiconductor 5A can be obtained that can shorten the process and shorten the fabrication time when forming an MO8 type semiconductor device having a GDD structure. It will be done.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an element according to steps for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of an element according to steps for explaining a conventional manufacturing method. 13... Phosphorus doped layer, 14... Arsenic doped layer, 1
5°...n-diffusion region, 16...n+ diffusion region. Applicant's representative: Sa Hi-O Figure 1 Figure 2

Claims (1)

[Claims] 1. A semiconductor device in which two types of impurities with different concentrations are diffused through the same opening provided in an injection blocking film on a semiconductor substrate to form a diffusion layer with a double concentration distribution. In the manufacturing method, a first impurity having a large diffusion coefficient into the semiconductor substrate is implanted at a low concentration through the opening, and a second impurity having a small diffusion coefficient is implanted at a high concentration through the opening. and a second step of forming the diffusion layer having a double concentration distribution by performing a single heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is silicon, and the first and second impurities are phosphorus and arsenic, respectively.