JP3309529B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor and a manufacturing method.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a first conductivity type impurity layer (hereinafter referred to as a well diffusion layer) on a silicon substrate, an element isolation region formed by selective oxidation, and a MOS transistor is as follows. is there. As shown in FIG. 2A, a first silicon oxide film is formed on a silicon substrate 201, a well impurity is implanted, and then a well diffusion layer 202 is formed by a thermal diffusion method. Next, a silicon nitride film is deposited, the photoresist is removed only in a region where element isolation is to be formed using a photoresist, and the silicon nitride film is removed using the photoresist as a mask. After removing the photoresist, a channel stopper 203 is implanted using the silicon nitride film as a mask. Next, an element isolation silicon oxide film 204 is selectively formed in the element isolation region by thermal oxidation using the silicon nitride film as a mask. Thereafter, the silicon nitride film and the first silicon oxide film are removed, and before the gate oxidation, the second silicon film is removed by a thermal oxidation method for the purpose of removing impurities on the substrate surface and relaxing stress by forming an element isolation silicon oxide film. An oxide film 205 is formed.

Next, as shown in FIG. 2B, after removing the second silicon oxide film 205, a gate oxide film 206 of a MOS transistor is formed by a thermal oxidation method, and polysilicon is deposited by a CVD method. Then, the gate electrode 207 is formed by patterning using a photoresist and performing dry etching. Finally, using the device isolation silicon oxide film 204 and the gate electrode 207 as a mask, a high-concentration diffusion layer 208 serving as a source / drain region of a MOS transistor is formed by ion implantation.

[0004]

In recent years, semiconductor devices have been highly integrated, and the structure of semiconductor elements such as MOS transistors has become complicated. Is getting higher.

The gate length of a MOS transistor is also reduced to half a micron, and the power supply voltage of a semiconductor device is also reduced in order to maintain high reliability.

In the above-described conventional semiconductor device, MOS
The impurity concentration of the well diffusion layer 202 is increased for miniaturization of the type transistor. When trying to operate such a semiconductor device at a low voltage, the leakage current in the off state of the MOS transistor increases due to the deterioration of the subthreshold characteristic, and the threshold voltage cannot be lowered. In particular, in a semiconductor memory device with low current consumption such as a static random access memory (SRAM), not only does the current consumption increase, but also the operation of the memory cell becomes unstable.

Therefore, the present invention is intended to solve such a problem, and an object of the present invention is to improve the subthreshold characteristics of the MOS type transistor with miniaturization of the element, thereby achieving low-voltage operation and low-voltage operation. It is an object of the present invention to provide a semiconductor device with high current consumption, high speed and high reliability, and a method for manufacturing the same, and to reduce the cost of a wafer process by reducing the number of manufacturing steps as compared with a conventional semiconductor device manufacturing method.

[0008]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a gate electrode, a channel, and a source / drain region formed on a semiconductor substrate. Forming a resist in a region where a gate electrode of the MOS transistor is formed, performing ion implantation using the resist as a permeable film, introducing impurities into the semiconductor substrate, and performing a heat treatment on the impurities. Forming the well of the region where the channel is formed shallower than the well of the region where the source / drain is formed.

Further, a method for manufacturing a semiconductor device according to the present invention
A method of manufacturing a semiconductor device including a MOS transistor on a semiconductor substrate, comprising: forming a resist on a region of the semiconductor substrate where a gate electrode of the MOS transistor is to be formed; Performing a step of introducing impurities into the semiconductor substrate in a region where the resist is formed and a region where the resist is not formed, and performing a heat treatment on the semiconductor substrate;
Forming a well and forming an oxide film on the semiconductor substrate, removing the oxide film, and forming a gate insulating film on the semiconductor substrate in this order. I do.

[0010]

Next, an embodiment of the present invention will be described with reference to FIG.
This will be described in detail with reference to element cross-sectional views shown in FIGS.

First, a first silicon oxide film layer of about 20 nm is formed on an N-type semiconductor substrate 101 having a specific resistance of 10 to 100 Ω in an oxidizing atmosphere at 1000 ° C. for 20 minutes. A silicon nitride film layer of a degree is formed. Next, a photoresist is applied, the resist is patterned using a projection exposure method, and SF ₆ ,
The silicon nitride film layer is dry-etched using an etching gas such as CF ₄ .

The photoresist is removed, and the silicon nitride film layer is used as a mask in an oxidizing atmosphere at 900 to 12 mm.
FIG. 1A shows a state in which the element isolation silicon oxide film 102 is formed by thermal oxidation at 00 ° C. for 60 to 200 minutes, and the silicon nitride film layer is removed with hot phosphoric acid or the like.

Next, a photoresist is applied, patterning is performed only in a region where a gate electrode of a MOS transistor is formed by using a projection exposure method, and then boron is implanted by an ion implantation method.

The conditions for the implantation of the resist and boron at this time are, for example, that the resist is applied to a thickness of 1000 nm, the boron is implanted under the conditions of about 90 to 100 KeV, and about 5 × 10 ^{12 to} 5 × 10 ^13. It is desirable that the concentration peak be on the substrate surface.

Next, the photoresist is removed and thermally oxidized in an oxidizing atmosphere to form a second silicon oxide film 103 and a PWELL region 104. This state is shown in FIG.
(B).

At this time, the thermal oxidation conditions are such that the oxygen content is 1-5.
% Thermal oxidation at 900 to 1000 ° C. for about 10 to 20 minutes is desirable.

Next, for example, when the ratio of HF to H ₂ O is 1:10
The silicon oxide film formed by the thermal oxidation is removed with the mixed solution of the above, a gate oxide film 105 of about 10 to 20 nm is grown by using the thermal oxidation method, and the gate oxide film 105 is formed by using the CVD method.
After a polycrystalline silicon layer having a thickness of about 0 nm is formed, phosphorus is implanted by a thermal diffusion method, patterning is performed, and dry etching is performed to form a gate electrode 106. Next, arsenic is ion-implanted at 50 KeV and 1 × 10 ¹⁵ to 1 × 10 ¹⁶ to form source and drain regions of the MOS transistor.
FIG. 1 is a cross-sectional view of the final step of the embodiment of the present invention in which the high-concentration N-type diffusion layer 107 is formed by implanting / cm ² .
(C).

In the embodiment of the present invention, a surface channel type N-channel MOS transistor in which a PWELL region and an N-type polysilicon gate electrode are provided on an N-type semiconductor substrate has been described. However, the NWELL region and a P-type polysilicon gate electrode are provided. May be provided as a surface channel P-channel MOS transistor.

[0019]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the PWELL region 104 is shallow under the gate electrode 106 and the high concentration N-type diffusion layer 1 is formed.
07, the PWELL region 104 below the gate electrode is completely depleted and the N-type semiconductor substrate 101 is depleted, so that the depletion capacitance can be significantly reduced. .

The sub-threshold characteristic of the MOS transistor is improved in inverse proportion to the depletion capacitance below the gate electrode, so that the sub-threshold characteristic is improved.

Further, since the PWELL region 104 below the high concentration N-type diffusion layer 107 is formed deeper than the PWELL region 104 below the gate electrode 106, the PWELL region 104 is The capacitance applied to the PN junction formed by the PWELL region 104 is reduced, and the leakage current at the PN junction can be reduced, so that low voltage operation, low current consumption, high speed and high reliability are possible. A semiconductor device including the MOS transistor described above can be supplied.

Further, according to the method of manufacturing a semiconductor device of the present invention, the conventional thermal oxidation step before the gate oxidation can be used as the thermal oxidation at the time of forming the PWELL region 104.
According to the method of manufacturing a semiconductor device of the present invention, PWEL
Since the L region is formed after the formation of the element isolation silicon oxide film, the impurity concentration under the element isolation silicon oxide film does not decrease due to thermal oxidation, and good element isolation characteristics can be obtained without forming a channel stopper conventionally performed. be able to.

Therefore, in the method of manufacturing a semiconductor device according to the present invention, the number of steps in the wafer process can be reduced as compared with the conventional manufacturing method, so that the cost of the wafer process can be reduced.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing an embodiment of the present invention.

FIG. 2 is a vertical sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 101 ... N-type semiconductor substrate 102, 204 ... element isolation silicon oxide film 103, 207 ... second silicon oxide film 104 ... PWELL region 105, 206 ... gate oxide film 106, 207 ... · Gate electrode 107 ··· High concentration N-type diffusion layer 201 ··· Semiconductor substrate 202 ··· Well diffusion layer 203 ··· Channel stopper 208 ··· High concentration diffusion layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/8238 H01L 27/092

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device comprising a gate electrode, a channel, and a source / drain region formed on a semiconductor substrate, the method comprising: forming a gate electrode of the MOS transistor on the semiconductor substrate in a region where the gate electrode is formed; Forming a resist, performing ion implantation using the resist as a permeable film, and introducing an impurity into the semiconductor substrate, performing a heat treatment on the impurity, and forming a well in a region where the channel is formed into the source. A step of forming the drain shallower than a well in a region where the drain is formed. 2. A method of manufacturing a semiconductor device having a MOS transistor on a semiconductor substrate, comprising: forming a resist in a region on the semiconductor substrate where a gate electrode of the MOS transistor is formed; Performing ion implantation as a film, introducing impurities into the semiconductor substrate in a region where the resist is formed and a region where the resist is not formed, and performing a heat treatment on the semiconductor substrate to form a well. A step of forming an oxide film on the semiconductor substrate; a step of removing the oxide film; and a step of forming a gate insulating film on the semiconductor substrate in this order. Method.