JPS60235437A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a channel stopper on side faces of a groove in a self-aligning manner for preventing a parastic channel from being produced, by introducing an impurity only into a region for forming a groove with the use of a groove forming mask and by forming the groove so as to leave the impurity layer located under the mask. CONSTITUTION:An etching mask 32 is provided on the surface of a silicon substrate 31, and ions of p type impurity 33a such as boron are implanted in an aperture of the mask to provide a p type region 35a having a high impurity density. A p type impurity layer 35 is driven in by thermal treatment at a high temperature to form a p type region 36. The silicon substrate 31 is then etched anisotropically with the use of the film 32 as a mask so as to form a shallow groove 37. This process is repeated for several times according to a required depth of the groove, and finally a channel stopper layer 39 can be formed on the side faces of the deep groove.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for suppressing the generation of parasitic channels in a semiconductor device, and in particular, a channel stopper layer for preventing the generation of vertical parasitic channels on the side walls of deep trenches. The present invention relates to a method of manufacturing a semiconductor device suitable for forming a semiconductor device.

[Background of the invention]

In order to further increase the integration of large-scale integrated circuits (LSI),
As shown in FIG. 1, deep grooves 12 formed in a semiconductor substrate 11 have been utilized in recent years. However, the conductivity type of the surface of the side wall portion 13 of this deep groove is reversed due to the high density of surface states, redistribution of impurities, etc., and a parasitic channel is formed. This parasitic channel has undesirable effects such as increasing leakage current between elements.

Therefore, preventing the generation of this parasitic channel is very important when utilizing the deep groove shown in FIG.

[Purpose of the invention]

An object of the present invention is to solve the problems of the prior art and to
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a channel stopper for preventing the generation of a parasitic channel is formed in a self-aligned manner on the side surface of a deep groove that contributes to high integration of I.

[Background of the invention]

In order to achieve the above object, in the present invention, after forming an etching mask for forming a groove in a semiconductor substrate,
Using this mask, impurities are introduced only into the region where the groove will be formed, and heat treatment is used to introduce the impurities under the mask. The present invention is characterized in that grooves are formed without side etching by etching, and as shown in FIG.
” channel stopper layer 23 is formed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples.

Example 1 FIG. 3 is a process diagram showing Example 1. In the following, a case using a low concentration P-type silicon substrate will be explained as an example.

First, on the surface of the silicon substrate 31, a photoresist film or Si
An etching mask 32 made of an O□ film is formed, and a p-type impurity 33a such as boron is injected into the opening of the mask for 10'2 to 10 minutes.
1013 am-' ion implantation is performed to form a p shadow region 35a with a high impurity concentration. In order to prevent contamination and ion channeling during ion implantation, it is preferable to form a thin SiO□ film 34 with a thickness of 10 to 50 nm on the surface of the silicon substrate (FIG. 3(A)).
P heat treated at a high temperature of 1100℃ and ion implanted
A P shadow region 36 having a depth of about 1 .mu.m and an impurity concentration of 10 Ig to 10 "cm" is formed by driving in the shaped impurity layer 35 (FIG. 3(B)). Next, using the film 32 as a mask, the silicon substrate 31 is etched anisotropically by 1 to 2 μm to form a shallow groove 37. At this time, p inside the mask opening
Although the shadow area 36 is removed by etching, the mask 3
Since the P-type impurity wraps around and diffuses under 2, a P shadow region 36' remains.

Then again the p-type impurity 33 b &10''~10
I310l3 ion implantation and p shadow area 35 at the bottom of the groove
b (Fig. 3(C)). Next, the p-type impurity layer 35b is driven in again by high-temperature heat treatment to form a P shadow region 38 around the trench (FIG. 3(D)). This process is repeated several times depending on the groove depth as shown in Figure 3 (E).
), finally forming a channel stopper layer 39 on the side surface of the deep groove as shown in FIG. 3F.

Embodiment 2 FIG. 4 is an embodiment in which the channel stopper forming method according to the present invention is applied to a high resistance element formed in a deep groove.

This high resistance element is used in large capacity static RAM (Ra
It is used for memory cells of ndom access memory), and its structure is n-type silicon 41
Inside the deep groove 43 formed so as to pass through the P-shaped well region 42 with a depth of 2 to 6 μm formed in the surface region,
A high-resistance polycrystalline silicon 45 of 10 to 10'2 Ω is embedded through an insulating film 44 such as Sin. A power supply voltage is applied to the n-type silicon substrate 41, and a minute current is supplied to the drain diffusion layer 47 of the MOS transistor through the high resistance polycrystalline silicon 45. Since the P-well 42 is at ground potential, a parasitic channel is formed on the side surface of the deep groove 47. In order to prevent the formation of this parasitic channel, a channel stopper 46 is formed on the side surface of the groove by the method according to the invention.

FIG. 5 is a diagram showing a process for forming a channel stopper in the high resistance element shown in FIG. 4. First, Figure 5 (A
), a thermal oxidation method was used to deposit 10 to 50 nm on the surface.
A semiconductor substrate 51 on which a thin silicon oxide film 53 of m is formed.
After forming a stacked film of a polycrystalline silicon film 54 of 100 to 500 nm and a silicon oxide film 55 of 1 to 2 μm on top by vapor phase growth, a window is opened only in this stacked film by photoetching, and a thin silicon oxide film is formed. The film 53 is left.

Next, as shown in FIG. 5(B), using the remaining overlapping film as a mask, the thin silicon oxide film 53 is passed through the silicon substrate 5.
After implanting 10'3 to 10150I11-2 ions of boron 56 into the substrate 1, the boron ions are diffused under the layered film by high-temperature treatment at about 100° C. to form a P shadow region 56. Next, as shown in FIG. 5C, using the remaining overlapping film as a mask, a trench is formed in the silicon substrate to a depth of 2 to 6 μm deeper than the p-well by an anisotropic dry etching method.
8 is formed, and at the same time, a diffused boron ion implantation layer 59 is left around this groove under the layered film to serve as a parasitic channel stopper. Finally, as shown in FIG. 5(D), a silicon oxide film 60 of 100 to 500 nm is left only on the side wall of the groove (58 in FIG. 5C) formed in the silicon substrate, and Polycrystalline silicon 61 having a high resistance is buried in the trench so that its bottom surface contacts the substrate silicon 51. In this embodiment, the channel stopper layer 59 only needs to be formed within the n-well 52.

Embodiment 3 FIG. 6 shows an embodiment in which the channel stopper forming method according to the present invention is applied to a well isolation structure of a complementary MO3 transistor (hereinafter abbreviated as CMO8). In this embodiment, the surface of the silicon substrate 71 has a depth of 2 to 6 mm.
A p-type well 73 and an n-type well 74 of μm are formed, and a deep groove 72 is formed at the boundary to separate them.
is formed. Since parasitic channels are likely to occur at the interface between the deep groove 72 and the p-type well,
A channel stopper 75 is formed only on the side surface of the well. A parasitic channel is less likely to occur on the n-well side surface of the deep trench, and no channel stopper is formed in this embodiment. Such a structure in which the channel stopper is formed only on one side wall of the deep groove can be realized by making the impurity concentration of the n-well higher than the impurity concentration of the channel stopper in the n-well.

〔Effect of the invention〕

As explained above, according to the present invention, a channel stopper for suppressing the generation of a parasitic channel can be formed in a self-aligned manner on the side surface of a deep groove formed in a semiconductor substrate, thereby significantly reducing the manufacturing process. It is possible to realize a stable manufacturing process and a deep groove shape with good electrical characteristics without any additions or changes, which greatly contributes to higher integration of LSIs.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional structural diagram of a deep trench formed in a semiconductor substrate.
Fig. 2 is a cross-sectional structural diagram of a single layer of channel stopper formed on the side surface of a deep groove according to the present invention, Fig. 3 is a cross-sectional structural diagram showing the process of forming a single layer of channel stopper of the present invention, and Fig. 4 is a structural diagram of a channel stopper of the present invention. Cross-sectional structural diagram showing an example in which the method is applied to a high resistance element formed in a deep groove, No. 5
The figure is a cross-sectional structural diagram showing the process of forming a single layer of channel stopper in the high resistance element shown in FIG. 4, and FIG. 6 is a cross-sectional view showing an example in which the channel stopper forming method according to the present invention is applied to a CMO8 well isolation structure. It is a structural diagram.

Claims (1)

[Claims] 1. - Forming a film on a conductive type semiconductor substrate;
This film is used as a mask to ion-implant impurities of the same conductivity type as the substrate, followed by heat treatment, and the same film is used again as a mask to form elements on the substrate so that the ion-implanted layer that goes under the film remains on the side wall. A method of manufacturing a semiconductor device, comprising the step of forming a groove in a region.