JPS61119075A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61119075A
JPS61119075A JP24101984A JP24101984A JPS61119075A JP S61119075 A JPS61119075 A JP S61119075A JP 24101984 A JP24101984 A JP 24101984A JP 24101984 A JP24101984 A JP 24101984A JP S61119075 A JPS61119075 A JP S61119075A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
groove
formed
capacity part
silicide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24101984A
Inventor
Isami Sakai
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10861Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor being in a substrate trench

Abstract

PURPOSE:To enable the formation of an N type impurity diffusion layer on side planes of the groove in a capacity part of a DRAM memory cell by rapid diffusion of impurities into a silicide layer even when the groove is deep and to enable the control of the distribution of concentration with high accuracy by doping impurities by ion implantation. CONSTITUTION:Boron ions are implanted into an inert region of a P type silicon substrate 101 as a channel stopper and a field oxide film 102 is grown in the inert region selectively. At the same time, a channel stopper impurity diffusion layer 103 is formed. In a capacity part of an active region, a groove of 5mum deep is formed by reactive ion etching and a tungsten silicide layer is grown to form a tungsten silicide layer 105 in the capacity part. A window 107 of a photoresist 106 is formed in the capacity part and an ion implantation layer of arsenic is formed. By a heat treatment, arsenic included in the ion implantation layer 108 is diffused into the tungsten silicide layer 105 and further into the silicon substrate on side planes of the groove thereby forming an N type diffusion layer 109.
JP24101984A 1984-11-15 1984-11-15 Manufacture of semiconductor device Pending JPS61119075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24101984A JPS61119075A (en) 1984-11-15 1984-11-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24101984A JPS61119075A (en) 1984-11-15 1984-11-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61119075A true true JPS61119075A (en) 1986-06-06

Family

ID=17068123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24101984A Pending JPS61119075A (en) 1984-11-15 1984-11-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61119075A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298158A (en) * 1986-06-17 1987-12-25 Nec Corp Semiconductor memory
JPS6420648A (en) * 1987-07-15 1989-01-24 Toshiba Corp Semiconductor device and manufacture thereof
JPH08306882A (en) * 1995-05-11 1996-11-22 Nec Corp Semiconductor device and fabrication method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298158A (en) * 1986-06-17 1987-12-25 Nec Corp Semiconductor memory
JPS6420648A (en) * 1987-07-15 1989-01-24 Toshiba Corp Semiconductor device and manufacture thereof
JPH0579182B2 (en) * 1987-07-15 1993-11-01 Tokyo Shibaura Electric Co
JPH08306882A (en) * 1995-05-11 1996-11-22 Nec Corp Semiconductor device and fabrication method thereof

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