JPH0321039A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit of high performance, high reliability, and high integration by demarcating plural impurity well regions and element formation regions with the same trenches, and connecting adjacent impurity well regions with an impurity region provided at the side and the bottom of the trench. CONSTITUTION:Plural opposite conductivity type impurity well regions 2 and 3 and element formation regions formed at the one conductivity type semiconductor substrate 1 are demarcated by trenches 4 which are deeper than the impurity well regions 2 and 3 and are filled with insulating films 5, and the impurity well regions 2 are connected by opposite conductivity type impurity regions 6 formed at the sides and the bottoms of the trenches. Accordingly, the element isolating regions can be formed without using the LOCOS method by selective oxidation, so it can be formed in such structure that birds' beak including stress does not exist. Moreover, since the impurity well regions 2 and 3 can be formed in self alignment by insulating film isolation, an impurity well region 2, which includes a minute impurity well contact region 9, and boundary region can be formed. Hereby, a semiconductor integrated circuit of high performance, high reliability, and high integration can be obtained.

Description

[Detailed Description of the Invention] [Summary 1] The plurality of impurity well regions and element-forming regions are deeper than the impurity well regions, and are formed by inserting an insulation layer into the I-1. The structure is such that the impurity well region is connected by an impurity region of opposite conductivity type formed on the side and bottom portions of the I-wrench. As a result, it is possible to form a structure in which there is no element isolation region or bird's beak, resulting in thinning of the element region, improvement of GaI-oxide film breakdown voltage, and improvement of carrier J7 life.
The impurity well region and boundary region can be miniaturized by forming J'A on the self-alignment line, the latch-up can be improved by separating the impurity well region with an insulating film, and the impurity region can be formed by self-alignment to form the impurity region for connection between the impurity well regions. RL Noel head J or fine 6911
Easy connection due to the ability to tilt the source train region and channels 1 hepar 1 heart region 31
1. [Industrial Application Field] The present invention relates to MIS type semiconductor devices, and is particularly applicable to MIS type semiconductor devices, in which fine impurity 9 I-, ST.9 regarding definition of fine impurity well region including P7 L contact I region and formation of fine element isolation region. For super 1-S, etc., highly integrated MTS type half-half assembly (,.2, half-half, Hayabusa (4) (f-1' for the fine 1 element of the element M[ The E area piles up, so f+
The formation of the impurity well region is not self-aligned, the impurity well contact area is not very fine, and so on. The problem of f\ being criticized is becoming more and more obvious.
There is a need for a means that can be realized by a relatively simple process that improves the miniaturization of the impurity P7 well region including the well contact I region by self-lining and the miniaturization of the element isolation region.

[Prior art] Fig. 4 is a schematic side sectional view of a single semiconductor device from JK.
is a p-type silicon (Si) substrate, 52 is an I) type impurity well region, and 53 is a p-type impurity 'J! 4Ny/L region, 1jA is r〕type channels 1 heliper';j"j
JrHQ, j) 5 is p:% (+!.=1- Janels I
Hetuber region, 56 is field T' oxide film, j]7 is n
ten-shaped source train region, 584; l. r) 10-type source train 1 or. 59 is p 10 type r'y L: 1 ntata I'ii1't J! r'see, 60 is n ten saints rn enore:? Nctor 7-. il. b+lj, 61 is game 1
- 1 Shun 1 Hi I! , Σ, 62L1 month I・', Hi 4・9
j, 63 shi, 1 bu, Notagawa acid 1 arsenic membrane, G4 ha'lA
Silicate glass (PSG) IVA, 65L: i. AI wiring is shown.

In the same figure, the L O CO S method {, this element 5', -, +, f [is performed, and the element forming area and the element HiL area are the ratio], and the occlusal impact is formed with less. Can you do it,
Because the heart's beater is broken, the element i4 Fll'l area {;! (Thinning (1 and 2 are limited to VT). Also, regarding the definition of the impurity well region, since there is no senoreference line, the Ii ichisei un♀. tun 1 course well region 52 and 1) In determining the spacing between the regions 53, it is necessary to take into account the lateral diffusion of impurities in both well regions and the alignment error, and miniaturization has not been carried out, and the well contact region by the LOCOS method must be considered. (5
9. 60) is also an obstacle to high integration. 1
In the extension of the conventional technology and the conventional technology, although it is possible to miniaturize the element formation region, it is not possible to miniaturize the impurity P7L region including the fine impurity P7L contact region or to miniaturize the element isolation region, resulting in high integration. There was a problem that it was not possible to perform the Dakai.

[Problem to be Solved by the Invention 1 The problem to be solved by the present invention is that, as shown in the conventional example, in order to obtain an extremely highly integrated semiconductor integrated circuit,
Fine definition of the impurity well region including the fine impurity well region I and L O
It has been difficult to develop a semiconductor device that has made it possible to form a finer element isolation region that surpasses the formation of an element isolation region using the COS method. The problem is that a plurality of impurity well regions and element formation regions of opposite conductivity type formed in a semiconductor substrate of one conductivity type are defined by trenches formed deeper than the impurity well regions and buried with an insulating film. This problem is solved by a semiconductor device according to the present invention, in which the impurity well regions are connected by impurity regions of opposite conductivity type formed on the side and bottom portions of the trench.

[Function] That is, in the semiconductor device of the present invention, the plurality of impurity well regions and element formation regions are defined in self-alignment lines by wrenches that are deeper than the impurity well regions and are formed by burying an insulating film. 】゛, the impurity well region is an impurity head of the opposite conductivity type formed on the surface and bottom of the trench (4'lS'l jki() connected from 12). Therefore, element portion i:il [area 3''; L: JR oxidation, Y
Ruiwa {(1) Since it can be shaped without using the L O C O S method, there is no hard's heater that incorporates S1 Heres'! +W Since it is difficult to form
The ability to improve the withstand voltage of the oxide film (, resulting in higher performance)
High reliability can be achieved by making it difficult to be damaged by electric currents or poles, and improving carrier life. In addition, since the impurity FAR7 well region can be formed as a self-line by insulating film separation, high integration can be achieved by forming the impurity well region and boundary region including the fine impurity Jlq r'7L contact I region.・That Sochia Sopu can be improved (,
It is also possible to achieve higher performance. In addition, the junction capacitance is low because the source train region and the tube region can be formed with a height of 1 [1]. In other words, it is possible to obtain a semiconductor device which enables the formation of extremely high performance, highly reliable, high speed and highly integrated semiconductor integrated circuits.

[Example 1] Hereinafter, the present invention will be specifically explained using illustrated embodiment (c) I.

FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device (1.) of the present invention, and FIG. 2 is a schematic side sectional view of a second embodiment of a single semiconductor device of the present invention. Figure 3 (a) to (e)
) is a process cross-sectional view of an embodiment of a manufacturing method for a semiconductor device of the present invention.

Identical objects are indicated by the same reference numerals throughout. Figure 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention using a p-type silicon (Si) substrate; 10
J)--type silicon (Si) substrate of about 10 cm, 2 is an n-type impurity + fz L region of about 10 cm,
3 is a type 1 impurity r゛7 well region of about 10 cm, 4 is a trench in 1, 5 is an insulating film buried in the trench, and 6 is a low type impurity region for connection between impurity well regions of about 1016 cm. , 7 is n of about 1020cn13
+ type source drain region, 8 is 10 Cn+ -3 p+ type source drain region, 9 is 10 cnr
r of about 3]-type impurity well contact f region, 1
0 is 1511 1l1 gate oxide film, 11 is 30
12 is a block oxide film of about 5011 m, 13 is a phosphosilicate glass (PSG) film of about 800 nm, and 14 is an AI wiring of about 1.0 nm.

In the figure, a plurality of n-type impurity well regions 2 and an element formation region are formed by fine 1-wrenches (4) deeper than the n-type impurity well regions 2 and embedded in the insulation section.
, 5) are finely defined in the self-line,
A plurality of adjacent n-type impurity well regions 2 are connected by n-type impurity regions 6 formed on the side and bottom portions of the I-wrenches (4, 5). A region 9 is formed in a part of the n1 type impurity well region 2 to the n0 type impurity well contact 1, and the well voltage applied to the n0 type impurity well contact I to the region 9 is "1+ type impurity well contact 1". It is provided to a plurality of adjacent n-type impurity well regions 2 via the n-type impurity well region 2 containing the contact region 9 and the n--type impurity region 6, and all the n-type impurity P7 well regions 2 are at the same potential. Also, the n-type impurity well region 2 and the p-type impurity well region 3 are finely separated into self-alignment lines by the I~ wrench <4, 5). Therefore, the element isolation region L by selective oxidation
Since it can be formed without using the OCOS method, that is, it can be formed in a 4"^1 size without the presence of a bird's beak that causes stress, it is possible to achieve high integration by forming 113 fine elements. Improved performance by improving the withstand voltage of Elec I-ron or ball-wrapping! 9-pronged impurity well region that can enable high reliability by being less prone to cracking and improving carrier life. can be formed in a self-line by insulating film separation, which enables high integration by forming impurity well regions and boundary regions including fine impurity well contact I/regions, and high performance by improving latch-up. Furthermore, since the source train region and the channel 1 heparium region can be formed separately, it is possible to increase the speed by reducing the junction capacitance and to improve the performance by improving the junction breakdown voltage. can.

FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the invention, and 1, 3 to 5, 7, 8, 10 to 14 are the first
Same as the figure, 2a is the first n-type impurity well region, 21) is the second n-type impurity well region, and 6a is the first n-type impurity region for connection between the impurity well regions. , 6b
9a is a second n1-type impurity region for connection between impurity well regions; 9a is a first n10-type impurity well contact I-region;
9[) indicates the second n0-type impurity well contact 1- region.

In the figure, n1 type impurity well regions (2a, 2b) having two different well voltages are formed, and the first n1 type impurity well contact 1 given to the first n0 type impurity well contact region 9a is The well voltage is applied to the first n-type impurity well region 2a via the first n-type impurity region 6a, while the second well voltage is applied to the second n-type impurity well contact region 9b. The pressure is the same as in FIG. 1 except that the pressure is applied to the second n-type impurity well region 2] through the second 11-containing region 6b. In addition to the effect shown in FIG. 1, the formation of impurity well regions with different potentials and the formation of connections between impurity well regions I\ with different potentials can be easily realized.

Next, the present invention (part 1, which describes an example of the method of manufacturing such a semiconductor device)
Fig. 3 (a) A p-type silicon (S1) substrate] was sequentially grown with about 50 nm of acidic atomization 15 and about 50 nm of nitriding 16. Let. Next, using a normal photolithography technique, a nitride film 1G and an oxide film 15, 1} are selectively formed.
-- Type 1 silicon (Si) substrate] is etched to form a trench 4.Next, using a conventional photolithography technique, a resist I- (not shown) and a nitride film 1 are etched.
6 is used as a mask layer, phosphorus is ion-implanted by rotation, and n-type impurity regions 6 are selectively implanted into the side and bottom portions of the trench l1.
, this is formed 9 3rd] E1 (+1) Next, the chemical vapor phase decomposition method (to form the insulation JN5 from this, anisotropic I-lyedging) Figure 3 (C) Next, using the usual photolithography technique, mask the resist I1 (not shown) and the trenches (4, 5) filled with the insulating film 5. As a layer, phosphorus is ion-implanted to form a low-type impurity well region 2, and boron is ion-implanted to form a low-type impurity well region 1).
Type 1 impurity well regions 3 are selectively defined.

Next, the depth is adjusted by performing high-temperature treatment, and an n-type impurity well region 2 and an I)-type impurity well region 3, which are shallower than the I-wrench 4, are formed. Next, the nitride film 16 and the oxide film 15 are removed by etching. The polycrystalline silicon film 11 is patterned using the FoI lithography technique to form the Ge I electrode 11.

FIG. 3(e) Next, using the usual photoI lithography technique, 1
/JIS I (not shown), insulating film 5 and gate electrode 11
Using as a mask layer, arsenic is ion-implanted to form the rl+ type source I/in region 7 and r1+ type impurity rlz el contact region 9, and boron is ion-implanted to form the p-type source/drain region 8 and p-type impurity. A well contact region (not shown) is then selectively defined.

Next, the oxide film 10 on the unnecessary portion of the gate 1 is removed by etching. The blocking oxidation 'fI!' is then applied by applying conventional techniques. Al2 and phosphosilicate glass (PSG) II
I! 13 growth, high-temperature heat treatment to form n1 type sourced 1/in region 7, n0 type impurity well contact 1 region 9, 1) -1- type sourced I/in region 8 and p ten impurity r well contact 1 region The semiconductor device is completed by controlling the depth (not shown), forming the electrode concavity 1 to the window, and shaping the AI wiring 14.9 As shown in the above embodiments, the present invention According to the semiconductor device, the element isolation region can be formed without using the LOCOS method using selective oxidation, that is, the element isolation region can be formed into an elliptical shape 13 1/1 without a bird's beak that includes an internal space. Being able to form fine element regions (
, Elec I Heron or Hall will be able to improve the performance by improving the breakdown voltage of the gate oxide film.
This makes it possible to achieve high reliability by making the carrier less likely to be damaged and improving carrier life. In addition, since the impurity well region can be formed as a self-line by insulating film RIE, high integration can be achieved by forming impurity well regions and boundary regions including fine impurity well contact I regions, and high integration can be achieved by improving latch-up. Performance can also be improved. Furthermore, since the source/drain region and the channel stopper region can be formed separately, it is possible to increase the speed by reducing the junction capacitance and to improve the performance by improving the junction breakdown voltage.

"Effects of the Invention" As described above, according to the present invention, in a MIS type semiconductor device, a plurality of impurity well regions and element formation regions are defined by the same trench, Since it can be formed into a structure that achieves connection between the impurity well regions adjacent to the impurity regions provided at the side and bottom portions of the trench, it can be formed into a structure without device isolation regions or bird's beaks, resulting in miniaturization of the device region. , GaI-oxidation de-breakdown voltage and carrier lifetime improvement, miniaturization of the impurity well region and boundary region by forming the impurity well region on a self-aligned line, and improvement of latch-up by separating the impurity well region with an insulating film. , the impurity region for connection between the impurity well regions can be formed in a self-aligned manner, resulting in fine and easy connections between the impurity well regions, and the ability to separate the source train region from the channel I-thumper region reduces the junction capacitance and increases the junction withstand voltage. Improvements can also be made. That is, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, high-speed, and highly integrated semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of Kihatsudan, and FIGS. (e) is a process sectional view of an embodiment of the manufacturing method for a semiconductor device of the present invention, and FIG. 4 is a schematic side sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate, 2 is an n-type impurity well region, 2a is a first n-type impurity well region, and 2bi is a second n-type impurity well region.
1-type impurity well region, 3ip 1-type impurity well region, 4if ~ wrench, 5i trench-buried insulating film, 6; l n-type impurity region for connection between impurity well regions, 6a is a first type impurity region for connection between impurity well regions 61) is a second n-type impurity region for connection between impurity well regions, 7, tn+ type source train region, 8ip 10 type source I/rain region, 9, l: n 10 type source I/rain region. Impurity well contact region 9a, first n-type impurity well contact region 9b, l:
2nd n-type impurity well contact region 10 gate oxide film, 11 gate electrode, 12 i block oxide film, 13 phosphosilicate glass (PSG) film, 14. ．． iAl wiring is shown.

Claims (2)

[Claims] (1) A plurality of impurity well regions and element formation regions of opposite conductivity type formed in a semiconductor substrate of one conductivity type are defined by trenches formed deeper than the impurity well regions and filled with an insulating film, and the impurity well regions are connected by impurity regions of opposite conductivity type formed at the side and bottom portions of the trench. (2) The well voltage applied to the opposite conductivity type impurity well contact region formed in a part of the impurity well region is applied to the impurity well region containing the impurity well contact region and adjacent impurities via the impurity region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided in a well region.