JPH02291166A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02291166A JPH02291166A JP1112522A JP11252289A JPH02291166A JP H02291166 A JPH02291166 A JP H02291166A JP 1112522 A JP1112522 A JP 1112522A JP 11252289 A JP11252289 A JP 11252289A JP H02291166 A JPH02291166 A JP H02291166A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- film
- insulating films
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 241000293849 Cordylanthus Species 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 238000001020 plasma etching Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 description 14
- 108091006146 Channels Proteins 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 210000003323 beak Anatomy 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- KYARBIJYVGJZLB-UHFFFAOYSA-N 7-amino-4-hydroxy-2-naphthalenesulfonic acid Chemical compound OC1=CC(S(O)(=O)=O)=CC2=CC(N)=CC=C21 KYARBIJYVGJZLB-UHFFFAOYSA-N 0.000 description 1
- 241000272875 Ardeidae Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000384512 Trachichthyidae Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 101150107610 rimP gene Proteins 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
「１既 要」
半導体基板上に設けられる素子分離領域が、選択的に設
けられた第１の絶縁膜及び前記第１の絶縁膜の側壁にＲ
Ｊ ＩＥ （反応性イオンエッチング）法によりセル
ファラインに設けられた第２の絶縁膜とにより形成され
な紹造を有しているためバーズビークの存在しない楢造
に形成できることによる素子領域の微細化、ゲーＩ′−
酸化膜耐圧の改善及びキャリア寿命の改善を、第１の絶
縁膜段差を側壁に形成する第２の絶縁膜で緩和できるこ
とによるステップ力バレソシの良い配線体の形成を、素
子分離領域形成用絶縁膜の膜へりを最少限に抑え、配線
体の容量を減少させることによる高速化を可能とした半
導体装置。DETAILED DESCRIPTION OF THE INVENTION "1 Requirements" An element isolation region provided on a semiconductor substrate is provided with a first insulating film selectively provided and a sidewall of the first insulating film.
Since it has a structure that is not formed by the second insulating film provided on the self-line by JIE (reactive ion etching) method, it can be formed into a structure without bird's beak, which allows for miniaturization of the element area. Game I'-
The improvement of the oxide film withstand voltage and the carrier life can be alleviated by the second insulating film formed on the sidewall of the first insulating film, thereby forming a wiring body with good step force resistance. A semiconductor device that enables higher speeds by minimizing the edge of the film and reducing the capacitance of the wiring.
［産業上の利川分野］
本発明はＭＩＳ及びバイボーラ型半導体装置に係り、特
に、バーズビークのない素子分離領域を右ずる高集積な
半導体集積回路の形成を可能とした半導体装置に関する
９
従来、半導体集積回路の素子分離領域の形成は、窒化膜
を使用した選択酸化による、いわゆる１ココス法により
おこなわれてきたか、極めて集積度か上昇している今］
」、ロコス法により必ず生じてしまうスＩヘレスを誘引
ずるバーズビークにより、素子形成領域の微細化力嘆Ｌ
しい、薄膜化されなゲート酸化膜の耐圧が劣化ずる、エ
レクＩヘロン又はホールの容易なトラップにより寿命か
劣化する等の問題が顕著になってきており、高集積イヒ
への妨げになりつつある。そこでハーズビークが存在ぜ
す、しかも素子分離領域の段差を緩和した高集積な素子
分離を実現できる手段か要望されている、、［従来の技
術］
第５図は従来の半導体装置の模式側断而目１てある９５
１はＩ）−型シリコン（Ｓｉ）基板、５２は丁）型ウエ
ル領域、５｝３はｎ型ウエル領域、５４はｐ型チャネル
ストッパー領域、５５はｒｌ型ヂャネルス１〜ツバー領
域、５６はフィールＩく酸化膜、５７は丁ｌ｛型ソース
１−レイン領域、５８はｐ十型ソーストレイン領域、５
９はゲート酸化膜、６０はゲート電極、６１はブロック
用酸化膜、６２は燐珪酸ガラス（ＰＳＧ）膜、６３は八
）配線を示している、
同図において、ｐ−型シリコン（Ｓ１）基板ｊ］１に選
択的にｐ型ウエル領域５２及び１゛｝型ウエル領域５３
か設けられており、前記１つ型ウエル領域５２にはＮチ
ャネル１一ランシスタか、前記ロ型ウエル領域５３には
１）チャネル１ヘランジスタかそれそれ選択的に形成さ
れている。素子分高１１領域は四コス法により形成され
ており、スＩ−１，スを内在するバースビークが存在し
ている９１″Ｖコス法によれば、素子分離領域の段差を
バーズしークにより緩和でき、ステップ力バレッジの良
い配線体を形成できるという利点を持つが、一方、この
バーズビークの存在により、素子形成領域の微細化か難
しい、薄膜化されたゲー１−Ｍ化膜の耐圧か劣化ずる、
エレク１〜ロン又はボールの容易な１へラップにより９
ｑ命が劣化する等の欠点かある，又、ロニ７ス法による
素子分離では素子分離絶縁膜を容易には厚くてきないな
め配線容量か大きくなり、高速化には不利であるという
欠点もある，、
１介明か解決しようとする問題点］
木発明か解決しようとする問題点は、ＩＪ′（来例に示
されるように、ロコス法によるバーズビークの存在によ
り、素子形成領域の微細化か難しかっかこと、薄膜化さ
れたゲート酸化膜の耐圧が劣化ずること、エレクｒ−ロ
ン又はホールの容易なＩ−ラップにより寿命が劣化する
こと等の改善かできなかったこと及びロコス法による素
−ｊ′−分ρＩＷでは素子分離絶縁膜を容易には厚くで
きないなめ配線容量か大きくなり、高速化が達成できな
かー）たことである。[Industrial Field] The present invention relates to MIS and bibolar semiconductor devices, and particularly relates to a semiconductor device that enables the formation of highly integrated semiconductor integrated circuits with device isolation regions free of bird's beaks. Formation of element isolation regions in circuits has traditionally been carried out by selective oxidation using a nitride film, the so-called one-cos method.
'', the bird's beak that induces scratches that always occur with the Locos method reduces the ability to miniaturize the element formation area.
Problems such as deterioration of the withstand voltage of the thinner gate oxide film and deterioration of the lifespan due to the easy trapping of Elek I herons and holes are becoming more prominent, and these problems are becoming a hindrance to high integration. . Therefore, there is a need for a method that can realize highly integrated device isolation in which Her's beak exists and the level difference in the device isolation region is alleviated. [Prior art] Fig. 5 is a schematic side view of a conventional semiconductor device. There is one eye 95
1 is an I)-type silicon (Si) substrate, 52 is a D-type well region, 5}3 is an n-type well region, 54 is a p-type channel stopper region, 55 is an RL-type channel region 1 to tube region, 56 is a field 57 is a p-type source 1-rain region, 58 is a p-type source train region, 5
9 is a gate oxide film, 60 is a gate electrode, 61 is a block oxide film, 62 is a phosphosilicate glass (PSG) film, and 63 is 8) wiring. In the same figure, a p-type silicon (S1) substrate j] p-type well region 52 and 1゛}-type well region 53 selectively in 1.
In the one-type well region 52, an N-channel 1-channel transistor or in the R-type well region 53, a 1) channel 1-transistor is selectively formed. The element height 11 region is formed by the four-cos method, and according to the 91"V cos method in which there is a bird's beak containing I-1 and so, the step in the element isolation region is formed by the bird's seek. This bird's beak has the advantage of being able to relax and form a wiring body with a good stepping force barrier, but on the other hand, the presence of this bird's beak makes it difficult to miniaturize the element forming area and deteriorates the withstand voltage of the thinned Ga 1-M film. Cheating,
Elec 1 to Ron or ball easy 1 to 9 by wrap
There are disadvantages such as deterioration of Q life.Also, in element isolation using the Ronis method, the element isolation insulating film cannot be easily thickened, which increases the wiring capacitance, which is disadvantageous for increasing speed. ,, 1 Problem to be solved by the invention] The problem to be solved by the invention is IJ' (as shown in the next example, it is difficult to miniaturize the element forming area due to the presence of bird's beak in the Locos method). In addition, it was not possible to improve the breakdown voltage of the thinned gate oxide film, the deterioration of the life due to easy I-wrapping of electrons or holes, and the fact that the element-j using the Locos method could not be improved. In the case of ρIW, the device isolation insulating film cannot be easily thickened, so the wiring capacitance becomes large, and high speed cannot be achieved.
［問題点を解決するための手段］
上記問題点は、半導体基板上に選択的に設げられな第１
の絶縁膜及び前記第１の絶縁膜の｛ｉｊｌｌ壁に設けら
れた第２の絶縁膜と（、ごより素子分餅［領域が形成さ
れている本発明の半導体装置によって解決される。[Means for solving the problem] The above problem is caused by the first
This problem is solved by the semiconductor device of the present invention in which an insulating film and a second insulating film provided on the wall of the first insulating film are formed.
１作 用］
即ち木発明の半導体装置においては、半導体基板上に設
けられる素子分８ｆｆ領域が、ｊπ択的（、ご設けられ
た第１の絶縁膜及ひ前記第１の絶縁膜の側壁にＲ Ｉ
Ｅ （反応性イオンエッチンク）法（．Ｚよりセルファ
ライン（１こ設けろｉ−Ｌか第２の絶縁膜とにより形成
された’４１造を有している３、したかって、素子分離
領域を選択酸化による、いわゆるロコス法を使用せずに
形成できるなめ、即ちスＩ− １／スを内在さぜるハー
スヒークカ存在しないイ゛ＩＩ１１造に形成できるなめ
、微細な素子領域を形成できることによる高集積化を、
ゲーＩヘ酸化膜の耐圧を改善できることによる高性能化
を、工Ｉ／ク１ヘロン又はホールか１・ラップされにく
くなり、キャリアノｆ命が改善できることによる高信頼
性を可能にすることかできる。又、第１の絶縁膜段差を
側壁に形成する第２の絶縁膜で緩和できることに３Ｊ：
るステップ力バレッジの良い配線体の形成をも可能にす
ることかできる，さｌコ，に、素子分高１１領域形成川
絶縁膜の膜べりをエッチングスＩ−ツパー膜の形成によ
り、最少限に抑えることかできるなめ配線体の容量を減
少させることができることによる高速化をも可能にする
ことかできる。即ち、極めて高性能、高信頼且つ高集積
な半導体集積回路の形成を可能とした半導体装置を得る
ことかてきる、
１］実施例」
以下木発明を、図示実施例により貝体的に１；（Ｌ明ず
る３第１図は木発明に係る半導体装置の原理を示す模式
側断面図、第２１図は木発明の半導体装置にお（つる第
１の実施例の模式側断１０１国、第３レ１は本発明の半
導体装置における第２の実施例の模式｛１１１Ｊ断面図
、第．／１１ン１（ａ）へ２（ｅ）は木発明の製造方法
の一実施例の工程断面１タｌである、、全レｌを通し回
一対象物は同−１）−号で示す，第１図は■）型シリコ
ン基板を用いた際の本弁明の原理を模式的に示している
。１は１０ ｃｍ 程度のｒ）−型シリコン（＄１
）基板、２は０．８Ｐｍ程度の第１の絶縁膜、３は第２
の絶縁膜く側壁絶縁膜）、６・１は１０ ｃｍ 程
度のｐ型ウエル領域、５は１０ ｃｍ程度の丁〕型ウ
エル領域、６は１０ Ｃｎｌ 程度のｎ −１−型
ソースｒ’レイン領域、７ほ１０２０Ｃｍ−３程度ノ「
）＋型ンース１−レイン領域、８は２ ０ ｎ ｍ程度
のゲーＩ−酸化膜、９は３００ ｎｍ程度のケー１へ電
極、１（》は．’ｌｉＯｎｍ程度のフロック用酸化膜、
１１は０．８７ｍ程度の燐珪酸ガラス（＋）ＳＧ）膜、
１２はリｍＰ，ｊ度のＡＩ配線を示す，同図において、
ｐ−型シリコン（Ｓｉ）基板］に選択的に第１の絶縁膜
２か設けられており、前記第１の絶縁膜２の側壁にＲ
Ｉ Ｅ （反応性イオンエッチンク）法によりセルファ
ラインに第２の絶縁膜３か設けらノ工ており、前記第１
の絶縁膜２及び第２の絶縁膜３とにより素子分Ｍｆｔ領
域が形成されている，７したがって、素子分離領域を選
択酸化による、いわゆるロコス法を使川ぜすに形成でき
るなめ、即ちストレスを内在させるバーズビークの存在
しないｍ遣に形成できるなめ、微細な素子領域を形成で
きることによる高集積化を、ゲーＩヘ酸化膜の耐圧を改
善できることによる高性能化を、エレクＩヘロン又はホ
ールかトラップされにくくなり、キャリアＪｆ命か改善
できることによる高（，−頼性を可能にすることかでき
る。又、第１−の絶縁膜段差を側壁に形成する第２の絶
縁膜て緩和できることによるスデップカハレッジの良い
配線体の形成も可能にすることかできる。さらに、素子
分離領域形成川絶縁膜の膜べりをエッチングスＩヘツバ
ー膜の形成により、最少限に抑えることかできるなめ配
線体の容量を減少させることかできることによる高速化
をも可能（１こずることかできる．．（エリチンクスＩ
ヘツバ一ｊ模は１図示されていない、．）第２１メ１は
本介明の半導木装置（．．ｌ Ｊ；ける第１の実施例の
模式側断面図を示している，１−〜−１２は第千レ１と
同じ物を示している。1 action] That is, in the semiconductor device of the invention, an 8ff region for an element provided on a semiconductor substrate is R I
The E (reactive ion etching) method (. It can be formed by selective oxidation without using the so-called LOCOS method, that is, it can be formed into an I-II11 structure in which there is no hearthstone that contains I-1/s, and it is possible to form a fine element region, resulting in high integration. ,
It is possible to improve performance by improving the withstand voltage of the oxide film, and to achieve high reliability by making it difficult to wrap the metal or hole, and improving carrier life. . In addition, 3J: The step difference in the first insulating film can be alleviated by the second insulating film formed on the side wall.
It is also possible to form a wiring body with a good stepping force barrier.Finally, by forming an element height 11 region and etching the film thinning of the insulating film, the formation of an I-thumper film can be minimized. It is also possible to increase the speed by reducing the capacitance of the diagonal wiring body. That is, it is possible to obtain a semiconductor device that enables the formation of an extremely high-performance, highly reliable, and highly integrated semiconductor integrated circuit. (L Akizuru 3 Figure 1 is a schematic side sectional view showing the principle of the semiconductor device according to the invention, and Figure 21 is a schematic side sectional view of the semiconductor device of the invention. 3. Le 1 is a schematic cross-sectional view of the second embodiment of the semiconductor device of the present invention. Figure 1 schematically shows the principle of this defense when a ■) type silicon substrate is used. . 1 is about 10 cm r)-type silicon ($1
) substrate, 2 is the first insulating film of about 0.8Pm, 3 is the second
6.1 is a p-type well region of about 10 cm, 5 is a di]-type well region of about 10 cm, and 6 is an n-1-type source r' rain region of about 10 Cnl. , 7 about 1020cm-3
) + type non-1-rain region, 8 is about 20 nm GaI-oxide film, 9 is about 300 nm electrode to Kay 1, 1 (》 is about .'liOnm oxide film for flocking,
11 is a phosphosilicate glass (+)SG) film of about 0.87 m,
12 shows the AI wiring of rimP,j degree, in the same figure,
A first insulating film 2 is selectively provided on the p-type silicon (Si) substrate, and R is formed on the side wall of the first insulating film 2.
A second insulating film 3 is provided on the Selfa line by an IE (reactive ion etching) method, and the first insulating film 3 is
The element Mft region is formed by the insulating film 2 and the second insulating film 3.7 Therefore, the element isolation region can be formed by selective oxidation, the so-called LOCOS method, without stress. Since it can be formed in a micro pattern without the inherent bird's beak, it is possible to achieve high integration by forming a fine device area, and to improve performance by improving the withstand voltage of the oxide film. This makes it possible to improve the carrier Jf life, thereby making it possible to achieve high reliability.Also, it is possible to reduce the step difference in the first insulating film by reducing the step difference in the second insulating film formed on the sidewall. It is also possible to form a wiring body with a good edge.Furthermore, by etching the film sagging of the insulating film forming the element isolation region and forming a hetuber film, the capacitance of the slanted wiring body can be minimized. It is also possible to increase the speed by reducing the
The Hetsuba model is not shown in the figure. ) The 21st page 1 shows a schematic side sectional view of the first embodiment of the semiconductor device (..l J;) of the present invention. It shows.
同図においては、■）−型シリコン（Ｓ１）基板Ｉ（，
二選択的にｐ型ウエル領域４及ひｎ型ウエル領域５か設
けられており、前記ｐ型ウエル領域／−１にはＮチャネ
ルトランシスタが、前記ｎ型ウエル領域５にはＰチャネ
ルＩヘランジスタかそれぞれｊ巽択的に形成されている
。素子分離領域は第１図と同じ第１の絶縁膜２及ひ前記
第１の絶縁膜２の側壁にＲＪｌｅ（反応性イオンエッチ
ング）法によりセルファラインに設けられた第２の絶縁
膜３とにより形成さノ上でおり、ハーズビークか存在し
ないので、第１図同様の効果を得ることかできる。なお
同実ｈ色例においては、チャネノレス１・ツバー；ｉｆ
ｉ ＪＦ！！は１寺（・ご形成されてよ３らす、素子分
ｊｊｉｌＥ饋賎にセルファラインに形成するやや高濃度
のｐ型ウエル領域・１及ひ１１型ウエル領域５かその役
割を兼ねている４，第３図は本発明の半導体装置におけ
る第２の実施例の模式側断面図を示している。１・〜１
２は第１図と同じ物を、１３はｐ型チャネルス１・ツバ
ー領域、１４はＤ型チャネルスｌ−ツパー領域を示す。In the figure, ■)-type silicon (S1) substrate I(,
A p-type well region 4 and an n-type well region 5 are selectively provided, and the p-type well region /-1 is provided with an N-channel transistor, and the n-type well region 5 is provided with a P-channel I transistor. Each of them is formed selectively. The element isolation region is formed by the same first insulating film 2 as in FIG. 1 and a second insulating film 3 provided on the side wall of the first insulating film 2 in a self-aligned manner by RJle (reactive ion etching) method. Since it is formed on the top and there is no Her's beak, the same effect as in FIG. 1 can be obtained. In addition, in the same real h color example, if
i JF! ! The p-type well region with a slightly high concentration to be formed in the self-line in the element portion 1 and 11 type well region 5 or 4 which also serves as the role , FIG. 3 shows a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.1.~1
2 is the same thing as in FIG. 1, 13 is a p-type channel 1-tube region, and 14 is a D-type channel 1-tube region.
同図においては、チャネルスｈツパー領域の形成を除い
ては、ほほ第２図と同し構成に形成されている。ｐ型チ
ャネルストッパー領域１３及びｒｌ型チャネルス？−ツ
バー領域１４はそれそれ口十型ソースＩくレイン領域６
及びｐ十型ソーストレイン領域７とは素子分離領域の一
部を形成する第２の絶縁膜（側壁絶縁膜）の厚さたけ概
略離れて形成されており、接合容量の低減及び接合耐圧
の」二昇か期待できる。同実施例においてら、素子分硅
［．領域にはバーズビークか存在しないので、第１図同
様の効果を得ることかできる９
次いて木発明に係る半導体装置の製造方法の−実施例に
ついて第７１１タ１（，ｌ） ・へ−（ｅ）及ひ第２レ
ｊを参照して説明する９
第４図（ａ）
通常の技法を適用することにより、ｐ−型シリコン（Ｓ
ｉ）基板１に酸化膜２及び窒化膜１５を順次成長する。In this figure, the structure is almost the same as that in FIG. 2 except for the formation of the channel stopper region. p-type channel stopper region 13 and rl-type channels? - The tube region 14 has a ten-shaped source I and the rain region 6.
The p-type source train region 7 is formed approximately as far away as the thickness of the second insulating film (sidewall insulating film) forming a part of the element isolation region, thereby reducing the junction capacitance and increasing the junction breakdown voltage. I can hope for second rank. In the same embodiment, the element division [. Since there is no bird's beak in the region, it is possible to obtain the same effect as in FIG. ) and second layer j. 9 FIG. 4(a) By applying conventional techniques, p-type silicon (S
i) An oxide film 2 and a nitride film 15 are sequentially grown on the substrate 1.
第４図（ｂ）
次いで通常のフォ■へリソグラフィー技術を利用し、選
択的に前記窒化膜１５及び酸化膜２を順次エッチング除
去し、素子分離領域の一部を形成する第１の絶縁膜２、
膜べり防止膜（窒化膜）１５を形成する。次いで素子分
離領域の一部を横成ずる第２の絶縁膜３を形成するため
に化学気相成長酸化膜３を成長する。FIG. 4(b) Next, using a normal photolithography technique, the nitride film 15 and the oxide film 2 are selectively etched and removed one after another to form a first insulating film 2 that forms a part of the element isolation region. ,
A film anti-film erosion film (nitride film) 15 is formed. Next, a chemical vapor deposition oxide film 3 is grown to form a second insulating film 3 that extends over a portion of the element isolation region.
第４図（Ｃ）
次いで前記化学気相成長酸化膜３をＲ Ｉ ｌ＝： （
反応性イオンエッチング）法により異方性Ｉくライエッ
チングし、第１の絶縁膜２の側壁にセルファラインで第
２の絶縁膜（側壁絶縁膜）３を残し素子分離領域を形成
する。次いで通常のフォＩへリンクラフィー技術を利用
し、レジスＩヘ＜図示ぜず）、第１の絶縁膜２及び第２
の絶縁膜（側壁絶縁膜）３をマスク層として、硼素をイ
オン注入してｐ型ウエル領域４を、炒をイオン注入して
ｎ型ウエル領域５をそれそれ選択的に画定する。次いで
高温でランニングし所望の深さを持つｐ型ウエル領域４
及びｎ型ウエル領域５を形成ずる。FIG. 4(C) Next, the chemical vapor deposition oxide film 3 is formed by R I l=: (
Anisotropic lie etching is performed using a reactive ion etching method to form an element isolation region by leaving a second insulating film (side wall insulating film) 3 on the side wall of the first insulating film 2 in a self-aligned manner. Next, by using the usual FoI link roughy technique, the resist I (not shown), the first insulating film 2 and the second insulating film 2 are formed.
Using the insulating film (sidewall insulating film) 3 as a mask layer, boron ions are implanted to selectively define the p-type well region 4, and boron ions are implanted to selectively define the n-type well region 5. Then run at high temperature to form a p-type well region 4 with a desired depth.
Then, an n-type well region 5 is formed.
第４図（（１）
次いでゲート酸化膜８、多結晶シリコン膜を順次成長さ
せる９次いで通常のフオ１−リソグラフィー技術を利用
し、前記多結晶シリコン膜をバターニングし、ゲート電
極９を形成する。FIG. 4 ((1) Next, a gate oxide film 8 and a polycrystalline silicon film are sequentially grown.Next, the polycrystalline silicon film is patterned using a normal photolithography technique to form a gate electrode 9. .
第４図（ｅ）
次いで通常のフオＩ・リソグラフィー技術を利用し、レ
ジスト（図示せず）、第１の絶縁膜２、第２の絶縁膜（
側壁絶縁膜）３及びゲー１〜電極９をマスク層として、
砒素をイオン注入してｎ＋型ソース１くレイン領域６を
、硼素をイオン注入してｐ十型ソーストレイン領域７を
それそれ選択的に画定する。FIG. 4(e) Next, a resist (not shown), a first insulating film 2, a second insulating film (
Using sidewall insulating film) 3 and gates 1 to 9 as mask layers,
Arsenic is ion-implanted to selectively define the n+ type source 1 and drain region 6, and boron is ion-implanted to selectively define the p-type source train region 7.
第２図
次いて膜べり防止膜（窒化膜）１５をボイルした燐酸に
よりエッチング除去する９次いで不要部のゲー１ヘ酸化
膜８をエッチング除去する。次いでブロック用酸化膜１
０、熔珪酸ガラス（ＰＳＧ）膜１１を順次成長させる９
次いてやや高温処理を施し所望の深さを持つｎ十型ソー
スＦ Ｉ／イン領域６及ひ乍十型ソース■−レイン領域
７を形成する９次いで通常の技法を適用することにより
電極コンタクｒヘ窓の形成、八１配線１２の形成等をお
こない半導体装置を完成する９
上記製造方法においては、第１の絶縁膜上に膜べり防止
膜（窒化膜）を設けているか、第１の絶縁膜の側壁に第
２の絶縁膜を形成する際、第１の絶縁膜が十分残される
エツチンクか可能であれば前記膜べり防止膜（窒化膜）
は省略してもさしつかえない９又、膜べり防止膜（窒化
膜）をそのまま残し，素子分離領域形成用の第１の絶縁
膜の一部としてもよい。2. Next, the anti-film slipping film (nitride film) 15 is removed by etching with boiled phosphoric acid. 9Then, the unnecessary portions of the oxide film 8 on the gate 1 are removed by etching. Next, block oxide film 1
0. Sequential growth of fused silicate glass (PSG) film 11 9
Next, a slightly high temperature process is performed to form an n-type source F I/in region 6 and a 5-type source F I/in region 6 and a 5-type source F I/in region 7 with a desired depth.Next, by applying a conventional technique, the electrode contactor is formed. 9. Forming windows, 81 forming wiring 12, etc. to complete the semiconductor device. When forming the second insulating film on the side wall of the film, use etching to leave enough of the first insulating film, or if possible, use the film anti-slip film (nitride film).
It is also possible to omit the film anti-slip film (nitride film) as it is and use it as a part of the first insulating film for forming the element isolation region.
第３図に示されるように、素子分離領域の第１の絶縁膜
の下にチャネルス１ヘツバー領域を形成する方法は、ま
ずイオン注入により、ｐ型ウエル領域及びｎ型ウエル領
域を形成する。次いて厚い酸化膜（第１の絶縁膜となる
）、工・ソチングスＩヘツバー用の下地窒化膜、多結晶
シリコン膜及び酸化防止用の窒化膜を順次成長させる。As shown in FIG. 3, the method for forming the channel 1 hetuber region under the first insulating film in the element isolation region is to first form a p-type well region and an n-type well region by ion implantation. Next, a thick oxide film (which will become the first insulating film), a base nitride film for the I-hetuber, a polycrystalline silicon film, and a nitride film for preventing oxidation are successively grown.
次いで素子形成領域をＩ／ジス１ヘてマスクし、素子分
離領域の酸化防止用の窒化膜をエッチング除去後、硼素
をイオン注入してチャネルスＩヘツパー領域を形成する
９次いでＩ／ジス■〜を除去し、露出した素子分離領域
の多結晶シリコン膜を酸化し、酸化膜に変える。次いで
前記酸化膜をマスク層として素子形成領域の窒化膜、多
結晶シリコン膜、下地窒化膜を順次エッチング除去する
。次いで酸化膜を全面エッチングすれば素子形成領域は
シリコン基板が露出し、一方、素子分離領域はエッチン
グス■ヘツパー用の下地窒化膜のために厚い酸化膜を残
すことができる。即ち、下部にチャネルストッパー領域
を有する第１の絶縁膜が形成できる。以後は前記実施例
の製造方法に準ずる。Next, the element formation region is masked with I/DIS 1, and the nitride film for preventing oxidation in the element isolation region is etched away, and boron ions are implanted to form a channel I hepar region. The polycrystalline silicon film in the exposed element isolation region is oxidized and converted into an oxide film. Next, using the oxide film as a mask layer, the nitride film, polycrystalline silicon film, and base nitride film in the element formation region are sequentially removed by etching. Next, by etching the entire surface of the oxide film, the silicon substrate is exposed in the element forming region, while a thick oxide film can be left in the element isolation region as a base nitride film for the etching process. That is, a first insulating film having a channel stopper region underneath can be formed. Thereafter, the manufacturing method of the above embodiment is followed.
以上実施例に示したように、本発明の半導体装置によれ
ば、素子分離領域を選択酸化による、いわゆる口二７ス
法を使川ぜずに形成できるため、即ちス１・レスを内在
さぜるバーズビークの存在しないイ溝造に形成できるた
め、微細な素子領域を形成できることによる高集積化を
、ケーＩヘ酸化膜θ）耐圧を改善できることによる高性
能化を、エレクＩ・ロン又はホールが１へラップされに
くくなり、キャリア寿命が改善できることによる高偕頼
性を可ｆｆＵにずることかてきる９又、第１の絶縁膜段
差を側壁に形成する第２の絶縁膜で緩和できることによ
るステップカハＩ／ツジの良い配線体の形成も可能にす
ることかできる。さらに、素子分ｔｌｌｆ．領域形成川
絶縁膜の膜べりをエッチングスｈ ツパー膜の形成によ
り、最少限に抑えることができるため配線体の容量を減
少させることかできることによる高速化をも可能にする
ことかできる９
［介明の効果］
以上説明のように木発明によれば、Ｍ Ｉ Ｓ及びハイ
ボーラ型半導体装置において、第１の絶縁膜及び前記第
１の絶縁ｊ模の側壁にセルファラインに設けられた第２
の絶縁膜とにより素子分離領域か形成されているため、
バースビークの存在しない楢造に形成できることによる
素子領域の微細化、ゲート酸化膜耐圧の改善及びキャリ
ア’Ｍ命の改善を、第１の絶縁膜段差を側壁に形成する
第２の絶縁膜で緩和できることによるステップカバＩ／
ツジの良い配線体の形成を、素子分離領域形成用絶縁膜
の膜べりを最少限に抑え、配線体の容量を減少させるこ
とによる高速化を可能にすることかできる９即ち、碌め
て高性能、高信頼「１．つ高集積を併せ持つ半導体集積
回路を得ることかできる。As shown in the embodiments above, according to the semiconductor device of the present invention, an element isolation region can be formed by selective oxidation without using the so-called 27-strip method, that is, it is possible to form an element isolation region by selective oxidation without using any internal scratches. Since it can be formed in a groove structure without a bird's beak, it is possible to achieve high integration by forming a fine element area, and to improve performance by improving the breakdown voltage of the oxide film θ). This makes it difficult for carriers to be wrapped into 1 and improves the carrier life, which makes it possible to increase the reliability to ffU. It is also possible to form a wiring body with good step strength. Furthermore, the element tllf. By forming a region forming layer and an insulating film, film erosion of the insulating film can be minimized by etching. This also makes it possible to increase the speed by reducing the capacitance of the wiring body9. [Bright Effect] As explained above, according to the invention, in the MIS and high-vola semiconductor devices, the second insulating film and the second insulating layer provided in the self-alignment line on the side wall of the first insulating pattern are
Since an element isolation region is formed by the insulating film,
The miniaturization of the element region, improvement of gate oxide film breakdown voltage, and improvement of carrier 'M life due to the ability to form a structure with no birth beaks can be alleviated by the second insulating film formed on the sidewall of the first insulating film step. Step Cover I/
It is possible to increase the speed of forming a wiring body with good stiffness by minimizing the film deterioration of the insulating film for forming an element isolation region and reducing the capacitance of the wiring body9. It is possible to obtain a semiconductor integrated circuit that has both high performance and high reliability.
第１図は木発明の゛１′．導体装置の原理を示す模式側
断面図、第２国は本発明の半導体装置における第１−の
実施例の模式側断面レ１、第３図は木発明の半導体装置
における第２の実施例の模式側断面レｌ、第４レ１（ａ
）・へ２（ｅ）は本発明の半導体装置における製造方法
の−実施例の二「稈断面国、第５レ１は１７（来の半導
体装置の模式側断面Ｎである。
図において、
］ よ丁）−型シリコン・（Ｓｉ）基４反、２士第１の
絶縁膜、
３，１：第２の絶縁膜（側壁絶縁股）、・１１Ｙ）型ウ
エル饋域、
５土１１型ウエル饋域、
６．．ｉ：ロ十型ソースＩヘレイン領域、７ ｊ ｐ−
１型ソース１くレイン領域、８１ゲ゛一Ｉ−酸１ヒｊ模
、
９ｉケーＩへ電極、
１０＝Ｉｉ：ブロック用酸化ｊ模、
１１土禁珪酸力゛ラス（ＰＳＧ） Ｉ摸、１２１八１配
ｔ泉、
１３；ｌｐ型チャネルスＩ・ツバー領域、１／Ｉま１１
型チャネルスＩ・ツパー領域、１！＋ｊｌ模べり防止１
模（窒化ｊ模）を示ず，Figure 1 is ``1'' of the wooden invention. A schematic side cross-sectional view showing the principle of a conductor device, the second figure is a schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic side cross-sectional view of the second embodiment of the semiconductor device of the invention. Schematic side cross-section level l, fourth level 1 (a
)・2(e) is the second embodiment of the manufacturing method for the semiconductor device of the present invention. 4-type silicon (Si)-based, 2-layer first insulating film, 3,1: second insulating film (side wall insulation crotch), 11Y)-type well space, 5-type 11-type well region, 6..i: Lox-type source I region, 7 j p-
1 type source 1 drain region, 81 Ge I-acid 1 Hj model, 9i K I electrode, 10 = Ii: Block oxide J model, 11 Soil-free silicate glass (PSG) I model, 121 81 distribution, 13; lp type channels I/tuber region, 1/I and 11
Type Channels I Thupah area, 1! +jl imitation prevention 1
It does not show any pattern (nitride pattern),
Claims (2)
及び前記第１の絶縁膜の側壁に設けられた第２の絶縁膜
とにより素子分離領域が形成されていることを特徴とす
る半導体装置。(1) An element isolation region is formed by a first insulating film selectively provided on a semiconductor substrate and a second insulating film provided on a side wall of the first insulating film. semiconductor devices.
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。(2) The semiconductor device according to claim 1, wherein the first insulating film is composed of a plurality of different insulating films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1112522A JP2608470B2 (en) | 1989-05-01 | 1989-05-01 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1112522A JP2608470B2 (en) | 1989-05-01 | 1989-05-01 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02291166A true JPH02291166A (en) | 1990-11-30 |
| JP2608470B2 JP2608470B2 (en) | 1997-05-07 |
Family
ID=14588751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1112522A Expired - Lifetime JP2608470B2 (en) | 1989-05-01 | 1989-05-01 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2608470B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028361A (en) * | 1994-03-14 | 2000-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing of semiconductor device having low leakage current |
| US6414352B2 (en) | 1997-09-11 | 2002-07-02 | Nec Corporation | Semiconductor device having an electronically insulating layer including a nitride layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972759A (en) * | 1982-10-20 | 1984-04-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60234326A (en) * | 1984-05-07 | 1985-11-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPH027558A (en) * | 1988-06-27 | 1990-01-11 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
-
1989
- 1989-05-01 JP JP1112522A patent/JP2608470B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972759A (en) * | 1982-10-20 | 1984-04-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60234326A (en) * | 1984-05-07 | 1985-11-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPH027558A (en) * | 1988-06-27 | 1990-01-11 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028361A (en) * | 1994-03-14 | 2000-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing of semiconductor device having low leakage current |
| US6514834B2 (en) | 1994-03-14 | 2003-02-04 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having a low leakage current |
| US6414352B2 (en) | 1997-09-11 | 2002-07-02 | Nec Corporation | Semiconductor device having an electronically insulating layer including a nitride layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2608470B2 (en) | 1997-05-07 |
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