JPH023257A - Semiconductor device having field shield structure and its manufacture - Google Patents

Abstract

PURPOSE:To prevent generation of short-circuit of an electrode and enable improvement of pressure resistance and reduction of capacity by inclining the side face of a conductive layer which constitutes a field shield, and controlling the thickness of an insulation layer provided on the conductive layer independently. CONSTITUTION:The sidewall of a conductive layer 12 in an opening 13 is made into a slant 15 that inclines gradually to the outside of an element formation area 14 toward the upside of an opening 13. A gate electrode 17 has a part that extends above the slant 15 of the conductive layer 12. This extension part is insulated from the conductive layer 12 by an insulation layer 16 which is formed by oxidizing the surface of the conductive layer 12. On the conductive layer 12 and the gate electrode 17 is formed an interlayer insulation layer 20. That is, even if the gate electrode 17 is patterned by anisotropic etching, a conductive substance does not remain at the slant 15, and these is no fear of the gate electrode 17 and the silicon substrate 10 being short-circuited. Also, since the insulation layer 16 and the gate insulation layer 18 are formed in separate processes, the insulation layer 16 can have enough thickness, and the desired pressure resistance is given to between the conductive layer 12 and the gate electrode 17, and also the capacity between these is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device having a field shield structure in which element isolation is performed using an electric field.

The conductive layer constituting the field shield is formed on a semiconductor substrate with an insulating layer interposed therebetween for the purpose of improving the insulation between the conductive layer constituting the field shield and the electrode having an extended portion formed thereon. , an element formation region consisting of a conductive substrate exposed in an opening provided at a predetermined position of the conductive layer, and a side wall portion of the conductive layer within the opening, gradually increasing toward the top of the opening. an inclined surface that slopes outside the element formation region; a semiconductor element formed in the element formation region;
The electrode constitutes the semiconductor element and includes an electrode having an extended portion formed on the inclined surface with a second insulating layer interposed therebetween.

[Industrial application field]

The present invention relates to a semiconductor device having a field shield structure in which elements are separated by an electric field.

[Conventional technology]

LOGO5 (Local Oxidation of
In the local selective oxidation method called 5ilicon), the bird's beak inevitably digs into the element formation region.

There are limits to the increasing density of integrated circuits. In contrast, a method of separating elements using a trench structure is being considered, but it is not widely used at present due to the difficulty of precision machining of trenches and the complexity of the process.

On the other hand, by surrounding the element formation region with a conductive layer and forming an electric field between this electrosensitive layer and the substrate, the elements are isolated.
A so-called field shield method has been proposed for a long time. The field shield method has a relatively simple structure and formation process, and is suitable for high integration in terms of structure.

[Problem to be solved by the invention]

The structure and formation process of the conventional field shield
This will be explained with reference to FIGS. 8 through 8 to clarify the problems.

As shown in FIG. 6 (al), first, a silicon substrate 1 is thermally oxidized, and an SiO□ insulating layer 2 is formed on its surface.
Furthermore, a polycrystalline silicon layer 3 is deposited.

If necessary, the polycrystalline silicon layer 3 is doped with impurities to make it low in resistance.

Next, after patterning the polycrystalline silicon layer 3 into the shape of a field shield, the exposed portion of the SiO□ insulating layer 2 is removed. Then, as shown in Figure 6 (bl),
A SiO□ gate oxide film 4 having a thickness of approximately 300 mm is formed on the exposed surface of the silicon substrate 1 by thermal oxidation. In this step, an oxide film 41 is also generated on the surface of the patterned polycrystalline silicon layer 31. Polycrystalline silicon layer 31
A region 5 surrounded by is an element formation region.

Assuming that, for example, a MOS-FET is to be formed in the element formation region 5 after the above, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 1, and impurities are doped into this polycrystalline silicon layer as necessary to make the resistance low. After that, this is patterned into a predetermined shape and shape as shown in Figure 6 FC+.
A gate electrode 6 having the following dimensions is formed.

FIG. 7 is a perspective view showing the structure immediately after the step described in FIG. 6(C), and FIG. 8 is a partial cross-sectional view of the polycrystalline silicon layer 31 constituting the field shield after the gate electrode 6 is formed.

In FIG. 7, predetermined impurities are implanted into the surface of the silicon substrate 1 exposed within the element formation region 5 to form source/drain regions 7. Thereafter, a MOS-FET separated by a field shield is completed by forming a glabella insulating layer, forming contact holes for the source/drain regions 7, etc. in accordance with five normal steps.

By the way, anisotropic etching is used for patterning the polycrystalline silicon layer 3 in the step explained in FIG. 6(b) because microfabrication is required.

As a result, the patterned polycrystalline silicon layer 31
The side surfaces of the silicon substrate 1 are substantially perpendicular to the silicon substrate 1. Therefore, in the sixth (C) step.

Again, the polycrystalline silicon layer is patterned into the shape of the gate electrode 6 by anisotropic etching.

As shown in FIG. 8, a polycrystalline silicon sidewall 61 is formed as a residue on the side surface of the polycrystalline silicon layer 31.

This phenomenon is actively utilized as a method for forming sidewalls such as insulating layers on the side surfaces of electrodes and the like using anisotropic etching. However, in forming the field shield, formation of the polycrystalline silicon sidewall 61 is not preferred. This is because, since the polycrystalline silicon sidewall 61 is electrically connected to the gate electrode 6, there is a risk that the gate electrode 6 and the source/drain lead electrodes may be short-circuited.

In addition, in the conventional field shield structure described above,
The polycrystalline silicon layer 31 and the gate electrode 6 are insulated by an oxide film 41, but the thickness of the oxide film 41 is determined by that of the gate oxide film 4 and cannot be set freely. Therefore, the polycrystalline silicon layer 31
There was a problem that the withstand voltage between the gate electrode 6 and the gate electrode 6 was insufficient, and the capacitance between them was large.

An object of the present invention is to provide a field shield structure that can solve the problems in the conventional field shield structure described above.

[Means to solve the problem]

The above object is to provide an element comprising a conductive layer constituting a field shield formed on a semiconductor substrate via an oxidation-resistant insulating layer, and the semiconductor substrate exposed in an opening provided at a predetermined position of the conductive layer. a semiconductor element formed in the element formation area; A semiconductor device having a field shield structure according to the present invention, characterized in that the electrode constitutes a semiconductor element and includes an electrode having an extended portion formed on the inclined surface with a second insulating layer interposed therebetween. and a step of forming an oxidation-resistant insulating layer on the semiconductor substrate, a step of forming a second conductive layer constituting a field shield on the oxidation-resistant insulating layer, and an oxidation-resistant mask layer on the conductive layer. patterning the oxidation-resistant mask layer so that the field shield forming portion of the conductive layer is masked; and exposing the conductive layer with the field shield forming portion masked to an oxidizing atmosphere. a step of converting the conductive layer other than the field shield forming portion into an oxide layer by heat treatment in the inside, a step of sequentially selectively removing the oxidation-resistant mask layer and the oxide layer, and a step of sequentially selectively removing the oxidation resistant mask layer and the oxide layer remaining as the field shield forming portion. The method is characterized by comprising a step of oxidizing the surface of the conductive layer to form a surface insulating layer, and a step of selectively removing the oxidation-resistant insulating layer exposed around the field shield forming portion. This is achieved by the method for manufacturing a semiconductor device having a field shield structure according to the present invention.

[For production]

LO the polycrystalline silicon layer that makes up the field shield.
Patterning is performed by applying the CO5 method. As a result, the bird's beak digs into the polycrystalline silicon layer in the field shield formation region, and the side surfaces of the field shield become sloped surfaces. Therefore, even if an electrode having an extended portion provided on the field shield is patterned by anisotropic etching, no residue of the electrode material will be generated on the sloped surface, and the electrode and the source/drain in the element forming region will not remain. A short circuit with the extraction electrode is less likely to occur. Also.

By providing an oxidation-resistant insulating layer in advance between the polycrystalline silicon layer that makes up the field shield and the substrate, the surface of the polycrystalline silicon layer that makes up the field shield is oxidized to form an insulating layer of the desired thickness. Thereafter, the oxidation-resistant insulating layer can be selectively removed to form a gate oxide film having a desired thickness on the surface of the substrate in the element formation region.

That is, the thickness of the insulating layer between the field shield and the electrode can be controlled independently of that of the gate oxide film, making it possible to improve breakdown voltage and reduce capacitance.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) shows an example of a semiconductor device according to the present invention.
Schematic plan view showing the structure of a MOS transistor separated by a field shield, FIG.
C1 is a schematic XX sectional view and YY sectional view in FIG. 1(a).

Referring to FIG. 1(a) to C), silicon substrate 1
A conductive layer 12 made of, for example, polycrystalline silicon, which constitutes a field shield, is placed on the surface of the film through an oxidation-resistant insulating layer 11 made of, for example, 5i3Na (nitrogen silicon).
is formed. An opening 13 is formed in a predetermined region of the conductive layer 12.
is formed, and the silicon substrate 10 exposed within this opening 13 is used as an element formation region 14. opening 1
The sidewall of the conductive layer 12 in the slanted surface 1 gradually slopes toward the outside of the element formation region 14 toward the upper side of the opening 13.
It is 5.

The element formation region 14 includes a gate electrode 17 that faces the silicon substrate 10 via a gate insulating layer 18 made of SiO□ (silicon dioxide) formed by thermally oxidizing the surface of the silicon substrate 10, and substrates on both sides of the gate electrode 17. An MO consisting of source/drain regions 19 formed by implanting impurities into
S transistor is formed.

Gate electrode 17 has a portion extending onto inclined surface 15 of conductive layer 12 . The extended portion and the conductive layer 12 are insulated by an insulating layer 16 formed by oxidizing the surface of the conductive layer 12. An interlayer insulating layer 20 is formed on the conductive layer 12 and the gate electrode 17. moreover.

Wiring layers 21 and 22 are formed which are connected to gate electrode 17 and source/drain region 19, respectively, through contact holes provided in interlayer insulating layer 20.

In the field shield structure consisting of the conductive layer 12 shown in FIG. 17 and the silicon substrate 10 are not likely to be short-circuited. Further, since the insulating layer 16 and the gate insulating layer 18 are formed in separate steps, the insulating layer 16 can have a sufficiently large thickness.
A desired breakdown voltage is provided between the conductive layer 12 and the gate electrode 17, and the capacitance between them is reduced.

FIG. 2 is a sectional view of a main part in the step of forming the field shield shown in FIG. 1, and the same parts as in FIG. 1 are designated by the same reference numerals.

Referring to FIG. 2 (al), on a silicon substrate 10 there is an oxidation-resistant insulating layer 11 made of, for example, 5isNa, about 1,000 thick and a conductive layer 12 of about 4,000 thick made of polycrystalline silicon, for example. are sequentially formed, and further one conductive layer 12 is formed.
An oxidation-resistant mask layer 23 of 1,000 thick, for example, 5iJ4 is formed thereon. These formations are known as C
The polycrystalline silicon conductive layer F112 may be doped with an appropriate impurity to impart conductivity to the polycrystalline silicon conductive layer F112 by using a VD (chemical vapor deposition) method. Impurity ions may be implanted after formation.

Then, the upper layer 5iJ4 was formed using 9 well-known lithographic techniques.
As shown in FIG. 2(b), the oxidation-resistant mask layer 23 is
After patterning so that the field shield forming portion is masked, the polycrystalline silicon conductive layer 12 is oxidized in an oxidizing atmosphere under the same conditions as the normal LOCOS method. As a result, as shown in Figure 2 (C),
The portion of the conductive layer 1 exposed from the oxidation-resistant mask layer 23
2 is converted into a SiO□ layer 24. Oxidation-resistant mask layer 2
The polycrystalline silicon conductive layer 12 below 3 is also partially oxidized.
Bird's beaks occur as in the normal LOCO3 method. therefore.

The side surface of the conductive layer 12 remaining under the oxidation-resistant mask layer 23 becomes an inclined surface 15.

After the above, the oxidation-resistant mask layer 23 and the SiO□ layer 2
4 are sequentially and selectively removed. In the case of the 5iJ4 oxidation-resistant mask layer 23, the well-known etching method of dipping in hot phosphoric acid may be used;
Etching may be performed using a (hydrofluoric acid) solution.

Polycrystalline silicon conductive layer 12 exposed by the above removal process
As shown in FIG. The silicon substrate 10 in the region is protected.

Next, the oxidation-resistant insulating layer 11 exposed around the conductor 112 is selectively removed. SiJ, oxidation-resistant insulating layer 11
In this case, the hot phosphoric acid immersion method described above may be used. In this way, the structure shown in FIG. 2 is obtained. The figure shows a part of the field shield, and in reality, the second
A conductive layer 12 having the structure shown in FIG. 1E is formed to surround an element formation region 14, as shown in FIG. A semiconductor element is formed.

FIG. 3 is a cross-sectional view of a main part in another embodiment of the step of forming the field shield shown in FIG. 1, and the same parts as in the first previous figure are designated by the same reference numerals.

In this embodiment, as shown in FIG. 3(a).

A SiO□ layer 2 with a thickness of approximately 300 mm is formed on a silicon substrate 10.
After forming 5 layers, apply the same procedure as in the previous example.

An oxidation-resistant insulating layer 11 made of, for example, Si3N4. Conductive layer 12 made of polycrystalline silicon. An oxidation-resistant mask layer 23 made of Si3N is sequentially formed. It may be formed by thermally oxidizing the SiO□ layer 25 layer type 5-con board 10. Also.

The conductive layer 12 is imparted with conductivity in the same manner as in the previous embodiment.

After the above, the oxidation-resistant mask layer 23 was patterned as shown in FIG. 3(C) in the same manner as in the previous example. The polycrystalline silicon conductive layer 12 is selectively oxidized using the oxidation-resistant mask layer 23 as a mask.Then, the oxidation-resistant mask layer 23 and the SiOg layer 25 produced by the selective oxidation are sequentially and selectively removed. Obtain the structure shown in dl.

In this embodiment, following the above steps, the oxidation-resistant insulating layer 11 is patterned so as to mask the element formation region separated by one ordinary LOGOS isolation insulating layer. 1. The surface of the silicon substrate 10 is subjected to normal LOCO
Thermal oxidation is performed under the conditions of the three methods to form a one-separation insulating layer 26 as shown in FIG. The initial thickness of the silicon conductive layer 12 is 1, for example, 4000.
Assuming that the thickness of one isolation insulating layer 26 is 3000 people,
The thickness of SiO□iO□16 is about 4000 people,
Beneath this remains a polycrystalline silicon conductive layer 12 approximately 2000 nm thick.

After the above, the oxidation-resistant insulating layer 11 exposed on the silicon substrate 10 is selectively removed to obtain the structure shown in FIG. 3(f). That is, a region separated by the field shield formed by the conductive layer 12 and a region separated by the isolation insulating layer 26 formed by the LOCO5 method are formed on the same silicon substrate 10, and each region has nine MOS l-transistors (not shown). , bipolar transistors, etc. are formed as appropriate.

In the above embodiment, 25 layers of SiO□ layer type 5, LOC
When forming the isolation insulating layer by the O5 method, Si3N
This is provided for the purpose of alleviating the lattice strain on the silicon substrate surface caused by the 4 oxidation-resistant insulating layer.

FIG. 4 is a sectional view of a main part in a step of still another embodiment of the present invention, and the same parts as in the previous figures are designated by the same reference numerals.

In the embodiment of the present invention, in the same manner as in the embodiment shown in FIG. As shown in the figure, the thickness is about 300 people.
An iOz layer 27 is formed, and an oxidation-resistant mask layer 23 made of Si, N, etc. is formed thereon in the same manner as in each of the above embodiments.
form. For example, a thermal oxidation method may be used for forming the SiO□ layer 25 layer type 5.

Next, in the same manner as in the previous embodiment, the oxidation-resistant mask layer 23 was patterned as shown in FIG. 4 fb), and then the conductive layer 12 was thermally oxidized by the LOCO5 method.

As shown in FIG. 4(C), a SiO□ layer 24 is generated.
Next, the oxidation-resistant mask layer 23 and the SiO□ layer 24 are selectively removed in sequence. Then, the exposed surface of the conductive layer 12 is thermally oxidized to form a SiO□i layer as shown in FIG. 4(d).
After forming the O□ 16, the oxidation-resistant insulating layer 11 exposed around the conductive layer 12 is removed to obtain the structure shown in FIG. 4(e).

According to this embodiment, when forming the 5i02 layer 24.

Since oxygen is easily supplied under the oxidation-resistant mask layer 23 through the 5i02 layer 27, the amount of penetration of the bird's beak increases, and the conductive I constituting the field shield increases.
There is an advantage that the slope of the side surface of J12 becomes gentler. Note that this embodiment is similar to the embodiment described in FIG. 3, provided that an SiO□ layer is interposed between the silicon substrate 10 and the oxidation-resistant insulating layer 11.

A region separated by the LOGO5 isolation insulating layer and a region separated by the field shield can be formed on the same silicon substrate.

FIG. 5 is a sectional view of a main part in a step of still another embodiment of the present invention, and the same parts as in the previous figures are designated by the same reference numerals.

As shown in FIG.
4. Form oxidation-resistant mask layers 23 in sequence. The thickness of each layer is the same as in each of the above embodiments.

In this example, as shown in FIG.

Oxidation-resistant mask layer 23. SiO□ layer 27. Conductive layer 12
is patterned so that it remains in the field shield forming area. This patterning is performed using an oxidation-resistant mask 12.
3 is made of Si3N4, the oxidation-resistant mask layer 23 is first patterned using a well-known lithography technique, and then the Si02 layer 27 and the polycrystalline silicon conductive layer 27 are patterned using the Si,N4 oxidation-resistant mask layer 23 as a mask. layer 1
2 may be etched sequentially.

Next, the conductive layer 12 is partially oxidized by heat treatment in an oxidizing atmosphere, and as shown in FIG. 5(C),
24 SiO□ layers are placed on top. As in each of the above embodiments, the conductive layer 12SiO□ under the oxidation-resistant mask layer 23
The bird's beak of layer 24 penetrates, and the side surfaces of conductive layer 12 become sloped surfaces. After this, the oxidation-resistant mask layer 23 and the SiO
□The upper layer 427 of the layer 24 is sequentially selectively removed, and the exposed surface of the polycrystalline silicon conductive layer 12 is thermally oxidized.
As shown in FIG. 5(d), a Sing insulating layer 16 is formed. Furthermore, the oxidation-resistant insulating layer 11 exposed around the conductive layer 12 is selectively removed to obtain the structure shown in FIG.

According to this embodiment, the advantages of the embodiments shown in FIGS. 3 and 4 can be obtained, as well as the advantages shown in FIGS.
), since the conductive layer 12 is patterned so that only the field shield forming portion remains before the thermal oxidation process, the warpage of the silicon substrate 10 due to the difference in thermal expansion coefficient with the 5in2 layer 24 is reduced. Benefits can be obtained.

In the above embodiment, the process of forming MOS transistors separated by a field shield was explained as an example, but it goes without saying that the field shield structure of the present invention can be applied to the separation of bipolar transistors.

〔Effect of the invention〕

According to the present invention, since the side surface of the conductive layer constituting the field shield is an inclined surface, it is possible to prevent a short circuit between an electrode having an extended portion provided on the field shield and the conductive layer constituting the field shield. Furthermore, since the thickness of the insulating layer provided on the conductive layer constituting the field shield can be independently controlled, it is possible to provide a sufficiently large breakdown voltage between the electrode and the conductive layer. moreover.

Element formation region and L separated by field shield
Element formation regions separated by the OCOS method can be formed on the same substrate through a common process. As a result, it has the effect of promoting higher density and multifunctionality of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view and a cross-sectional view showing the structure of a MOS transistor separated by a field shield according to the present invention. FIG. 2 is a sectional view of essential parts in an embodiment of the step of forming the field shield shown in FIG. 1. 3 to 5 are sectional views of main parts in steps of another embodiment of the present invention. FIG. 6 is a sectional view of a main part for explaining a conventional field shield structure forming process. FIG. 7 is a perspective view showing the structure of a MOS transistor formed by the process of FIG. 6. FIG. 8 is a partial cross-sectional view of the field shield in the structure of FIG. 7. In fig. 1 and lO are silicon substrates. 2, 24, 25, 27, and 41 are SiO□ layers. 3 and 31 are polycrystalline silicon layers. 4 and 18 are gate oxide films. 5 is an element forming area. 6 and 17 are gate electrodes. 7 and 19 are source/drain regions. 11 is an oxidation-resistant insulating layer 12 is a conductive layer. 13 is an opening. 14 is an element forming area. 15 is an inclined surface 16 is an insulating layer 20 is an interlayer insulating layer. 21 and 22 are wiring layers. 23 is an oxidation-resistant mask layer. 26 is an isolation insulating layer. 61 is a polycrystalline silicon side wall. 7 dead moon field ~ Le F't - 7 minutes thin N
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Claims (2)

[Claims] (1) Formation of an element consisting of a conductive layer constituting a field shield formed on a semiconductor substrate via an oxidation-resistant insulating layer, and the semiconductor substrate exposed in an opening provided at a predetermined position in the conductive layer. a semiconductor element formed in the element formation area; 1. A semiconductor device having a field shield structure, comprising an electrode constituting a semiconductor element and having an extended portion formed on the inclined surface with a second insulating layer interposed therebetween. (2) forming an oxidation-resistant insulating layer on the semiconductor substrate; forming a conductive layer for forming a field shield on the oxidation-resistant insulating layer; and forming an oxidation-resistant mask on the conductive layer. patterning the oxidation-resistant mask layer so that the field shield forming portion of the conductive layer is masked; and exposing the conductive layer with the field shield forming portion masked to an oxidizing atmosphere. a step of converting the conductive layer other than the field shield forming portion into an oxide layer by heat treatment in the inside, a step of sequentially selectively removing the oxidation-resistant mask layer and the oxide layer, and a step of sequentially selectively removing the conductive layer remaining as the field shield forming portion. The method is characterized by comprising the steps of: oxidizing the surface of the conductive layer to form a surface insulating layer; and selectively removing the oxidation-resistant insulating layer exposed around the field shield forming portion. A method for manufacturing a semiconductor device having a field shield structure.